| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-addrmode.ll | 28 ; base + unsigned offset (> imm9 and <= imm12 * size of type in bytes)
38 ; base + unsigned offset (> imm12 * size of type in bytes)
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| /external/v8/src/arm64/ |
| D | assembler-arm64-inl.h | 1142 Instr Assembler::ImmLSUnsigned(int imm12) {
1143 DCHECK(is_uint12(imm12));
1144 return imm12 << ImmLSUnsigned_offset;
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| D | assembler-arm64.h | 1738 inline static Instr ImmLSUnsigned(int imm12);
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| /external/valgrind/VEX/priv/ |
| D | host_arm64_defs.h | 164 UShort imm12; /* 0 .. 4095 */ member
174 extern ARM64RIA* ARM64RIA_I12 ( UShort imm12, UChar shift );
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| D | guest_arm_toIR.c | 2369 IRExpr* mk_EA_reg_plusminus_imm12 ( UInt rN, UInt bU, UInt imm12, in mk_EA_reg_plusminus_imm12() argument
2374 vassert(imm12 < 0x1000); in mk_EA_reg_plusminus_imm12()
2376 DIS(buf, "[r%u, #%c%u]", rN, opChar, imm12); in mk_EA_reg_plusminus_imm12()
2380 mkU32(imm12) ); in mk_EA_reg_plusminus_imm12()
14472 UInt imm12 = INSN(11,0); in decode_NV_instruction() local
14475 DIP("pld%c [r%u, #%c%u]\n", bR ? ' ' : 'w', rN, bU ? '+' : '-', imm12); in decode_NV_instruction()
14507 UInt imm12 = INSN(11,0); in decode_NV_instruction() local
14509 DIP("pli [r%u, #%c%u]\n", rN, bU ? '+' : '-', imm12); in decode_NV_instruction()
15114 UInt imm12 = (insn >> 0) & 0xFFF; /* 11:0 */ in disInstr_ARM_WRK() local
15146 eaE = mk_EA_reg_plusminus_imm12( rN, bU, imm12, dis_buf ); in disInstr_ARM_WRK()
[all …]
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| D | host_arm64_defs.c | 305 ARM64RIA* ARM64RIA_I12 ( UShort imm12, UChar shift ) { in ARM64RIA_I12() argument
308 riA->ARM64riA.I12.imm12 = imm12; in ARM64RIA_I12()
310 vassert(imm12 < 4096); in ARM64RIA_I12()
324 vex_printf("#%u",(UInt)(riA->ARM64riA.I12.imm12 in ppARM64RIA()
3274 argR->ARM64riA.I12.imm12, rN, rD in emit_ARM64Instr()
3302 argR->ARM64riA.I12.imm12, rN, rD); in emit_ARM64Instr()
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| D | guest_arm64_toIR.c | 5025 UInt imm12 = INSN(21,10); in dis_ARM64_load_store() local
5030 getIReg64orSP(nn), mkU64(imm12 * szB)); in dis_ARM64_load_store()
5036 nameIReg64orSP(nn), imm12 * szB); in dis_ARM64_load_store()
5046 nameIReg64orSP(nn), imm12 * szB); in dis_ARM64_load_store()
5056 nameIReg64orSP(nn), imm12 * szB); in dis_ARM64_load_store()
6403 UInt imm12 = INSN(21,10); in dis_ARM64_load_store() local
6409 assign(ea, binop(Iop_Add64, getIReg64orSP(nn), mkU64(imm12 * 8))); in dis_ARM64_load_store()
6410 DIP("prfm prfop=%u, [%s, #%u]\n", tt, nameIReg64orSP(nn), imm12 * 8); in dis_ARM64_load_store()
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| D | host_arm64_isel.c | 925 vassert(ri->ARM64riA.I12.imm12 < 4096); in iselIntExpr_RIA()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 804 // addrmode_imm12 := reg +/- imm12
880 // addrmode2 := reg +/- imm12
1712 let Inst{11-0} = addr{11-0}; // imm12
1743 let Inst{11-0} = addr{11-0}; // imm12
1775 let Inst{11-0} = addr{11-0}; // imm12
1804 let Inst{11-0} = addr{11-0}; // imm12
1978 let Inst{11-0} = addr{11-0}; // imm12
2490 let Inst{11-0} = addr{11-0}; // imm12
2553 // {11-0} imm12/Rm
2571 // {11-0} imm12/Rm
[all …]
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| D | ARMInstrFormats.td | 664 // {11-0} imm12/Rm
682 // {11-0} imm12/Rm
701 // {13} 1 == Rm, 0 == imm12
703 // {11-0} imm12/Rm
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| D | ARMInstrThumb2.td | 151 // t2addrmode_imm12 := reg + imm12
162 // t2ldrlabel := imm12
973 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
1061 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
1631 let Inst{11-0} = addr{11-0}; // imm12
1696 let Inst{11-0} = addr{11-0}; // imm12
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| D | README.txt | 505 LDR into imm12 and so_reg forms. This allows us to clean up some code. e.g.
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| /external/vixl/src/vixl/a64/ |
| D | assembler-a64.h | 3960 static Instr ImmLSUnsigned(int imm12) { in ImmLSUnsigned() argument
3961 VIXL_ASSERT(is_uint12(imm12)); in ImmLSUnsigned()
3962 return imm12 << ImmLSUnsigned_offset; in ImmLSUnsigned()
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| /external/valgrind/none/tests/arm64/ |
| D | integer.stdout.exp | 194 ADD imm12
235 SUB imm12
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| /external/valgrind/none/tests/arm/ |
| D | v6intARM.stdout.exp | 779 pld reg +/- imm12 cases
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