| /external/llvm/include/llvm/Target/ |
| D | TargetCallingConv.h | 67 bool isSExt() const { return Flags & SExt; } in isSExt() function
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| D | TargetLowering.h | 2311 bool isSExt : 1; member
2321 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), in ArgListEntry()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.cpp | 101 Entry.isSExt = false; in EmitSpecializedLibcall()
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| D | ARMFastISel.cpp | 2132 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { in SelectRet()
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| D | ARMISelLowering.cpp | 6663 Entry.isSExt = false; in LowerFSINCOS()
6673 Entry.isSExt = false; in LowerFSINCOS()
11553 Entry.isSExt = isSigned; in getDivRemArgList()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 2503 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select() local
2506 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
2512 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break; in Select()
2518 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
2523 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; in Select()
2539 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select() local
2542 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
2550 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break; in Select()
2556 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) && in Select()
2561 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break; in Select()
[all …]
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| D | PPCISelLowering.cpp | 3026 if (Flags.isSExt()) in extendArgForPPC64()
4955 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4()
5526 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_Darwin()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZCallingConv.td | 13 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 677 bool isSExt = true; in getCopyFromRegs() local
680 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 in getCopyFromRegs()
682 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 in getCopyFromRegs()
684 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 in getCopyFromRegs()
686 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 in getCopyFromRegs()
688 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 in getCopyFromRegs()
690 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 in getCopyFromRegs()
692 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 in getCopyFromRegs()
694 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 in getCopyFromRegs()
700 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
[all …]
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| D | LegalizeDAG.cpp | 2204 Entry.isSExt = isSigned; in ExpandLibCall()
2252 Entry.isSExt = isSigned; in ExpandLibCall()
2286 Entry.isSExt = isSigned; in ExpandChainLibCall()
2373 Entry.isSExt = isSigned; in ExpandDivRemLibCall()
2382 Entry.isSExt = isSigned; in ExpandDivRemLibCall()
2478 Entry.isSExt = false; in ExpandSinCosLibCall()
2486 Entry.isSExt = false; in ExpandSinCosLibCall()
2494 Entry.isSExt = false; in ExpandSinCosLibCall()
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| D | LegalizeTypes.cpp | 1098 Entry.isSExt = isSigned; in ExpandChainLibCall()
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| D | TargetLowering.cpp | 72 isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt); in setAttributes()
99 Entry.isSExt = shouldSignExtendTypeInLibCall(Op.getValueType(), isSigned); in makeLibCall()
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| D | LegalizeIntegerTypes.cpp | 2506 Entry.isSExt = true; in ExpandIntRes_XMULO()
2514 Entry.isSExt = true; in ExpandIntRes_XMULO()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 1301 if (Outs[OIdx].Flags.isSExt()) in LowerCall()
1314 else if (Outs[OIdx].Flags.isSExt()) in LowerCall()
2171 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments()
2297 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments()
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1071 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in X86SelectRet()
1077 if (Outs[0].Flags.isSExt()) in X86SelectRet()
2890 if (Flags.isSExt()) in fastLowerCall()
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| D | X86ISelLowering.cpp | 18165 Entry.isSExt = false; in LowerWin64_i128OP()
19709 Entry.isSExt = false; in LowerFSINCOS()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 168 if (ArgFlags.isSExt()) in CC_Hexagon_VarArg()
233 if (ArgFlags.isSExt()) in CC_Hexagon()
397 if (ArgFlags.isSExt()) in RetCC_Hexagon()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 308 if (ArgFlags.isSExt()) in AnalyzeArguments()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1491 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { in selectRet()
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| D | MipsISelLowering.cpp | 2386 if (ArgFlags.isSExt()) in CC_MipsO32()
2398 if (ArgFlags.isSExt()) in CC_MipsO32()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 696 Offset, Ins[i].Flags.isSExt()); in LowerFormalArguments()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 3712 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in selectRet()
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| D | AArch64ISelLowering.cpp | 1985 Entry.isSExt = false; in LowerFSINCOS()
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