/external/llvm/test/MC/AArch64/ |
D | arm64-memory.s | 284 ldpsw x2, x3, [x14, #16] 285 ldpsw x2, x3, [sp, #-16] 292 ; CHECK: ldpsw x2, x3, [x14, #16] ; encoding: [0xc2,0x0d,0x42,0x69] 293 ; CHECK: ldpsw x2, x3, [sp, #-16] ; encoding: [0xe2,0x0f,0x7e,0x69] 316 ldpsw x2, x3, [x14, #16]! 317 ldpsw x2, x3, [sp, #-16]! 323 ; CHECK: ldpsw x2, x3, [x14, #16]! ; encoding: [0xc2,0x0d,0xc2,0x69] 324 ; CHECK: ldpsw x2, x3, [sp, #-16]! ; encoding: [0xe2,0x0f,0xfe,0x69] 344 ldpsw x2, x3, [x14], #16 345 ldpsw x2, x3, [sp], #-16 [all …]
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D | basic-a64-diagnostics.s | 2539 ldpsw x9, x2, [sp, #2] 2540 ldpsw x1, x2, [x10, #256] 2541 ldpsw x3, x4, [x11, #-260] 2642 ldpsw x9, x2, [sp], #2 2643 ldpsw x1, x2, [x10], #256 2644 ldpsw x3, x4, [x11], #-260 2745 ldpsw x9, x2, [sp, #2]! 2746 ldpsw x1, x2, [x10, #256]! 2747 ldpsw x3, x4, [x11, #-260]!
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D | basic-a64-instructions.s | 3010 ldpsw x9, x10, [sp, #4] 3011 ldpsw x9, x10, [x2, #-256] 3012 ldpsw x20, x30, [sp, #252] 3058 ldpsw x9, x10, [sp], #4 3059 ldpsw x9, x10, [x2], #-256 3060 ldpsw x20, x30, [sp], #252 3105 ldpsw x9, x10, [sp, #4]! 3106 ldpsw x9, x10, [x2, #-256]! 3107 ldpsw x20, x30, [sp, #252]!
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-ldp.ll | 14 ; CHECK: ldpsw 98 ; CHECK: ldpsw [[DST1:x[0-9]+]], [[DST2:x[0-9]+]], [x0, #-8] 201 ; CHECK: ldpsw [[DST1:x[0-9]+]], [[DST2:x[0-9]+]], [x0, #-256] 331 ; CHECK: ldpsw x{{[0-9]+}}, x{{[0-9]+}}, [x{{[0-9]+}}, #8] 346 ; CHECK: ldpsw x{{[0-9]+}}, x{{[0-9]+}}, [x0], #8
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/external/llvm/test/MC/Disassembler/AArch64/ |
D | arm64-memory.txt | 290 # CHECK: ldpsw x2, x3, [x14, #16] 291 # CHECK: ldpsw x2, x3, [sp, #-16] 318 # CHECK: ldpsw x2, x3, [x14, #16]! 319 # CHECK: ldpsw x2, x3, [sp, #-16]! 346 # CHECK: ldpsw x2, x3, [x14], #16 347 # CHECK: ldpsw x2, x3, [sp], #-16
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D | basic-a64-instructions.txt | 2662 # CHECK: ldpsw x9, x10, [sp, #4] 2663 # CHECK: ldpsw x9, x10, [x2, #-256] 2664 # CHECK: ldpsw x20, x30, [sp, #252] 2710 # CHECK: ldpsw x9, x10, [sp], #4 2711 # CHECK: ldpsw x9, x10, [x2], #-256 2712 # CHECK: ldpsw x20, x30, [sp], #252 2758 # CHECK: ldpsw x9, x10, [sp, #4]! 2759 # CHECK: ldpsw x9, x10, [x2, #-256]! 2760 # CHECK: ldpsw x20, x30, [sp, #252]!
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/external/v8/test/cctest/ |
D | test-disasm-arm64.cc | 1252 COMPARE(ldpsw(x0, x1, MemOperand(x2)), "ldpsw x0, x1, [x2]"); in TEST_() 1253 COMPARE(ldpsw(x3, x4, MemOperand(x5, 16)), "ldpsw x3, x4, [x5, #16]"); in TEST_() 1254 COMPARE(ldpsw(x6, x7, MemOperand(x8, -32, PreIndex)), in TEST_() 1256 COMPARE(ldpsw(x9, x10, MemOperand(x11, 128, PostIndex)), in TEST_()
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/external/v8/src/arm64/ |
D | assembler-arm64.h | 1386 void ldpsw(const Register& rt, const Register& rt2, const MemOperand& src);
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D | assembler-arm64.cc | 1589 void Assembler::ldpsw(const Register& rt, in ldpsw() function in v8::internal::Assembler
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/external/vixl/test/ |
D | test-disasm-a64.cc | 1730 COMPARE(ldpsw(x0, x1, MemOperand(x2)), "ldpsw x0, x1, [x2]"); in TEST() 1731 COMPARE(ldpsw(x3, x4, MemOperand(x5, 16)), "ldpsw x3, x4, [x5, #16]"); in TEST() 1732 COMPARE(ldpsw(x6, x7, MemOperand(x8, -32, PreIndex)), in TEST() 1734 COMPARE(ldpsw(x9, x10, MemOperand(x11, 128, PostIndex)), in TEST()
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D | test-assembler-a64.cc | 15601 __ ldpsw(x2, x3, MemOperand(x0, offset)); in TEST() local 15755 __ ldpsw(x2, x3, MemOperand(x0, preindex, PreIndex)); in TEST() local 15881 __ ldpsw(x2, x3, MemOperand(x0, postindex, PostIndex)); in TEST() local
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/external/vixl/src/vixl/a64/ |
D | assembler-a64.h | 1820 void ldpsw(const Register& rt, const Register& rt2, const MemOperand& src);
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D | assembler-a64.cc | 1461 void Assembler::ldpsw(const Register& rt, in ldpsw() function in vixl::Assembler
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/external/vixl/doc/ |
D | supported-instructions.md | 591 void ldpsw(const Register& rt, const Register& rt2, const MemOperand& src)
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/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.td | 1242 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">; 1251 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">; 1260 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
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