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Searched refs:opstr (Results 1 – 19 of 19) sorted by relevance

/external/llvm/lib/Target/Mips/
DMicroMipsDSPInstrFormats.td10 class MMDSPInst<string opstr = "">
14 string BaseOpcode = opstr;
25 class POOL32A_3R_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
37 class POOL32A_2R_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
48 class POOL32A_2RAC_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> {
61 class POOL32A_3RB0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
74 class POOL32A_2RSA4_FMT<string opstr, bits<12> op> : MMDSPInst<opstr> {
86 class POOL32A_2RSA3_FMT<string opstr, bits<7> op> : MMDSPInst<opstr> {
99 class POOL32A_2RSA5B0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
112 class POOL32A_2RSA4B0_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
[all …]
DMicroMipsInstrInfo.td178 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
181 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZC, FrmI> {
189 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
192 !strconcat(opstr, "\t$rt, $addr"),
199 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
202 !strconcat(opstr, "\t$rt, $addr"),
222 class MovePMM16<string opstr, RegisterOperand RO> :
224 !strconcat(opstr, "\t$dst_regs, $rs, $rt"), [],
243 class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
246 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
[all …]
DMipsInstrInfo.td784 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
788 !strconcat(opstr, "\t$rd, $rs, $rt"),
789 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
796 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
801 !strconcat(opstr, "\t$rt, $rs, $imm16"),
803 Itin, FrmI, opstr> {
809 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
811 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
818 class LogicNOR<string opstr, RegisterOperand RO>:
820 !strconcat(opstr, "\t$rd, $rs, $rt"),
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DMipsInstrFPU.td104 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
107 !strconcat(opstr, "\t$fd, $fs, $ft"),
108 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
113 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
115 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32;
116 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
121 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
123 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
128 multiclass ABSS_M<string opstr, InstrItinClass Itin,
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DMipsCondMov.td19 class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
22 !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR, opstr> {
27 class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
30 !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR, opstr>,
36 class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
39 !strconcat(opstr, "\t$rd, $rs, $fcc"),
41 Itin, FrmFR, opstr>, HARDFLOAT {
46 class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
49 !strconcat(opstr, "\t$fd, $fs, $fcc"),
51 Itin, FrmFR, opstr>, HARDFLOAT {
DMips64InstrInfo.td315 class Count1s<string opstr, RegisterOperand RO>:
316 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
317 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
321 class ExtsCins<string opstr, SDPatternOperator Op = null_frag>:
323 !strconcat(opstr, " $rt, $rs, $pos, $lenm1"),
325 NoItinerary, FrmR, opstr> {
329 class SetCC64_R<string opstr, PatFrag cond_op> :
331 !strconcat(opstr, "\t$rd, $rs, $rt"),
334 II_SEQ_SNE, FrmR, opstr> {
338 class SetCC64_I<string opstr, PatFrag cond_op>:
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DMicroMips32r6InstrInfo.td372 class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
373 : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
375 MMR6Arch<opstr>, MicroMipsR6Inst16 {
382 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
384 : MMR6Arch<opstr> {
386 string AsmString = !strconcat(opstr, "\t$rt, $offset");
404 class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
405 : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
407 MMR6Arch<opstr>, MicroMipsR6Inst16 {
514 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
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DMipsDSPInstrFormats.td43 class DSPInst<string opstr = "">
46 string BaseOpcode = opstr;
DMips32r6InstrFormats.td28 class MipsR6Arch<string opstr> {
30 string BaseOpcode = opstr;
DMicroMips32r6InstrFormats.td14 class MMR6Arch<string opstr> {
16 string BaseOpcode = opstr;
DMips32r6InstrInfo.td381 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
383 : MipsR6Arch<opstr> {
385 string AsmString = !strconcat(opstr, "\t$rt, $offset");
DMipsInstrFormats.td109 InstrItinClass itin, Format f, string opstr = ""> :
112 string BaseOpcode = opstr;
DMicroMipsDSPInstrInfo.td160 class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
165 string AsmString = !strconcat(opstr, "\t$rt, $rs");
/external/icu/icu4c/source/test/cintltst/
Dputiltst.c314 const char *opstr; in TestCompareVersions() local
322 opstr = testCases[j+1]; in TestCompareVersions()
324 switch(opstr[0]) { in TestCompareVersions()
339 log_verbose("%d: %s %s %s, OK\n", (j/3), v1str, opstr, v2str); in TestCompareVersions()
341 …log_err("%d: %s %s %s: wanted values of the same sign, %d got %d\n", (j/3), v1str, opstr, v2str, o… in TestCompareVersions()
/external/regex-re2/re2/
Dparse.cc2065 StringPiece opstr = t; in Parse()
2083 opstr.set(opstr.data(), t.data() - opstr.data()); in Parse()
2084 if (!ps.PushRepeatOp(op, opstr, nongreedy)) in Parse()
2086 isunary = opstr; in Parse()
2092 StringPiece opstr = t; in Parse() local
2114 opstr.set(opstr.data(), t.data() - opstr.data()); in Parse()
2115 if (!ps.PushRepetition(lo, hi, opstr, nongreedy)) in Parse()
2117 isunary = opstr; in Parse()
/external/google-breakpad/src/third_party/libdisasm/
Dx86_format.c1090 struct op_string * opstr = (struct op_string *) arg; in format_op_raw() local
1092 format_operand_raw(op, insn, opstr->buf, opstr->len); in format_op_raw()
1114 struct op_string opstr = { buf, len }; in format_raw_insn() local
1158 opstr.len = len; in format_raw_insn()
1159 x86_operand_foreach( insn, format_op_raw, &opstr, op_any ); in format_raw_insn()
/external/llvm/lib/Target/NVPTX/
DNVPTXVector.td1082 class LoadParamScalar4Inst<NVPTXRegClass regclass, string opstr> :
1085 !strconcat(!strconcat("ld.param", opstr),
1088 class LoadParamScalar2Inst<NVPTXRegClass regclass, string opstr> :
1091 !strconcat(!strconcat("ld.param", opstr),
1095 class StoreParamScalar4Inst<NVPTXRegClass regclass, string opstr> :
1099 !strconcat(!strconcat("st.param", opstr),
1102 class StoreParamScalar2Inst<NVPTXRegClass regclass, string opstr> :
1105 !strconcat(!strconcat("st.param", opstr),
1108 class StoreRetvalScalar4Inst<NVPTXRegClass regclass, string opstr> :
1112 !strconcat(!strconcat("st.param", opstr),
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DNVPTXInstrInfo.td1765 class LoadParamMemInst<NVPTXRegClass regclass, string opstr> :
1767 !strconcat(!strconcat("ld.param", opstr),
1771 class LoadParamRegInst<NVPTXRegClass regclass, string opstr> :
1773 !strconcat(!strconcat("mov", opstr),
1777 class LoadParamV2MemInst<NVPTXRegClass regclass, string opstr> :
1779 !strconcat(!strconcat("ld.param.v2", opstr),
1782 class LoadParamV4MemInst<NVPTXRegClass regclass, string opstr> :
1786 !strconcat(!strconcat("ld.param.v4", opstr),
1789 class StoreParamInst<NVPTXRegClass regclass, string opstr> :
1791 !strconcat(!strconcat("st.param", opstr),
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/external/selinux/libsepol/cil/src/
Dcil_binary.c1865 char *opstr = ""; in __cil_expr_to_string() local
1870 opstr = CIL_KEY_OR; in __cil_expr_to_string()
1872 opstr = CIL_KEY_AND; in __cil_expr_to_string()
1874 opstr = CIL_KEY_XOR; in __cil_expr_to_string()
1877 cil_asprintf(out, "%s %s %s", opstr, s1, s2); in __cil_expr_to_string()