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Searched refs:saddlv (Results 1 – 15 of 15) sorted by relevance

/external/llvm/test/Transforms/SLPVectorizer/AArch64/
Dmismatched-intrinsics.ll7 ; CHECK: call i64 @llvm.arm64.neon.saddlv.i64.v4i32
8 ; CHECK: call i64 @llvm.arm64.neon.saddlv.i64.v2i32
10 %vaddlvq_s32.i = tail call i64 @llvm.arm64.neon.saddlv.i64.v4i32(<4 x i32> %in1) #2
11 %vaddlv_s32.i = tail call i64 @llvm.arm64.neon.saddlv.i64.v2i32(<2 x i32> %in2) #2
17 declare i64 @llvm.arm64.neon.saddlv.i64.v4i32(<4 x i32> %in1)
18 declare i64 @llvm.arm64.neon.saddlv.i64.v2i32(<2 x i32> %in1)
/external/llvm/test/MC/AArch64/
Dneon-across.s9 saddlv h0, v1.8b
10 saddlv h0, v1.16b
11 saddlv s0, v1.4h
12 saddlv s0, v1.8h
13 saddlv d0, v1.4s define
Dneon-diagnostics.s3713 saddlv b0, v1.8b
3714 saddlv b0, v1.16b
3715 saddlv h0, v1.4h
3716 saddlv h0, v1.8h
3717 saddlv s0, v1.2s
3718 saddlv s0, v1.4s
3719 saddlv d0, v1.2s define
/external/llvm/test/CodeGen/AArch64/
Darm64-neon-across.ll67 declare i64 @llvm.aarch64.neon.saddlv.i64.v4i32(<4 x i32>)
69 declare i32 @llvm.aarch64.neon.saddlv.i32.v8i16(<8 x i16>)
71 declare i32 @llvm.aarch64.neon.saddlv.i32.v16i8(<16 x i8>)
77 declare i32 @llvm.aarch64.neon.saddlv.i32.v4i16(<4 x i16>)
79 declare i32 @llvm.aarch64.neon.saddlv.i32.v8i8(<8 x i8>)
83 ; CHECK: saddlv h{{[0-9]+}}, {{v[0-9]+}}.8b
85 %saddlvv.i = tail call i32 @llvm.aarch64.neon.saddlv.i32.v8i8(<8 x i8> %a)
92 ; CHECK: saddlv s{{[0-9]+}}, {{v[0-9]+}}.4h
94 %saddlvv.i = tail call i32 @llvm.aarch64.neon.saddlv.i32.v4i16(<4 x i16> %a)
117 ; CHECK: saddlv h{{[0-9]+}}, {{v[0-9]+}}.16b
[all …]
Darm64-vaddlv.ll9 %vaddlv.i = tail call i64 @llvm.aarch64.neon.saddlv.i64.v2i32(<2 x i32> %a1) nounwind
25 declare i64 @llvm.aarch64.neon.saddlv.i64.v2i32(<2 x i32>) nounwind readnone
/external/vixl/src/vixl/a64/
Dsimulator-a64.h1763 LogicVRegister saddlv(VectorFormat vform,
Dmacro-assembler-a64.h2298 V(saddlv, Saddlv) \
Dassembler-a64.h3011 void saddlv(const VRegister& vd,
Dsimulator-a64.cc2784 case NEON_SADDLV: saddlv(vf, rd, rn); break; in VisitNEONAcrossLanes()
Dlogic-a64.cc1420 LogicVRegister Simulator::saddlv(VectorFormat vform, in saddlv() function in vixl::Simulator
Dassembler-a64.cc4034 void Assembler::saddlv(const VRegister& vd, in saddlv() function in vixl::Assembler
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp27412 saddlv h3, v19.16b 6a6ae66cc4216b5f1e4cae97cdedc8fe 2d17bd108ef21024989b962aceeb5213 0000000000…
27413 saddlv h3, v19.8b c9c9442fc64a712fa77ad1e23d7be807 8486e92a3b18b34357ea3d3655777445 00000000000…
27414 saddlv s3, v19.8h ec5c1e23161bedd368a1c5842d3592c8 362269ae4d5d24efe42a8cd075a678e7 00000000000…
27415 saddlv s3, v19.4h a4cb9e7c24a1c306a23be3d98e58bed9 20779159f046485f23287be27b55f76c 00000000000…
27416 saddlv d3, v19.4s 2d61e87321c4f16aeefda22f016da7fa 0f83e61e256c702953b23caed3ad7f0c 00000000000…
/external/vixl/test/
Dtest-simulator-a64.cc4038 DEFINE_TEST_NEON_ACROSS_LONG(saddlv, Basic)
/external/vixl/doc/
Dsupported-instructions.md3034 void saddlv(const VRegister& vd,
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td4021 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;