/external/mesa3d/src/gallium/drivers/nvc0/ |
D | nvc0_miptree.c | 34 uint32_t tile_mode = 0x000; in nvc0_tex_choose_tile_dims() local 36 if (ny > 64) tile_mode = 0x040; /* height 128 tiles */ in nvc0_tex_choose_tile_dims() 38 if (ny > 32) tile_mode = 0x030; /* height 64 tiles */ in nvc0_tex_choose_tile_dims() 40 if (ny > 16) tile_mode = 0x020; /* height 32 tiles */ in nvc0_tex_choose_tile_dims() 42 if (ny > 8) tile_mode = 0x010; /* height 16 tiles */ in nvc0_tex_choose_tile_dims() 45 return tile_mode; in nvc0_tex_choose_tile_dims() 47 if (tile_mode > 0x020) in nvc0_tex_choose_tile_dims() 48 tile_mode = 0x020; in nvc0_tex_choose_tile_dims() 50 if (nz > 16 && tile_mode < 0x020) in nvc0_tex_choose_tile_dims() 51 return tile_mode | 0x500; /* depth 32 tiles */ in nvc0_tex_choose_tile_dims() [all …]
|
D | nvc0_transfer.c | 41 PUSH_DATA (push, src->tile_mode); in nvc0_m2mf_transfer_rect() 57 PUSH_DATA (push, dst->tile_mode); in nvc0_m2mf_transfer_rect() 145 PUSH_DATA (push, 0x1000 | dst->tile_mode); in nve4_m2mf_transfer_rect() 153 PUSH_DATA (push, 0x1000 | src->tile_mode); in nve4_m2mf_transfer_rect()
|
D | nvc0_tex.c | 139 ((mt->level[0].tile_mode & 0x0f0) << (22 - 4)) | in nvc0_create_sampler_view() 140 ((mt->level[0].tile_mode & 0xf00) << (25 - 8)); in nvc0_create_sampler_view()
|
D | nvc0_surface.c | 123 PUSH_DATA (push, mt->level[level].tile_mode); in nvc0_2d_texture_set() 309 mt->level[sf->base.u.tex.level].tile_mode); in nvc0_clear_render_target() 379 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode); in nvc0_clear_depth_stencil()
|
D | nvc0_state_validate.c | 89 mt->level[sf->base.u.tex.level].tile_mode); in nvc0_validate_fb() 132 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode); in nvc0_validate_fb()
|
D | nvc0_screen.c | 759 mm_config.nvc0.tile_mode = 0; in nvc0_screen_create()
|
/external/drm_gralloc/ |
D | gralloc_drm_nouveau.c | 71 int flags, tile_mode, tile_flags; in alloc_bo() local 76 tile_mode = 0; in alloc_bo() 102 tile_mode = 0x40; in alloc_bo() 104 tile_mode = 0x30; in alloc_bo() 106 tile_mode = 0x20; in alloc_bo() 108 tile_mode = 0x10; in alloc_bo() 110 tile_mode = 0x00; in alloc_bo() 114 align = NVC0_TILE_HEIGHT(tile_mode); in alloc_bo() 119 tile_mode = 4; in alloc_bo() 121 tile_mode = 3; in alloc_bo() [all …]
|
/external/libdrm/radeon/ |
D | radeon_surface.c | 1281 unsigned mode, unsigned *tile_mode, unsigned *stencil_tile_mode) in si_surface_sanity() argument 1346 *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D; in si_surface_sanity() 1349 *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D_2AA; in si_surface_sanity() 1352 *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D_4AA; in si_surface_sanity() 1355 *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D_8AA; in si_surface_sanity() 1363 *tile_mode = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP; in si_surface_sanity() 1366 *tile_mode = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP; in si_surface_sanity() 1374 *tile_mode = SI_TILE_MODE_COLOR_2D_8BPP; in si_surface_sanity() 1377 *tile_mode = SI_TILE_MODE_COLOR_2D_16BPP; in si_surface_sanity() 1380 *tile_mode = SI_TILE_MODE_COLOR_2D_32BPP; in si_surface_sanity() [all …]
|
/external/mesa3d/src/gallium/drivers/nv50/ |
D | nv50_miptree.c | 231 lvl->tile_mode = nv50_tex_choose_tile_dims(nbx, nby, d); in nv50_miptree_init_layout_tiled() 233 tsx = NV50_TILE_SIZE_X(lvl->tile_mode); /* x is tile row pitch in bytes */ in nv50_miptree_init_layout_tiled() 234 tsy = NV50_TILE_SIZE_Y(lvl->tile_mode); in nv50_miptree_init_layout_tiled() 235 tsz = NV50_TILE_SIZE_Z(lvl->tile_mode); in nv50_miptree_init_layout_tiled() 248 NV50_TILE_SIZE(mt->level[0].tile_mode)); in nv50_miptree_init_layout_tiled() 286 bo_config.nv50.tile_mode = mt->level[0].tile_mode; in nv50_miptree_create() 338 mt->level[0].tile_mode = mt->base.bo->config.nv50.tile_mode; in nv50_miptree_from_handle() 351 unsigned tds = NV50_TILE_SHIFT_Z(mt->level[l].tile_mode); in nv50_mt_zslice_offset() 352 unsigned ths = NV50_TILE_SHIFT_Y(mt->level[l].tile_mode); in nv50_mt_zslice_offset() 358 unsigned stride_2d = NV50_TILE_SIZE_2D(mt->level[l].tile_mode); in nv50_mt_zslice_offset() [all …]
|
D | nv50_transfer.h | 18 uint16_t tile_mode; member
|
D | nv50_transfer.c | 39 rect->tile_mode = mt->level[l].tile_mode; in nv50_m2mf_rect_setup() 77 PUSH_DATA (push, src->tile_mode); in nv50_m2mf_transfer_rect() 94 PUSH_DATA (push, dst->tile_mode); in nv50_m2mf_transfer_rect()
|
D | nv50_resource.h | 41 uint32_t tile_mode; member
|
D | nv50_tex.c | 146 ((mt->level[0].tile_mode & 0x0f0) << (22 - 4)) | in nv50_create_sampler_view() 147 ((mt->level[0].tile_mode & 0xf00) << (25 - 8)); in nv50_create_sampler_view()
|
D | nv50_state_validate.c | 31 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode); in nv50_validate_fb() 72 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode); in nv50_validate_fb()
|
D | nv50_surface.c | 116 PUSH_DATA (push, mt->level[level].tile_mode); in nv50_2d_texture_set() 296 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode); in nv50_clear_render_target() 361 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode); in nv50_clear_depth_stencil()
|
/external/libdrm/nouveau/ |
D | abi16.c | 298 bo->config.nvc0.tile_mode = info->tile_mode; in abi16_bo_info() 303 bo->config.nv50.tile_mode = info->tile_mode << 4; in abi16_bo_info() 306 bo->config.nv04.surf_pitch = info->tile_mode; in abi16_bo_info() 343 info->tile_mode = config->nvc0.tile_mode; in abi16_bo_init() 348 info->tile_mode = config->nv50.tile_mode >> 4; in abi16_bo_init() 351 info->tile_mode = config->nv04.surf_pitch; in abi16_bo_init()
|
D | nouveau.h | 103 uint32_t tile_mode; member 107 uint32_t tile_mode; member
|
/external/libdrm/include/drm/ |
D | nouveau_drm.h | 121 uint32_t tile_mode; member 127 uint32_t tile_mode; member 254 uint32_t tile_mode; member
|
/external/kernel-headers/original/uapi/drm/ |
D | nouveau_drm.h | 49 uint32_t tile_mode; member
|
/external/libdrm/libkms/ |
D | nouveau.c | 113 arg.info.tile_mode = 0; in nouveau_bo_create()
|