| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 62 v16i1 = 16, // 16 x i1 enumerator
222 SimpleTy == MVT::v16i1); in is16BitVector()
313 case v16i1: in getVectorElementType()
382 case v16i1: in getVectorNumElements()
449 case v16i1: in getSizeInBits()
589 if (NumElements == 16) return MVT::v16i1; in getVectorVT()
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| D | ValueTypes.td | 39 def v16i1 : ValueType<16, 16>; // 16 x i1 vector value
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64TargetTransformInfo.cpp | 391 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 16 }, in getCmpSelInstrCost()
393 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 }, in getCmpSelInstrCost()
396 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 16 * AmortizationCost } in getCmpSelInstrCost()
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 143 case MVT::v16i1: return "v16i1"; in getEVTString()
221 case MVT::v16i1: return VectorType::get(Type::getInt1Ty(Context), 16); in getTypeForEVT()
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | vec-move-16.ll | 5 ; Test a v16i1->v16i8 extension.
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| D | vec-move-15.ll | 5 ; Test a v16i1->v16i8 extension.
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| D | vec-and-03.ll | 5 ; Test a v16i1->v16i8 extension.
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| D | vec-move-17.ll | 5 ; Test a v16i8->v16i1 truncation.
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| D | vec-shift-07.ll | 5 ; Test a v16i1->v16i8 extension.
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| /external/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 561 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost()
562 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost()
573 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
582 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
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| D | X86CallingConv.td | 49 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
292 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
565 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
735 CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>,
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| D | X86InstrAVX512.td | 2061 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
2087 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
2089 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
2120 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
2126 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
2180 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
2249 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
2256 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
2315 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2316 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
[all …]
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| D | X86RegisterInfo.td | 484 def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;}
492 def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)> {let Size = 16;}
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| D | X86ISelLowering.cpp | 1316 addRegisterClass(MVT::v16i1, &X86::VK16RegClass); in X86TargetLowering()
1347 setOperationAction(ISD::LOAD, MVT::v16i1, Legal); in X86TargetLowering()
1373 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom); in X86TargetLowering()
1411 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom); in X86TargetLowering()
1442 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom); in X86TargetLowering()
1472 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom); in X86TargetLowering()
1474 setOperationAction(ISD::SETCC, MVT::v16i1, Custom); in X86TargetLowering()
1480 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom); in X86TargetLowering()
1481 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16i1, Custom); in X86TargetLowering()
1482 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom); in X86TargetLowering()
[all …]
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| D | X86InstrCompiler.td | 553 defm _V16I1 : CMOVrr_PSEUDO<VK16, v16i1>;
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 76 case MVT::v16i1: return "MVT::v16i1"; in getEnumName()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 279 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 100 } in getCmpSelInstrCost()
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 161 def llvm_v16i1_ty : LLVMType<v16i1>; // 16 x i1
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