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Searched refs:v64i1 (Results 1 – 11 of 11) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DMachineValueType.h64 v64i1 = 18, // 64 x i1 enumerator
315 case v64i1: in getVectorElementType()
373 case v64i1: in getVectorNumElements()
463 case v64i1: in getSizeInBits()
591 if (NumElements == 64) return MVT::v64i1; in getVectorVT()
DValueTypes.td41 def v64i1 : ValueType<64 , 18>; // 64 x i1 vector value
/external/llvm/lib/IR/
DValueTypes.cpp145 case MVT::v64i1: return "v64i1"; in getEVTString()
223 case MVT::v64i1: return VectorType::get(Type::getInt1Ty(Context), 64); in getTypeForEVT()
/external/llvm/lib/Target/X86/
DX86CallingConv.td51 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
294 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
567 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
DX86RegisterInfo.td486 def VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;}
494 def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;}
DX86InstrAVX512.td2073 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
2097 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
2098 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
2136 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
2138 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
2190 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
2260 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
2361 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2399 defm KUNPCKDQ : avx512_mask_unpck<"dq", VK64, v64i1, VK32, HasBWI>, PS, VEX_W;
2466 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
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DX86ISelLowering.cpp1623 addRegisterClass(MVT::v64i1, &X86::VK64RegClass); in X86TargetLowering()
1628 setOperationAction(ISD::SETCC, MVT::v64i1, Custom); in X86TargetLowering()
1637 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom); in X86TargetLowering()
1641 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom); in X86TargetLowering()
1647 setOperationAction(ISD::SELECT, MVT::v64i1, Custom); in X86TargetLowering()
1657 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom); in X86TargetLowering()
1663 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom); in X86TargetLowering()
1666 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom); in X86TargetLowering()
1884 case 64: return MVT::v64i1; in getSetCCResultType()
2728 else if (RegVT == MVT::v64i1) in LowerFormalArguments()
[all …]
DX86InstrCompiler.td555 defm _V64I1 : CMOVrr_PSEUDO<VK64, v64i1>;
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp78 case MVT::v64i1: return "MVT::v64i1"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td163 def llvm_v64i1_ty : LLVMType<v64i1>; // 64 x i1
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1788 for (MVT NativeVT : {MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v32i1, MVT::v64i1, in HexagonTargetLowering()