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Searched refs:CCR (Results 1 – 11 of 11) sorted by relevance

/toolchain/binutils/binutils-2.25/gas/testsuite/gas/m68hc11/
D9s12x-exg-sex-tfr.d15 0x0000000c exg CCR,CCR
16 0x0000000e exg D,CCR
17 0x00000010 exg X,CCR
18 0x00000012 exg Y,CCR
19 0x00000014 exg SP,CCR
22 0x0000001a exg CCR,D
27 0x00000024 exg CCR,X
32 0x0000002e exg CCR,Y
37 0x00000038 exg CCR,SP
Dinsns9s12xg.d112 000000ce <label3\+0xca> tfr R2, CCR
113 000000d0 <label3\+0xcc> tfr CCR, R3
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/xgate/
Dall_insns.d125 0+00da <L100> tfr R7, CCR
126 0+00dc <L101> tfr CCR, R7
/toolchain/binutils/binutils-2.25/gas/config/
Dm68k-parse.h85 CCR, /* Condition code Reg */ enumerator
Dtc-h8300.c400 *mode = CCR; in parse_reg()
1138 case CCR: in get_specific()
1139 if (op_mode != CCR && in get_specific()
Dtc-m68k.c1933 if (opP->mode != CONTROL || opP->reg != CCR) in m68k_ip()
4109 { "ccr", CCR },
4110 { "cc", CCR },
/toolchain/binutils/binutils-2.25/include/opcode/
Dh8300.h78 CCR = 0x4000, enumerator
1252 {O (O_ANDC, SB), AV_H8, 2, "andc", {{IMM8, CCR | DST, E}}, {{0x0, 0x6, IMM8LIST, E}}},
1422 …{O (O_LDC, SB), AV_H8, 2, "ldc", {{IMM8, CCR | DST, E}}, {{ …
1424 …{O (O_LDC, SB), AV_H8, 2, "ldc", {{RS8, CCR | DST, E}}, {{0x0, 0x3, B30 | CCR | DST, …
1426 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSIND, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | …
1428 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSPOSTINC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | …
1430 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | …
1432 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | …
1434 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, I…
1436 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, I…
[all …]
/toolchain/binutils/binutils-2.25/opcodes/
Dh8300-dis.c302 else if ((x & MODE) == CCR) in print_one_arg()
483 if (((looking_for & MODE) == CCR && (thisnib != C_CCR)) in bfd_h8_disassemble()
DChangeLog-9899341 MOVE MACSR,CCR.
/toolchain/binutils/binutils-2.25/cpu/
Dfrv.cpu100 (prev-ccr-complex DI) ; Previous use of CCR register has variable latency
105 (cur-ccr-complex SI) ; Current use of CCR register has variable latency
2980 ; Integer condition code registers (CCR)
2982 ; The individual sub registers bits of the CCR are referenced more often than
3001 ; Floating point condition code registers (CCR)
3003 ; The individual sub registers bits of the CCR are referenced more often than
Dcris.cpu612 (CCR 5)