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Searched refs:FP (Results 1 – 25 of 243) sorted by relevance

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/toolchain/binutils/binutils-2.25/opcodes/
Dalpha-opc.c346 #define FP(oo,fff) FP_(oo,fff), FP_MASK macro
662 { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } },
663 { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 },
664 { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 },
665 { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } },
666 { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } },
667 { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 },
668 { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 },
669 { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 },
670 { "sqrtt/m", FP(0x14,0x06B), CIX, ARG_FPZ1 },
[all …]
Daarch64-tbl.h1227 #define FP &aarch64_feature_fp macro
1875 …{"scvtf", 0x1e020000, 0x7f3f0000, float2fix, 0, FP, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_S…
1876 …{"ucvtf", 0x1e030000, 0x7f3f0000, float2fix, 0, FP, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_S…
1877 …{"fcvtzs", 0x1e180000, 0x7f3f0000, float2fix, 0, FP, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_…
1878 …{"fcvtzu", 0x1e190000, 0x7f3f0000, float2fix, 0, FP, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_…
1880 {"fcvtns", 0x1e200000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
1881 {"fcvtnu", 0x1e210000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
1882 {"scvtf", 0x1e220000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF},
1883 {"ucvtf", 0x1e230000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF},
1884 {"fcvtas", 0x1e240000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/
Dloop_temps.s12 [FP+28] = R0;
13 [FP+32] = R1;
14 [FP+36] = R2;
15 [FP+-68] = SP;
17 [FP+-24] = R0;
18 R0 = [FP+44];
30 [FP+-60] = R7;
31 R7 = [FP+-60];
33 [FP+-60] = R7;
35 [FP+-64] = R2;
[all …]
Dstore.d7 0: 78 93 \[FP\] = P0;
9 4: fd 92 \[FP--\] = P5;
12 c: 3a bc \[FP \+ 0x0\] = P2;
13 e: f9 bb \[FP -0x4\] = P1;
14 10: 08 ba \[FP -0x80\] = P0;
19 16: bf 92 \[FP--\] = R7;
22 1e: 38 e6 01 c0 \[FP \+ -0xfffc\] = R0;
23 22: 4f 88 \[FP \+\+ P1\] = R1;
24 24: 86 ba \[FP -0x60\] = R6;
35 36: 07 8d W\[FP \+\+ P0\] = R4.H;
[all …]
Dload.d11 c: 0f e1 dc fe FP.L = 0xfedc;.*
19 2c: 8f e1 20 ff FP = 0xff20 \(Z\);.*
29 4e: 67 69 FP = 0x2c \(X\);.*
39 6a: 7e 91 SP = \[FP\];
40 6c: 47 90 FP = \[P0\+\+\];
43 72: 3b ac P3 = \[FP \+ 0x0\];
44 74: 3c e5 ff 7f P4 = \[FP \+ 0x1fffc\];
45 78: 3e e5 01 80 SP = \[FP \+ -0x1fffc\];
47 7e: 0d b8 P5 = \[FP -0x80\];
53 86: bc a2 R4 = \[FP \+ 0x28\];
[all …]
Dcache2.s17 PREFETCH [ FP ] ;
27 PREFETCH [ FP++ ] ;
37 FLUSH [ FP ] ;
46 FLUSH [ FP++ ] ;
56 FLUSHINV [ FP ] ;
66 FLUSHINV [ FP++ ] ;
76 IFLUSH [ FP ] ;
86 IFLUSH [ FP++ ] ;
Dflow.s55 R0 = [FP+-3604];
57 R0 = [FP+-3604];
60 P2 = P2 + FP;
66 R0 = [FP+-3604];
68 [FP+-3604] = R0;
93 R0 = [FP+-3608];
96 P2 = P2 + FP;
100 R0 = [FP+-3608];
103 P2 = P2 + FP;
Dcache2.d14 e: 47 02 PREFETCH\[FP\];
22 1e: 67 02 PREFETCH\[FP\+\+\];
30 2e: 57 02 FLUSH\[FP\];
38 3e: 77 02 FLUSH\[FP\+\+\];
46 4e: 4f 02 FLUSHINV\[FP\];
54 5e: 6f 02 FLUSHINV\[FP\+\+\];
62 6e: 5f 02 IFLUSH\[FP\];
70 7e: 7f 02 IFLUSH\[FP\+\+\];
Dflow.d43 44: 38 e4 7b fc R0 = \[FP \+ -0xe14\];
45 4a: 38 e4 7b fc R0 = \[FP \+ -0xe14\];
48 52: ba 5a P2 = P2 \+ FP;
54 60: 38 e4 7b fc R0 = \[FP \+ -0xe14\];
56 66: 38 e6 7b fc \[FP \+ -0xe14\] = R0;
71 98: 38 e4 7a fc R0 = \[FP \+ -0xe18\];
74 a0: ba 5a P2 = P2 \+ FP;
78 aa: 38 e4 7a fc R0 = \[FP \+ -0xe18\];
81 b2: ba 5a P2 = P2 \+ FP;
Dparallel2.d62 d8: 83 ce 08 41 A0 = A0 >> 0x1f \|\| R0 = \[FP -0x20\] \|\| NOP;
64 e0: 83 ce f8 00 A0 = A0 << 0x1f \|\| R0 = \[FP -0x1c\] \|\| NOP;
66 e8: 83 ce 00 50 A1 = A1 >> 0x0 \|\| R0 = \[FP -0x18\] \|\| NOP;
68 f0: 83 ce 00 10 A1 = A1 << 0x0 \|\| R0 = \[FP -0x14\] \|\| NOP;
70 f8: 82 ce fd 4e R7 = R5 << 0x1f \(S\) \|\| R0 = \[FP -0x10\] \|\| NOP;
72 100: 82 ce 52 07 R3 = R2 >>> 0x16 \|\| R0 = \[FP -0xc\] \|\| NOP;
74 108: 80 ce 7a 52 R1.L = R2.H << 0xf \(S\) \|\| R0 = \[FP -0x8\] \|\| NOP;
76 110: 80 ce f2 2b R5.H = R2.L >>> 0x2 \|\| R0 = \[FP -0x4\] \|\| NOP;
78 118: 00 ce 14 16 R3.L = ASHIFT R4.H BY R2.L \|\| R0 = \[FP -0x64\] \|\| NOP;
80 120: 00 ce 07 6e R7.H = ASHIFT R7.L BY R0.L \(S\) \|\| R0 = \[FP -0x68\] \|\| NOP;
[all …]
Dload.s10 FP.L = 0xfedc;
47 FP = [ p0++ ]; define
51 P4 = [FP + 0x0001FFFC];
54 P5 = [FP-128];
78 R6 = W [FP ++] (Z);
89 R6 = W [FP ++] (X);
128 R3 = b [ FP--] (x);
Dstore.s4 [FP] = P0;
21 [FP - 0xfffc] = R0;
23 [FP - 96] = r6;
51 w [FP-0xbcd0] = r1;
61 b[FP - 0x7FFF] = r6;
Dcache.d8 2: 67 02 PREFETCH\[FP\+\+\];
17 c: 4f 02 FLUSHINV\[FP\];
21 10: 7f 02 IFLUSH\[FP\+\+\];
Dmove2.s26 FP = FP; define
38 R4 = FP;
50 FP = R4; define
99 FP = M3; define
108 FP = L3; define
135 I3 = FP;
144 M3 = FP;
153 B3 = FP;
162 L3 = FP;
195 FP = USP; define
[all …]
Dmove2.d23 1e: 7f 32 FP = FP;
32 30: 67 30 R4 = FP;
43 46: 3c 32 FP = R4;
83 96: bf 32 FP = M3;
91 a6: ff 32 FP = L3;
111 ce: 5f 34 I3 = FP;
119 de: 7f 34 M3 = FP;
127 ee: 5f 36 B3 = FP;
135 fe: 7f 36 L3 = FP;
159 12e: f8 33 FP = USP;
[all …]
Dparallel.d26 48: 08 ce 3e 40 BITMUX \(R7, R6, A0\) \(ASL\) \|\| FP = \[P1\+\+\] \|\| NOP;
28 50: 06 ce 00 ca R5.L = ONES R0 \|\| P0 = \[FP--\] \|\| NOP;
34 68: 10 cc 3f 40 A0 = ABS A1 \|\| P3 = \[FP -0x3c\] \|\| R1 = \[I1 \+\+ M0\];
36 70: 30 cc 3f 00 A1 = ABS A0 \|\| P4 = \[FP -0x4\] \|\| R2 = \[I1\+\+\];
38 78: 30 cc 3f 40 A1 = ABS A1 \|\| FP = \[SP\] \|\| R3 = \[I2--\];
44 90: 02 cc 10 a8 R4.L = R2.H \+ R0.L \(S\) \|\| B\[FP\] = R0 \|\| R2.H = W\[I2--\];
84 130: 0b cc 3f a0 A0 \+= A1 \(W32\) \|\| B\[FP\] = R2 \|\| R5 = \[I1\+\+\];
88 140: 0b cc 3f 4c R6.L = \(A0 \+= A1\) \|\| B\[FP\] = R3 \|\| R7 = \[I1\+\+\];
102 178: 08 ca a8 25 R6 = R5.H \* R0.L \|\| B\[FP\] = R4 \|\| R7 = \[I0\+\+\];
132 1f0: 70 c8 3e 98 A1 = R7.H \* R6.L \(M, W32\) \|\| R5 = B\[FP\] \(X\) \|\| \[I1 \+\+ M1\] = R2;
[all …]
Dcontrol_code.s20 cC = FP == 0;
21 CC = FP < SP;
Dcontrol_code.d21 18: 47 0c CC = FP == 0x0;
22 1a: f7 08 CC = FP < SP;
Darithmetic.d19 1c: f9 5b FP = P1 \+ FP;
46 5e: 07 6f FP \+= -0x20;.*
68 88: 17 44 FP -= P2;
77 9a: 7d 45 P5 \+= FP \(BREV\);
Dparallel3.d90 148: 04 cb c1 e0 R3.H = R0.H \* R1.H, R3.L = R0.L \* R1.L \(IS\) \|\| \[FP\] = P0 \|\| NOP;
92 150: 00 c8 13 46 A1 = R2.L \* R3.H, A0 = R2.H \* R3.H \|\| \[FP\+\+\] = P0 \|\| NOP;
94 158: 01 c8 08 c0 A1 \+= R1.H \* R0.H, A0 = R1.L \* R0.L \|\| \[FP--\] = P0 \|\| NOP;
96 160: 60 c8 2f c8 A1 = R5.H \* R7.H, A0 \+= R5.L \* R7.L \(W32\) \|\| \[FP \+ 0x0\] = P0 \|\| NOP;
98 168: 01 c9 01 c0 A1 \+= R0.H \* R1.H, A0 = R0.L \* R1.L \(IS\) \|\| \[FP \+ 0x3c\] = P0 \|\| NOP;
110 …198: 04 c8 be 66 R2.H = \(A1 = R7.L \* R6.H\), R2.L = \(A0 = R7.H \* R6.H\) \|\| \[P0\] = FP \|\|…
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/tic54x/
Dasg.s9 .asg ar0, FP ; replace a sub-operand
15 L2: ld *FP+,a
28 .asg AR0,FP
/toolchain/binutils/binutils-2.25/include/opcode/
Di960.h101 #define FP 0x04 /* Mask for "floating-point-OK" bit */ macro
112 #define F OP( 0, 0, FP, 0 )
113 #define FL OP( 0, LIT, FP, 0 )
116 #define F2 OP( 1, 0, FP, 0 )
117 #define FL2 OP( 1, LIT, FP, 0 )
120 #define F4 OP( 3, 0, FP, 0 )
121 #define FL4 OP( 3, LIT, FP, 0 )
129 #define FP_OK(od) (od & FP) /* TRUE if floating-point op allowed */
/toolchain/binutils/binutils-2.25/gas/doc/
Dc-mips.texi31 * MIPS FP ABIs:: Marking which FP ABI is in use
139 as not making assumptions about 32-bit or 64-bit FP registers. The
799 @node MIPS FP ABIs
800 @section Directives to control the FP ABI
802 * MIPS FP ABI History:: History of FP ABIs
803 * MIPS FP ABI Variants:: Supported FP ABIs
804 * MIPS FP ABI Selection:: Automatic selection of FP ABI
805 * MIPS FP ABI Compatibility:: Linking different FP ABI variants
808 @node MIPS FP ABI History
809 @subsection History of FP ABIs
[all …]
/toolchain/binutils/binutils-2.25/cpu/
Dsh64-compact.cpu48 (name FP-INSN)
630 (FP-INSN)
638 (FP-INSN)
646 (FP-INSN)
654 (FP-INSN)
662 (FP-INSN)
668 (FP-INSN)
674 (FP-INSN)
682 (FP-INSN)
695 (FP-INSN)
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/tic4x/
Daddressing.s35 bnluf Type_BI ; No latched FP underflow branch (10010)
36 bluf Type_BI ; Latched FP underflow branch (10011)
37 bzuf Type_BI ; Zero or FP underflow branch (10100)
67 ldinluf R0,R0 ; No latched FP underflow load (10010)
68 ldiluf R0,R0 ; Latched FP underflow load (10011)
69 ldizuf R0,R0 ; Zero or FP underflow load (10100)

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