1; Hitachi SHcompact instruction set description.  -*- Scheme -*-
2;
3; Copyright 2000, 2007, 2009 Free Software Foundation, Inc.
4;
5; Contributed by Red Hat Inc; developed under contract from Hitachi
6; Semiconductor (America) Inc.
7;
8; This file is part of the GNU Binutils.
9;
10; This program is free software; you can redistribute it and/or modify
11; it under the terms of the GNU General Public License as published by
12; the Free Software Foundation; either version 3 of the License, or
13; (at your option) any later version.
14;
15; This program is distributed in the hope that it will be useful,
16; but WITHOUT ANY WARRANTY; without even the implied warranty of
17; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18; GNU General Public License for more details.
19;
20; You should have received a copy of the GNU General Public License
21; along with this program; if not, write to the Free Software
22; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
23; MA 02110-1301, USA.
24
25; dshcf -- define-normal-sh-compact-field
26
27(define-pmacro (dshcf xname xcomment ignored xstart xlength)
28  (dnf xname xcomment ((ISA compact)) xstart xlength))
29
30; dshcop -- define-normal-sh-compact-operand
31
32(define-pmacro (dshcop xname xcomment ignored xhardware xfield)
33  (dnop xname xcomment ((ISA compact)) xhardware xfield))
34
35
36; SHcompact-specific attributes.
37
38(define-attr
39  (for insn)
40  (type boolean)
41  (name ILLSLOT)
42  (comment "instruction may not appear in a delay slot")
43)
44
45(define-attr
46  (for insn)
47  (type boolean)
48  (name FP-INSN)
49  (comment "floating point instruction")
50)
51
52(define-keyword
53  (name frc-names)
54  (attrs (ISA compact))
55  (print-name h-frc)
56  (values (fr0   0) (fr1   1) (fr2   2) (fr3   3) (fr4   4) (fr5   5)
57	  (fr6   6) (fr7   7) (fr8   8) (fr9   9) (fr10 10) (fr11 11)
58	  (fr12 12) (fr13 13) (fr14 14) (fr15 15))
59)
60
61(define-keyword
62  (name drc-names)
63  (attrs (ISA compact))
64  (print-name h-drc)
65  (values (dr0 0) (dr2 2) (dr4 4) (dr6 6) (dr8 8) (dr10 10) (dr12 12) (dr14 14))
66)
67
68(define-keyword
69  (name xf-names)
70  (attrs (ISA compact))
71  (print-name h-xf)
72  (values (xf0   0) (xf1   1) (xf2   2) (xf3   3) (xf4   4) (xf5   5)
73	  (xf6   6) (xf7   7) (xf8   8) (xf9   9) (xf10 10) (xf11 11)
74	  (xf12 12) (xf13 13) (xf14 14) (xf15 15))
75)
76
77; Hardware specific to the SHcompact mode.
78
79(define-pmacro (front) (mul 16 frbit))
80(define-pmacro (back) (mul 16 (not frbit)))
81
82(define-hardware
83  (name h-frc)
84  (comment "Single precision floating point registers")
85  (attrs VIRTUAL (ISA compact))
86  (indices extern-keyword frc-names)
87  (type register SF (16))
88  (get (index) (reg h-fr (add (front) index)))
89  (set (index newval) (set (reg h-fr (add (front) index)) newval))
90)
91
92(define-hardware
93  (name h-drc)
94  (comment "Double precision floating point registers")
95  (attrs VIRTUAL (ISA compact))
96  (indices extern-keyword drc-names)
97  (type register DF (8))
98  (get (index) (reg h-dr (add (front) index)))
99  (set (index newval) (set (reg h-dr (add (front) index)) newval))
100)
101
102(define-hardware
103  (name h-xf)
104  (comment "Extended single precision floating point registers")
105  (attrs VIRTUAL (ISA compact))
106  (indices extern-keyword xf-names)
107  (type register SF (16))
108  (get (index) (reg h-fr (add (back) index)))
109  (set (index newval) (set (reg h-fr (add (back) index)) newval))
110)
111
112(define-hardware
113  (name h-xd)
114  (comment "Extended double precision floating point registers")
115  (attrs VIRTUAL (ISA compact))
116  (indices extern-keyword frc-names)
117  (type register DF (8))
118  (get (index) (reg h-dr (add (back) index)))
119  (set (index newval) (set (reg h-dr (add (back) index)) newval))
120)
121
122(define-hardware
123  (name h-fvc)
124  (comment "Single precision floating point vectors")
125  (attrs VIRTUAL (ISA compact))
126  (indices keyword "" ((fv0 0) (fv4 4) (fv8 8) (fv12 12)))
127  (type register SF (4))
128  (get (index) (reg h-fr (add (front) index)))
129  (set (index newval) (set (reg h-fr (add (front) index)) newval))
130)
131
132(define-hardware
133  (name h-fpccr)
134  (comment "SHcompact floating point status/control register")
135  (attrs VIRTUAL (ISA compact))
136  (type register SI)
137  (get () (or (or (or (raw-reg h-fpscr) (sll SI prbit 19)) (sll SI szbit 20)) (sll SI frbit 21)))
138  (set (newvalue) (sequence ()
139			    (set (reg h-fpscr) newvalue)
140			    (set prbit (and (srl newvalue 19) 1))
141			    (set szbit (and (srl newvalue 20) 1))
142			    (set frbit (and (srl newvalue 21) 1))))
143)
144
145(define-hardware
146  (name h-gbr)
147  (comment "Global base register")
148  (attrs VIRTUAL (ISA compact))
149  (type register SI)
150  (get () (subword SI (raw-reg h-gr 16) 1))
151  (set (newval) (set (raw-reg h-gr 16) (ext DI newval)))
152)
153
154(define-hardware
155  (name h-pr)
156  (comment "Procedure link register")
157  (attrs VIRTUAL (ISA compact))
158  (type register SI)
159  (get () (subword SI (raw-reg h-gr 18) 1))
160  (set (newval) (set (raw-reg h-gr 18) (ext DI newval)))
161)
162
163(define-hardware
164  (name h-macl)
165  (comment "Multiple-accumulate low register")
166  (attrs VIRTUAL (ISA compact))
167  (type register SI)
168  (get () (subword SI (raw-reg h-gr 17) 1))
169  (set (newval) (set (raw-reg h-gr 17) (-join-si (subword SI (raw-reg h-gr 17) 0) newval)))
170)
171
172(define-hardware
173  (name h-mach)
174  (comment "Multiply-accumulate high register")
175  (attrs VIRTUAL (ISA compact))
176  (type register SI)
177  (get () (subword SI (raw-reg h-gr 17) 0))
178  (set (newval) (set (raw-reg h-gr 17) (-join-si newval (subword SI (raw-reg h-gr 17) 1))))
179)
180
181(define-hardware
182  (name h-tbit)
183  (comment "Condition code flag")
184  (attrs VIRTUAL (ISA compact))
185  (type register BI)
186  (get () (and BI (raw-reg h-gr 19) 1))
187  (set (newval) (set (raw-reg h-gr 19) (or (and (raw-reg h-gr 19) (inv DI 1)) (zext DI newval))))
188)
189
190
191(dshcf f-op4     "Opcode (4 bits)"         ()  15   4)
192(dshcf f-op8     "Opcode (8 bits)"         ()  15   8)
193(dshcf f-op16    "Opcode (16 bits)"        ()  15  16)
194
195(dshcf f-sub4    "Sub opcode (4 bits)"     ()   3   4)
196(dshcf f-sub8    "Sub opcode (8 bits)"     ()   7   8)
197(dshcf f-sub10   "Sub opcode (10 bits)"    ()   9  10)
198
199(dshcf f-rn      "Register selector n"     ()  11   4)
200(dshcf f-rm      "Register selector m"     ()   7   4)
201
202(dshcf f-8-1     "One bit at bit 8"        ()   8   1)
203
204(df  f-disp8  "Displacement (8 bits)"  ((ISA compact) PCREL-ADDR) 7 8 INT
205     ((value pc) (sra SI value 1))
206     ((value pc) (add SI (sll SI value 1) (add pc 4))))
207
208(df  f-disp12 "Displacement (12 bits)" ((ISA compact) PCREL-ADDR) 11 12 INT
209     ((value pc) (sra SI value 1))
210     ((value pc) (add SI (sll SI value 1) (add pc 4))))
211
212(dshcf f-imm8    "Immediate (8 bits)"      ()   7   8)
213(dshcf f-imm4    "Immediate (4 bits)"      ()   3   4)
214
215(df f-imm4x2     "Immediate (4 bits)"      ((ISA compact)) 3 4 UINT
216    ((value pc) (srl SI value 1))
217    ((value pc) (sll SI value 1)))
218
219(df f-imm4x4     "Immediate (4 bits)"      ((ISA compact)) 3 4 UINT
220    ((value pc) (srl SI value 2))
221    ((value pc) (sll SI value 2)))
222
223(df f-imm8x2     "Immediate (8 bits)"      ((ISA compact)) 7 8 UINT
224    ((value pc) (sra SI value 1))
225    ((value pc) (sll SI value 1)))
226
227(df f-imm8x4     "Immediate (8 bits)"      ((ISA compact)) 7 8 UINT
228    ((value pc) (sra SI value 2))
229    ((value pc) (sll SI value 2)))
230
231(df f-dn "Double selector n" ((ISA compact)) 11 3 UINT
232    ((value pc) (srl SI value 1))
233    ((value pc) (sll SI value 1)))
234
235(df f-dm         "Double selector m"       ((ISA compact)) 7 3 UINT
236    ((value pc) (srl SI value 1))
237    ((value pc) (sll SI value 1)))
238
239(df f-vn         "Vector selector n"       ((ISA compact)) 11 2 UINT
240    ((value pc) (srl SI value 2))
241    ((value pc) (sll SI value 2)))
242
243(df f-vm         "Vector selector m"       ((ISA compact)) 9 2 UINT
244    ((value pc) (srl SI value 2))
245    ((value pc) (sll SI value 2)))
246
247(df f-xn         "Extended selector n"     ((ISA compact)) 11 3 UINT
248    ((value pc) (srl SI value 1))
249    ((value pc) (add SI (sll SI value 1) 1)))
250
251(df f-xm         "Extended selector m"     ((ISA compact)) 7 3 UINT
252    ((value pc) (srl SI value 1))
253    ((value pc) (add SI (sll SI value 1) 1)))
254
255
256; Operands.
257
258(dshcop rm     "Left general purpose register"          ()   h-grc   f-rm)
259(dshcop rn     "Right general purpose register"         ()   h-grc   f-rn)
260(dshcop r0     "Register 0"                             ()   h-grc   0)
261
262(dshcop frn    "Single precision register"              ()   h-frc   f-rn)
263(dshcop frm    "Single precision register"              ()   h-frc   f-rm)
264
265(dshcop fvn    "Left floating point vector"             ()   h-fvc   f-vn)
266(dshcop fvm    "Right floating point vector"            ()   h-fvc   f-vm)
267
268(dshcop drn    "Left double precision register"         ()   h-drc   f-dn)
269(dshcop drm    "Right double precision register"        ()   h-drc   f-dm)
270
271(dshcop imm4   "Immediate value (4 bits)"		()   h-sint  f-imm4)
272(dshcop imm8   "Immediate value (8 bits)"               ()   h-sint  f-imm8)
273(dshcop uimm8  "Immediate value (8 bits unsigned)"      ()   h-uint  f-imm8)
274
275(dshcop imm4x2 "Immediate value (4 bits, 2x scale)"     ()   h-uint  f-imm4x2)
276(dshcop imm4x4 "Immediate value (4 bits, 4x scale)"     ()   h-uint  f-imm4x4)
277(dshcop imm8x2 "Immediate value (8 bits, 2x scale)"     ()   h-uint  f-imm8x2)
278(dshcop imm8x4 "Immediate value (8 bits, 4x scale)"     ()   h-uint  f-imm8x4)
279
280(dshcop disp8  "Displacement (8 bits)"                  ()   h-iaddr f-disp8)
281(dshcop disp12 "Displacement (12 bits)"                 ()   h-iaddr f-disp12)
282
283(dshcop rm64   "Register m (64 bits)"                   ()   h-gr    f-rm)
284(dshcop rn64   "Register n (64 bits)"                   ()   h-gr    f-rn)
285
286(dshcop gbr    "Global base register"                   ()   h-gbr   f-nil)
287(dshcop pr     "Procedure link register"                ()   h-pr    f-nil)
288
289(dshcop fpscr  "Floating point status/control register" ()   h-fpccr f-nil)
290
291(dshcop tbit   "Condition code flag"                    ()   h-tbit  f-nil)
292(dshcop sbit   "Multiply-accumulate saturation flag"    ()   h-sbit  f-nil)
293(dshcop mbit   "Divide-step M flag"                     ()   h-mbit  f-nil)
294(dshcop qbit   "Divide-step Q flag"                     ()   h-qbit  f-nil)
295(dshcop fpul   "Floating point ???"			()   h-fr    32)
296
297(dshcop frbit  "Floating point register bank bit"       ()   h-frbit f-nil)
298(dshcop szbit  "Floating point transfer size bit"       ()   h-szbit f-nil)
299(dshcop prbit  "Floating point precision bit"           ()   h-prbit f-nil)
300
301(dshcop macl   "Multiply-accumulate low register"       ()   h-macl  f-nil)
302(dshcop mach   "Multiply-accumulate high register"      ()   h-mach  f-nil)
303
304
305(define-operand (name fsdm) (comment "bar")
306  (attrs (ISA compact)) (type h-frc) (index f-rm) (handlers (parse "fsd")))
307
308(define-operand (name fsdn) (comment "bar")
309  (attrs (ISA compact)) (type h-frc) (index f-rn))
310
311
312; Cover macro to dni to indicate these are all SHcompact instructions.
313; dshmi: define-normal-sh-compact-insn
314
315(define-pmacro (dshci xname xcomment xattrs xsyntax xformat xsemantics)
316  (define-insn
317    (name (.sym xname -compact))
318    (comment xcomment)
319    (.splice attrs (.unsplice xattrs) (ISA compact))
320    (syntax xsyntax)
321    (format xformat)
322    (semantics xsemantics)))
323
324(define-pmacro (dr operand) (reg h-dr (index-of operand)))
325(define-pmacro (xd x) (reg h-xd (and (index-of x) (inv QI 1))))
326
327(dshci add "Add"
328       ()
329       "add $rm, $rn"
330       (+ (f-op4 3) rn rm (f-sub4 12))
331       (set rn (add rn rm)))
332
333(dshci addi "Add immediate"
334       ()
335       "add #$imm8, $rn"
336       (+ (f-op4 7) rn imm8)
337       (set rn (add rn (ext SI (and QI imm8 255)))))
338
339(dshci addc "Add with carry"
340       ()
341       "addc $rm, $rn"
342       (+ (f-op4 3) rn rm (f-sub4 14))
343       (sequence ((BI flag))
344		 (set flag (add-cflag rn rm tbit))
345		 (set rn (addc rn rm tbit))
346		 (set tbit flag)))
347
348(dshci addv "Add with overflow"
349       ()
350       "addv $rm, $rn"
351       (+ (f-op4 3) rn rm (f-sub4 15))
352       (sequence ((BI t))
353		 (set t (add-oflag rn rm 0))
354		 (set rn (add rn rm))
355		 (set tbit t)))
356
357(dshci and "Bitwise AND"
358       ()
359       "and $rm64, $rn64"
360       (+ (f-op4 2) rn64 rm64 (f-sub4 9))
361       (set rn64 (and rm64 rn64)))
362
363(dshci andi "Bitwise AND immediate"
364       ()
365       "and #$uimm8, r0"
366       (+ (f-op8 #xc9) uimm8)
367       (set r0 (and r0 (zext DI uimm8))))
368
369(dshci andb "Bitwise AND memory byte"
370       ()
371       "and.b #$imm8, @(r0, gbr)"
372       (+ (f-op8 #xcd) imm8)
373       (sequence ((DI addr) (UQI data))
374		 (set addr (add r0 gbr))
375		 (set data (and (mem UQI addr) imm8))
376		 (set (mem UQI addr) data)))
377
378(dshci bf "Conditional branch"
379       ()
380       "bf $disp8"
381       (+ (f-op8 #x8b) disp8)
382       (if (not tbit)
383	   (set pc disp8)))
384
385(dshci bfs "Conditional branch with delay slot"
386       ()
387       "bf/s $disp8"
388       (+ (f-op8 #x8f) disp8)
389       (if (not tbit)
390	   (delay 1 (set pc disp8))))
391
392(dshci bra "Branch"
393       ()
394       "bra $disp12"
395       (+ (f-op4 10) disp12)
396       (delay 1 (set pc disp12)))
397
398(dshci braf "Branch far"
399       ()
400       "braf $rn"
401       (+ (f-op4 0) rn (f-sub8 35))
402       (delay 1 (set pc (add (ext DI rn) (add pc 4)))))
403
404(dshci brk "Breakpoint"
405       ()
406       "brk"
407       (+ (f-op16 59))
408       (c-call "sh64_break" pc))
409
410(dshci bsr "Branch to subroutine"
411       ()
412       "bsr $disp12"
413       (+ (f-op4 11) disp12)
414       (delay 1 (sequence ()
415			  (set pr (add pc 4))
416			  (set pc disp12))))
417
418(dshci bsrf "Branch to far subroutine"
419       ()
420       "bsrf $rn"
421       (+ (f-op4 0) rn (f-sub8 3))
422       (delay 1 (sequence ()
423			  (set pr (add pc 4))
424			  (set pc (add (ext DI rn) (add pc 4))))))
425
426(dshci bt "Conditional branch"
427       ()
428       "bt $disp8"
429       (+ (f-op8 #x89) disp8)
430       (if tbit
431	   (set pc disp8)))
432
433(dshci bts "Conditional branch with delay slot"
434       ()
435       "bt/s $disp8"
436       (+ (f-op8 #x8d) disp8)
437       (if tbit
438	   (delay 1 (set pc disp8))))
439
440(dshci clrmac "Clear MACL and MACH"
441       ()
442       "clrmac"
443       (+ (f-op16 40))
444       (sequence ()
445		 (set macl 0)
446		 (set mach 0)))
447
448(dshci clrs "Clear S-bit"
449       ()
450       "clrs"
451       (+ (f-op16 72))
452       (set sbit 0))
453
454(dshci clrt "Clear T-bit"
455       ()
456       "clrt"
457       (+ (f-op16 8))
458       (set tbit 0))
459
460(dshci cmpeq "Compare if equal"
461       ()
462       "cmp/eq $rm, $rn"
463       (+ (f-op4 3) rn rm (f-sub4 0))
464       (set tbit (eq rm rn)))
465
466(dshci cmpeqi "Compare if equal (immediate)"
467       ()
468       "cmp/eq #$imm8, r0"
469       (+ (f-op8 #x88) imm8)
470       (set tbit (eq r0 (ext SI (and QI imm8 255)))))
471
472(dshci cmpge "Compare if greater than or equal"
473       ()
474       "cmp/ge $rm, $rn"
475       (+ (f-op4 3) rn rm (f-sub4 3))
476       (set tbit (ge rn rm)))
477
478(dshci cmpgt "Compare if greater than"
479       ()
480       "cmp/gt $rm, $rn"
481       (+ (f-op4 3) rn rm (f-sub4 7))
482       (set tbit (gt rn rm)))
483
484(dshci cmphi "Compare if greater than (unsigned)"
485       ()
486       "cmp/hi $rm, $rn"
487       (+ (f-op4 3) rn rm (f-sub4 6))
488       (set tbit (gtu rn rm)))
489
490(dshci cmphs "Compare if greater than or equal (unsigned)"
491       ()
492       "cmp/hs $rm, $rn"
493       (+ (f-op4 3) rn rm (f-sub4 2))
494       (set tbit (geu rn rm)))
495
496(dshci cmppl "Compare if greater than zero"
497       ()
498       "cmp/pl $rn"
499       (+ (f-op4 4) rn (f-sub8 21))
500       (set tbit (gt rn 0)))
501
502(dshci cmppz "Compare if greater than or equal zero"
503       ()
504       "cmp/pz $rn"
505       (+ (f-op4 4) rn (f-sub8 17))
506       (set tbit (ge rn 0)))
507
508(dshci cmpstr "Compare bytes"
509       ()
510       "cmp/str $rm, $rn"
511       (+ (f-op4 2) rn rm (f-sub4 12))
512       (sequence ((BI t) (SI temp))
513		 (set temp (xor rm rn))
514		 (set t (eq (and temp #xff000000) 0))
515		 (set t (or (eq (and temp #xff0000) 0) t))
516		 (set t (or (eq (and temp #xff00) 0) t))
517		 (set t (or (eq (and temp #xff) 0) t))
518		 (set tbit (if BI (gtu t 0) 1 0))))
519
520(dshci div0s "Initialise divide-step state for signed division"
521       ()
522       "div0s $rm, $rn"
523       (+ (f-op4 2) rn rm (f-sub4 7))
524       (sequence ()
525		 (set qbit (srl rn 31))
526		 (set mbit (srl rm 31))
527		 (set tbit (if BI (eq (srl rm 31) (srl rn 31)) 0 1))))
528
529(dshci div0u "Initialise divide-step state for unsigned division"
530       ()
531       "div0u"
532       (+ (f-op16 25))
533       (sequence ()
534		 (set tbit 0)
535		 (set qbit 0)
536		 (set mbit 0)))
537
538(dshci div1 "Divide step"
539       ()
540       "div1 $rm, $rn"
541       (+ (f-op4 3) rn rm (f-sub4 4))
542       (sequence ((BI oldq) (SI tmp0) (UQI tmp1))
543		 (set oldq qbit)
544		 (set qbit (srl rn 31))
545		 (set rn (or (sll rn 1) (zext SI tbit)))
546		 (if (not oldq)
547		     (if (not mbit)
548			 (sequence ()
549				   (set tmp0 rn)
550				   (set rn (sub rn rm))
551				   (set tmp1 (gtu rn tmp0))
552				   (if (not qbit)
553				       (set qbit (if BI tmp1 1 0))
554				       (set qbit (if BI (eq tmp1 0) 1 0))))
555			 (sequence ()
556				   (set tmp0 rn)
557				   (set rn (add rn rm))
558				   (set tmp1 (ltu rn tmp0))
559				   (if (not qbit)
560				       (set qbit (if BI (eq tmp1 0) 1 0))
561				       (set qbit (if BI tmp1 1 0)))))
562		     (if (not mbit)
563			 (sequence ()
564				   (set tmp0 rn)
565				   (set rn (add rm rn))
566				   (set tmp1 (ltu rn tmp0))
567				   (if (not qbit)
568				       (set qbit (if BI tmp1 1 0))
569				       (set qbit (if BI (eq tmp1 0) 1 0))))
570			 (sequence ()
571				   (set tmp0 rn)
572				   (set rn (sub rn rm))
573				   (set tmp1 (gtu rn tmp0))
574				   (if (not qbit)
575				       (set qbit (if BI (eq tmp1 0) 1 0))
576				       (set qbit (if BI tmp1 1 0))))))
577		 (set tbit (if BI (eq qbit mbit) 1 0))))
578
579(dshci dmulsl "Multiply long (signed)"
580       ()
581       "dmuls.l $rm, $rn"
582       (+ (f-op4 3) rn rm (f-sub4 13))
583       (sequence ((DI result))
584		 (set result (mul (ext DI rm) (ext DI rn)))
585		 (set mach (subword SI result 0))
586		 (set macl (subword SI result 1))))
587
588(dshci dmulul "Multiply long (unsigned)"
589       ()
590       "dmulu.l $rm, $rn"
591       (+ (f-op4 3) rn rm (f-sub4 5))
592       (sequence ((DI result))
593		 (set result (mul (zext DI rm) (zext DI rn)))
594		 (set mach (subword SI result 0))
595		 (set macl (subword SI result 1))))
596
597(dshci dt "Decrement and set"
598       ()
599       "dt $rn"
600       (+ (f-op4 4) rn (f-sub8 16))
601       (sequence ()
602		 (set rn (sub rn 1))
603		 (set tbit (eq rn 0))))
604
605(dshci extsb "Sign extend byte"
606       ()
607       "exts.b $rm, $rn"
608       (+ (f-op4 6) rn rm (f-sub4 14))
609       (set rn (ext SI (subword QI rm 3))))
610
611(dshci extsw "Sign extend word"
612       ()
613       "exts.w $rm, $rn"
614       (+ (f-op4 6) rn rm (f-sub4 15))
615       (set rn (ext SI (subword HI rm 1))))
616
617(dshci extub "Zero extend byte"
618       ()
619       "extu.b $rm, $rn"
620       (+ (f-op4 6) rn rm (f-sub4 12))
621       (set rn (zext SI (subword QI rm 3))))
622
623(dshci extuw "Zero etxend word"
624       ()
625       "extu.w $rm, $rn"
626       (+ (f-op4 6) rn rm (f-sub4 13))
627       (set rn (zext SI (subword HI rm 1))))
628
629(dshci fabs "Floating point absolute"
630       (FP-INSN)
631       "fabs $fsdn"
632       (+ (f-op4 15) fsdn (f-sub8 #x5d))
633       (if prbit
634	   (set (dr fsdn) (c-call DF "sh64_fabsd" (dr fsdn)))
635	   (set fsdn (c-call SF "sh64_fabss" fsdn))))
636
637(dshci fadd "Floating point add"
638       (FP-INSN)
639       "fadd $fsdm, $fsdn"
640       (+ (f-op4 15) fsdn fsdm (f-sub4 0))
641       (if prbit
642	   (set (dr fsdn) (c-call DF "sh64_faddd" (dr fsdm) (dr fsdn)))
643	   (set fsdn (c-call SF "sh64_fadds" fsdm fsdn))))
644
645(dshci fcmpeq "Floating point compare equal"
646       (FP-INSN)
647       "fcmp/eq $fsdm, $fsdn"
648       (+ (f-op4 15) fsdn fsdm (f-sub4 4))
649       (if prbit
650	   (set tbit (c-call BI "sh64_fcmpeqd" (dr fsdm) (dr fsdn)))
651	   (set tbit (c-call BI "sh64_fcmpeqs" fsdm fsdn))))
652
653(dshci fcmpgt "Floating point compare greater than"
654       (FP-INSN)
655       "fcmp/gt $fsdm, $fsdn"
656       (+ (f-op4 15) fsdn fsdm (f-sub4 5))
657       (if prbit
658	   (set tbit (c-call BI "sh64_fcmpgtd" (dr fsdn) (dr fsdm)))
659	   (set tbit (c-call BI "sh64_fcmpgts" fsdn fsdm))))
660
661(dshci fcnvds "Floating point convert (double to single)"
662       (FP-INSN)
663       "fcnvds $drn, fpul"
664       (+ (f-op4 15) drn (f-8-1 10) (f-sub8 #xbd))
665       (set fpul (c-call SF "sh64_fcnvds" drn)))
666
667(dshci fcnvsd "Floating point convert (single to double)"
668       (FP-INSN)
669       "fcnvsd fpul, $drn"
670       (+ (f-op4 15) drn (f-8-1 0) (f-sub8 #xad))
671       (set drn (c-call DF "sh64_fcnvsd" fpul)))
672
673(dshci fdiv "Floating point divide"
674       (FP-INSN)
675       "fdiv $fsdm, $fsdn"
676       (+ (f-op4 15) fsdn fsdm (f-sub4 3))
677       (if prbit
678	   (set (dr fsdn) (c-call DF "sh64_fdivd" (dr fsdn) (dr fsdm)))
679	   (set fsdn (c-call SF "sh64_fdivs" fsdn fsdm))))
680
681(dshci fipr "Floating point inner product"
682       (FP-INSN)
683       "fipr $fvm, $fvn"
684       (+ (f-op4 15) fvn fvm (f-sub8 #xed))
685       (sequence ((QI m) (QI n) (SF res))
686		 (set m (index-of fvm))
687		 (set n (index-of fvn))
688		 (set res (c-call SF "sh64_fmuls" fvm fvn))
689		 (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-frc (add m 1)) (reg h-frc (add n 1)))))
690		 (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-frc (add m 2)) (reg h-frc (add n 2)))))
691		 (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-frc (add m 3)) (reg h-frc (add n 3)))))
692		 (set (reg h-frc (add n 3)) res)))
693
694(dshci flds "Floating point load status register"
695       (FP-INSN)
696       "flds $frn"
697       (+ (f-op4 15) frn (f-sub8 #x1d))
698       (set fpul frn))
699
700(dshci fldi0 "Floating point load immediate 0.0"
701       (FP-INSN)
702       "fldi0 $frn"
703       (+ (f-op4 15) frn (f-sub8 #x8d))
704       (set frn (c-call SF "sh64_fldi0")))
705
706(dshci fldi1 "Floating point load immediate 1.0"
707       (FP-INSN)
708       "fldi1 $frn"
709       (+ (f-op4 15) frn (f-sub8 #x9d))
710       (set frn (c-call SF "sh64_fldi1")))
711
712(dshci float "Floating point integer conversion"
713       (FP-INSN)
714       "float fpul, $fsdn"
715       (+ (f-op4 15) fsdn (f-sub8 #x2d))
716       (if prbit
717	   (set (dr fsdn) (c-call DF "sh64_floatld" fpul))
718	   (set fsdn (c-call SF "sh64_floatls" fpul))))
719
720(dshci fmac "Floating point multiply and accumulate"
721       (FP-INSN)
722       "fmac fr0, $frm, $frn"
723       (+ (f-op4 15) frn frm (f-sub4 14))
724       (set frn (c-call SF "sh64_fmacs" (reg h-frc 0) frm frn)))
725
726(define-pmacro (even x) (eq (and x 1) 0))
727(define-pmacro (odd x)  (eq (and x 1) 1))
728(define-pmacro (extd x) (odd (index-of x)))
729
730(dshci fmov1 "Floating point move (register to register)"
731       (FP-INSN)
732       "fmov $frm, $frn"
733       (+ (f-op4 15) frn frm (f-sub4 12))
734       (if (not szbit)
735	   ; single precision operation
736	   (set frn frm)
737	   ; double or extended operation
738	   (if (extd frm)
739	       (if (extd frn)
740		   (set (xd frn) (xd frm))
741		   (set (dr frn) (xd frm)))
742	       (if (extd frn)
743		   (set (xd frn) (dr frm))
744		   (set (dr frn) (dr frm))))))
745
746(dshci fmov2 "Floating point load"
747       (FP-INSN)
748       "fmov @$rm, $frn"
749       (+ (f-op4 15) frn rm (f-sub4 8))
750       (if (not szbit)
751	   ; single precision operation
752	   (set frn (mem SF rm))
753	   ; double or extended operation
754	   (if (extd frn)
755	       (set (xd frn) (mem DF rm))
756	       (set (dr frn) (mem DF rm)))))
757
758(dshci fmov3 "Floating point load (post-increment)"
759       (FP-INSN)
760       "fmov @${rm}+, frn"
761       (+ (f-op4 15) frn rm (f-sub4 9))
762       (if (not szbit)
763	   ; single precision operation
764	   (sequence ()
765		     (set frn (mem SF rm))
766		     (set rm (add rm 4)))
767	   ; double or extended operation
768	   (sequence ()
769		     (if (extd frn)
770			 (set (xd frn) (mem DF rm))
771			 (set (dr frn) (mem DF rm)))
772		     (set rm (add rm 8)))))
773
774(dshci fmov4 "Floating point load (register/register indirect)"
775       (FP-INSN)
776       "fmov @(r0, $rm), $frn"
777       (+ (f-op4 15) frn rm (f-sub4 6))
778       (if (not szbit)
779	   ; single precision operation
780	   (set frn (mem SF (add r0 rm)))
781	   ; double or extended operation
782	   (if (extd frn)
783	       (set (xd frn) (mem DF (add r0 rm)))
784	       (set (dr frn) (mem DF (add r0 rm))))))
785
786(dshci fmov5 "Floating point store"
787       (FP-INSN)
788       "fmov $frm, @$rn"
789       (+ (f-op4 15) rn frm (f-sub4 10))
790       (if (not szbit)
791	   ; single precision operation
792	   (set (mem SF rn) frm)
793	   ; double or extended operation
794	   (if (extd frm)
795	       (set (mem DF rn) (xd frm))
796	       (set (mem DF rn) (dr frm)))))
797
798(dshci fmov6 "Floating point store (pre-decrement)"
799       (FP-INSN)
800       "fmov $frm, @-$rn"
801       (+ (f-op4 15) rn frm (f-sub4 11))
802       (if (not szbit)
803	   ; single precision operation
804	   (sequence ()
805		     (set rn (sub rn 4))
806		     (set (mem SF rn) frm))
807	   ; double or extended operation
808	   (sequence ()
809		     (set rn (sub rn 8))
810		     (if (extd frm)
811			 (set (mem DF rn) (xd frm))
812			 (set (mem DF rn) (dr frm))))))
813
814(dshci fmov7 "Floating point store (register/register indirect)"
815       (FP-INSN)
816       "fmov $frm, @(r0, $rn)"
817       (+ (f-op4 15) rn frm (f-sub4 7))
818       (if (not szbit)
819	   ; single precision operation
820	   (set (mem SF (add r0 rn)) frm)
821	   ; double or extended operation
822	   (if (extd frm)
823	       (set (mem DF (add r0 rn)) (xd frm))
824	       (set (mem DF (add r0 rn)) (dr frm)))))
825
826(dshci fmul "Floating point multiply"
827       (FP-INSN)
828       "fmul $fsdm, $fsdn"
829       (+ (f-op4 15) fsdn fsdm (f-sub4 2))
830       (if prbit
831	   (set (dr fsdn) (c-call DF "sh64_fmuld" (dr fsdm) (dr fsdn)))
832	   (set fsdn (c-call SF "sh64_fmuls" fsdm fsdn))))
833
834(dshci fneg "Floating point negate"
835       (FP-INSN)
836       "fneg $fsdn"
837       (+ (f-op4 15) fsdn (f-sub8 #x4d))
838       (if prbit
839	   (set (dr fsdn) (c-call DF "sh64_fnegd" (dr fsdn)))
840	   (set fsdn (c-call SF "sh64_fnegs" fsdn))))
841
842(dshci frchg "Toggle floating point register banks"
843       (FP-INSN)
844       "frchg"
845       (+ (f-op16 #xfbfd))
846       (set frbit (not frbit)))
847
848(dshci fschg "Set size of floating point transfers"
849       (FP-INSN)
850       "fschg"
851       (+ (f-op16 #xf3fd))
852       (set szbit (not szbit)))
853
854(dshci fsqrt "Floating point square root"
855       (FP-INSN)
856       "fsqrt $fsdn"
857       (+ (f-op4 15) fsdn (f-sub8 #x6d))
858       (if prbit
859	   (set (dr fsdn) (c-call DF "sh64_fsqrtd" (dr fsdn)))
860	   (set fsdn (c-call SF "sh64_fsqrts" fsdn))))
861
862(dshci fsts "Floating point store status register"
863       (FP-INSN)
864      "fsts fpul, $frn"
865       (+ (f-op4 15) frn (f-sub8 13))
866       (set frn fpul))
867
868(dshci fsub "Floating point subtract"
869       (FP-INSN)
870       "fsub $fsdm, $fsdn"
871       (+ (f-op4 15) fsdn fsdm (f-sub4 1))
872       (if prbit
873	   (set (dr fsdn) (c-call DF "sh64_fsubd" (dr fsdn) (dr fsdm)))
874	   (set fsdn (c-call SF "sh64_fsubs" fsdn fsdm))))
875
876(dshci ftrc "Floating point truncate"
877       (FP-INSN)
878       "ftrc $fsdn, fpul"
879       (+ (f-op4 15) fsdn (f-sub8 #x3d))
880       (set fpul (if SF prbit
881		     (c-call SF "sh64_ftrcdl" (dr fsdn))
882		     (c-call SF "sh64_ftrcsl" fsdn))))
883
884(dshci ftrv "Floating point transform vector"
885       (FP-INSN)
886       "ftrv xmtrx, $fvn"
887       (+ (f-op4 15) fvn (f-sub10 #x1fd))
888       (sequence ((QI n) (SF res))
889		 (set n (index-of fvn))
890		 (set res (c-call SF "sh64_fmuls" (reg h-xf 0) (reg h-frc n)))
891		 (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 4)  (reg h-frc (add n 1)))))
892		 (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 8)  (reg h-frc (add n 2)))))
893		 (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 12) (reg h-frc (add n 3)))))
894		 (set (reg h-frc n) res)
895		 (set res (c-call SF "sh64_fmuls" (reg h-xf 1) (reg h-frc n)))
896		 (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 5)  (reg h-frc (add n 1)))))
897		 (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 9)  (reg h-frc (add n 2)))))
898		 (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 13) (reg h-frc (add n 3)))))
899		 (set (reg h-frc (add n 1)) res)
900		 (set res (c-call SF "sh64_fmuls" (reg h-xf 2) (reg h-frc n)))
901		 (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 6)  (reg h-frc (add n 1)))))
902		 (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 10) (reg h-frc (add n 2)))))
903		 (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 14) (reg h-frc (add n 3)))))
904		 (set (reg h-frc (add n 2)) res)
905		 (set res (c-call SF "sh64_fmuls" (reg h-xf 3) (reg h-frc n)))
906		 (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 7)  (reg h-frc (add n 1)))))
907		 (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 11) (reg h-frc (add n 2)))))
908		 (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 15) (reg h-frc (add n 3)))))
909		 (set (reg h-frc (add n 3)) res)))
910
911(dshci jmp "Jump"
912       ()
913       "jmp @$rn"
914       (+ (f-op4 4) rn (f-sub8 43))
915       (delay 1 (set pc rn)))
916
917(dshci jsr "Jump to subroutine"
918       ()
919       "jsr @$rn"
920       (+ (f-op4 4) rn (f-sub8 11))
921       (delay 1 (sequence ()
922			  (set pr (add pc 4))
923			  (set pc rn))))
924
925(dshci ldc "Load control register (GBR)"
926       ()
927       "ldc $rn, gbr"
928       (+ (f-op4 4) rn (f-sub8 30))
929       (set gbr rn))
930
931(dshci ldcl "Load control register (GBR)"
932       ()
933       "ldc.l @${rn}+, gbr"
934       (+ (f-op4 4) rn (f-sub8 39))
935       (sequence ()
936		 (set gbr (mem SI rn))
937		 (set rn (add rn 4))))
938
939(dshci lds-fpscr "Load status register (FPSCR)"
940       ()
941       "lds $rn, fpscr"
942       (+ (f-op4 4) rn (f-sub8 106))
943       (set fpscr rn))
944
945(dshci ldsl-fpscr "Load status register (FPSCR)"
946       ()
947       "lds.l @${rn}+, fpscr"
948       (+ (f-op4 4) rn (f-sub8 102))
949       (sequence ()
950		 (set fpscr (mem SI rn))
951		 (set rn (add rn 4))))
952
953(dshci lds-fpul "Load status register (FPUL)"
954       ()
955       "lds $rn, fpul"
956       (+ (f-op4 4) rn (f-sub8 90))
957       ; Use subword to convert rn's mode.
958       (set fpul (subword SF rn 0)))
959
960(dshci ldsl-fpul "Load status register (FPUL)"
961       ()
962       "lds.l @${rn}+, fpul"
963       (+ (f-op4 4) rn (f-sub8 86))
964       (sequence ()
965		 (set fpul (mem SF rn))
966		 (set rn (add rn 4))))
967
968(dshci lds-mach "Load status register (MACH)"
969       ()
970       "lds $rn, mach"
971       (+ (f-op4 4) rn (f-sub8 10))
972       (set mach rn))
973
974(dshci ldsl-mach "Load status register (MACH), post-increment"
975       ()
976       "lds.l @${rn}+, mach"
977       (+ (f-op4 4) rn (f-sub8 6))
978       (sequence ()
979		 (set mach (mem SI rn))
980		 (set rn (add rn 4))))
981
982(dshci lds-macl "Load status register (MACL)"
983       ()
984       "lds $rn, macl"
985       (+ (f-op4 4) rn (f-sub8 26))
986       (set macl rn))
987
988(dshci ldsl-macl "Load status register (MACL), post-increment"
989       ()
990       "lds.l @${rn}+, macl"
991       (+ (f-op4 4) rn (f-sub8 22))
992       (sequence ()
993		 (set macl (mem SI rn))
994		 (set rn (add rn 4))))
995
996(dshci lds-pr "Load status register (PR)"
997       ()
998       "lds $rn, pr"
999       (+ (f-op4 4) rn (f-sub8 42))
1000       (set pr rn))
1001
1002(dshci ldsl-pr "Load status register (PR), post-increment"
1003       ()
1004       "lds.l @${rn}+, pr"
1005       (+ (f-op4 4) rn (f-sub8 38))
1006       (sequence ()
1007		 (set pr (mem SI rn))
1008		 (set rn (add rn 4))))
1009
1010(dshci macl "Multiply and accumulate (long)"
1011       ()
1012       "mac.l @${rm}+, @${rn}+"
1013       (+ (f-op4 0) rn rm (f-sub4 15))
1014       (sequence ((DI tmpry) (DI mac) (DI result) (SI x) (SI y))
1015		 (set x (mem SI rn))
1016		 (set rn (add rn 4))
1017		 (if (eq (index-of rn) (index-of rm))
1018		     (sequence ()
1019			       (set rn (add rn 4))
1020			       (set rm (add rm 4))))
1021		 (set y (mem SI rm))
1022		 (set rm (add rm 4))
1023		 (set tmpry (mul (zext DI x) (zext DI y)))
1024		 (set mac (or DI (sll (zext DI mach) 32) (zext DI macl)))
1025		 (set result (add mac tmpry))
1026		 (sequence ()
1027			   (if sbit
1028			       (sequence ((SI min) (SI max))
1029					 (set max (srl (inv DI 0) 16))
1030					; Preserve bit 48 for sign.
1031					 (set min (srl (inv DI 0) 15))
1032					 (if (gt result max)
1033					     (set result max)
1034					     (if (lt result min)
1035						 (set result min)))))
1036			   (set mach (subword SI result 0))
1037			   (set macl (subword SI result 1)))))
1038
1039(dshci macw "Multiply and accumulate (word)"
1040       ()
1041       "mac.w @${rm}+, @${rn}+"
1042       (+ (f-op4 4) rn rm (f-sub4 15))
1043       (sequence ((SI tmpry) (DI mac) (DI result) (HI x) (HI y))
1044		 (set x (mem HI rn))
1045		 (set rn (add rn 2))
1046		 (if (eq (index-of rn) (index-of rm))
1047		     (sequence ()
1048			       (set rn (add rn 2))
1049			       (set rm (add rm 2))))
1050		 (set y (mem HI rm))
1051		 (set rm (add rm 2))
1052		 (set tmpry (mul (zext SI x) (zext SI y)))
1053		 (if sbit
1054		     (sequence ()
1055			       (if (add-oflag tmpry macl 0)
1056				   (set mach 1))
1057			       (set macl (add tmpry macl)))
1058		     (sequence ()
1059			       (set mac (or DI (sll (zext DI mach) 32) (zext DI macl)))
1060			       (set result (add mac (ext DI tmpry)))
1061			       (set mach (subword SI result 0))
1062			       (set macl (subword SI result 1))))))
1063
1064(dshci mov "Move"
1065       ()
1066       "mov $rm64, $rn64"
1067       (+ (f-op4 6) rn64 rm64 (f-sub4 3))
1068       (set rn64 rm64))
1069
1070(dshci movi "Move immediate"
1071       ()
1072       "mov #$imm8, $rn"
1073       (+ (f-op4 14) rn imm8)
1074       (set rn (ext DI (and QI imm8 255))))
1075
1076(dshci movb1 "Store byte to memory (register indirect w/ zero displacement)"
1077       ()
1078       "mov.b $rm, @$rn"
1079       (+ (f-op4 2) rn rm (f-sub4 0))
1080       (set (mem UQI rn) (subword UQI rm 3)))
1081
1082(dshci movb2 "Store byte to memory (register indirect w/ pre-decrement)"
1083       ()
1084       "mov.b $rm, @-$rn"
1085       (+ (f-op4 2) rn rm (f-sub4 4))
1086       (sequence ((DI addr))
1087		 (set addr (sub rn 1))
1088		 (set (mem UQI addr) (subword UQI rm 3))
1089		 (set rn addr)))
1090
1091(dshci movb3 "Store byte to memory (register/register indirect)"
1092       ()
1093       "mov.b $rm, @(r0,$rn)"
1094       (+ (f-op4 0) rn rm (f-sub4 4))
1095       (set (mem UQI (add r0 rn)) (subword UQI rm 3)))
1096
1097(dshci movb4 "Store byte to memory (GBR-relative w/ displacement)"
1098       ()
1099       "mov.b r0, @($imm8, gbr)"
1100       (+ (f-op8 #xc0) imm8)
1101       (sequence ((DI addr))
1102		 (set addr (add gbr imm8))
1103		 (set (mem UQI addr) (subword UQI r0 3))))
1104
1105(dshci movb5 "Store byte to memory (register indirect w/ displacement)"
1106       ()
1107       "mov.b r0, @($imm4, $rm)"
1108       (+ (f-op8 #x80) rm imm4)
1109       (sequence ((DI addr))
1110		 (set addr (add rm imm4))
1111		 (set (mem UQI addr) (subword UQI r0 3))))
1112
1113(dshci movb6 "Load byte from memory (register indirect w/ zero displacement)"
1114       ()
1115       "mov.b @$rm, $rn"
1116       (+ (f-op4 6) rn rm (f-sub4 0))
1117       (set rn (ext SI (mem QI rm))))
1118
1119(dshci movb7 "Load byte from memory (register indirect w/ post-increment)"
1120       ()
1121       "mov.b @${rm}+, $rn"
1122       (+ (f-op4 6) rn rm (f-sub4 4))
1123       (sequence ((QI data))
1124		 (set data (mem QI rm))
1125		 (if (eq (index-of rm) (index-of rn))
1126		     (set rm (ext SI data))
1127		     (set rm (add rm 1)))
1128		 (set rn (ext SI data))))
1129
1130(dshci movb8 "Load byte from memory (register/register indirect)"
1131       ()
1132       "mov.b @(r0, $rm), $rn"
1133       (+ (f-op4 0) rn rm (f-sub4 12))
1134       (set rn (ext SI (mem QI (add r0 rm)))))
1135
1136(dshci movb9 "Load byte from memory (GBR-relative with displacement)"
1137       ()
1138       "mov.b @($imm8, gbr), r0"
1139       (+ (f-op8 #xc4) imm8)
1140       (set r0 (ext SI (mem QI (add gbr imm8)))))
1141
1142(dshci movb10 "Load byte from memory (register indirect w/ displacement)"
1143       ()
1144       "mov.b @($imm4, $rm), r0"
1145       (+ (f-op8 #x84) rm imm4)
1146       (set r0 (ext SI (mem QI (add rm imm4)))))
1147
1148(dshci movl1 "Store long word to memory (register indirect w/ zero displacement)"
1149       ()
1150       "mov.l $rm, @$rn"
1151       (+ (f-op4 2) rn rm (f-sub4 2))
1152       (set (mem SI rn) rm))
1153
1154(dshci movl2 "Store long word to memory (register indirect w/ pre-decrement)"
1155       ()
1156       "mov.l $rm, @-$rn"
1157       (+ (f-op4 2) rn rm (f-sub4 6))
1158       (sequence ((SI addr))
1159		 (set addr (sub rn 4))
1160		 (set (mem SI addr) rm)
1161		 (set rn addr)))
1162
1163(dshci movl3 "Store long word to memory (register/register indirect)"
1164       ()
1165       "mov.l $rm, @(r0, $rn)"
1166       (+ (f-op4 0) rn rm (f-sub4 6))
1167       (set (mem SI (add r0 rn)) rm))
1168
1169(dshci movl4 "Store long word to memory (GBR-relative w/ displacement)"
1170       ()
1171       "mov.l r0, @($imm8x4, gbr)"
1172       (+ (f-op8 #xc2) imm8x4)
1173       (set (mem SI (add gbr imm8x4)) r0))
1174
1175(dshci movl5 "Store long word to memory (register indirect w/ displacement)"
1176       ()
1177       "mov.l $rm, @($imm4x4, $rn)"
1178       (+ (f-op4 1) rn rm imm4x4)
1179       (set (mem SI (add rn imm4x4)) rm))
1180
1181(dshci movl6 "Load long word to memory (register indirect w/ zero displacement)"
1182       ()
1183       "mov.l @$rm, $rn"
1184       (+ (f-op4 6) rn rm (f-sub4 2))
1185       (set rn (mem SI rm)))
1186
1187(dshci movl7 "Load long word from memory (register indirect w/ post-increment)"
1188       ()
1189       "mov.l @${rm}+, $rn"
1190       (+ (f-op4 6) rn rm (f-sub4 6))
1191       (sequence ()
1192		 (set rn (mem SI rm))
1193		 (if (eq (index-of rm) (index-of rn))
1194		     (set rm rn)
1195		     (set rm (add rm 4)))))
1196
1197(dshci movl8 "Load long word from memory (register/register indirect)"
1198       ()
1199       "mov.l @(r0, $rm), $rn"
1200       (+ (f-op4 0) rn rm (f-sub4 14))
1201       (set rn (mem SI (add r0 rm))))
1202
1203(dshci movl9 "Load long word from memory (GBR-relative w/ displacement)"
1204       ()
1205       "mov.l @($imm8x4, gbr), r0"
1206       (+ (f-op8 #xc6) imm8x4)
1207       (set r0 (mem SI (add gbr imm8x4))))
1208
1209(dshci movl10 "Load long word from memory (PC-relative w/ displacement)"
1210       (ILLSLOT)
1211       "mov.l @($imm8x4, pc), $rn"
1212       (+ (f-op4 13) rn imm8x4)
1213       (set rn (mem SI (add imm8x4 (and (add pc 4) (inv 3))))))
1214
1215(dshci movl11 "Load long word from memory (register indirect w/ displacement)"
1216       ()
1217       "mov.l @($imm4x4, $rm), $rn"
1218       (+ (f-op4 5) rn rm imm4x4)
1219       (set rn (mem SI (add rm imm4x4))))
1220
1221(dshci movw1 "Store word to memory (register indirect w/ zero displacement)"
1222       ()
1223       "mov.w $rm, @$rn"
1224       (+ (f-op4 2) rn rm (f-sub4 1))
1225       (set (mem HI rn) (subword HI rm 1)))
1226
1227(dshci movw2 "Store word to memory (register indirect w/ pre-decrement)"
1228       ()
1229       "mov.w $rm, @-$rn"
1230       (+ (f-op4 2) rn rm (f-sub4 5))
1231       (sequence ((DI addr))
1232		 (set addr (sub rn 2))
1233		 (set (mem HI addr) (subword HI rm 1))
1234		 (set rn addr)))
1235
1236(dshci movw3 "Store word to memory (register/register indirect)"
1237       ()
1238       "mov.w $rm, @(r0, $rn)"
1239       (+ (f-op4 0) rn rm (f-sub4 5))
1240       (set (mem HI (add r0 rn)) (subword HI rm 1)))
1241
1242(dshci movw4 "Store word to memory (GBR-relative w/ displacement)"
1243       ()
1244       "mov.w r0, @($imm8x2, gbr)"
1245       (+ (f-op8 #xc1) imm8x2)
1246       (set (mem HI (add gbr imm8x2)) (subword HI r0 1)))
1247
1248(dshci movw5 "Store word to memory (register indirect w/ displacement)"
1249       ()
1250       "mov.w r0, @($imm4x2, $rn)"
1251       (+ (f-op8 #x81) rn imm4x2)
1252       (set (mem HI (add rn imm4x2)) (subword HI r0 1)))
1253
1254(dshci movw6 "Load word from memory (register indirect w/ zero displacement)"
1255       ()
1256       "mov.w @$rm, $rn"
1257       (+ (f-op4 6) rn rm (f-sub4 1))
1258       (set rn (ext SI (mem HI rm))))
1259
1260(dshci movw7 "Load word from memory (register indirect w/ post-increment)"
1261       ()
1262       "mov.w @${rm}+, $rn"
1263       (+ (f-op4 6) rn rm (f-sub4 5))
1264       (sequence ((HI data))
1265		 (set data (mem HI rm))
1266		 (if (eq (index-of rm) (index-of rn))
1267		     (set rm (ext SI data))
1268		     (set rm (add rm 2)))
1269		 (set rn (ext SI data))))
1270
1271(dshci movw8 "Load word from memory (register/register indirect)"
1272       ()
1273       "mov.w @(r0, $rm), $rn"
1274       (+ (f-op4 0) rn rm (f-sub4 13))
1275       (set rn (ext SI (mem HI (add r0 rm)))))
1276
1277(dshci movw9 "Load word from memory (GBR-relative w/ displacement)"
1278       ()
1279       "mov.w @($imm8x2, gbr), r0"
1280       (+ (f-op8 #xc5) imm8x2)
1281       (set r0 (ext SI (mem HI (add gbr imm8x2)))))
1282
1283(dshci movw10 "Load word from memory (PC-relative w/ displacement)"
1284       (ILLSLOT)
1285       "mov.w @($imm8x2, pc), $rn"
1286       (+ (f-op4 9) rn imm8x2)
1287       (set rn (ext SI (mem HI (add (add pc 4) imm8x2)))))
1288
1289(dshci movw11 "Load word from memory (register indirect w/ displacement)"
1290       ()
1291       "mov.w @($imm4x2, $rm), r0"
1292       (+ (f-op8 #x85) rm imm4x2)
1293       (set r0 (ext SI (mem HI (add rm imm4x2)))))
1294
1295(dshci mova "Move effective address"
1296       (ILLSLOT)
1297       "mova @($imm8x4, pc), r0"
1298       (+ (f-op8 #xc7) imm8x4)
1299       (set r0 (add (and (add pc 4) (inv 3)) imm8x4)))
1300
1301(dshci movcal "Move with cache block allocation"
1302       ()
1303       "movca.l r0, @$rn"
1304       (+ (f-op4 0) rn (f-sub8 #xc3))
1305       (set (mem SI rn) r0))
1306
1307(dshci movt "Move t-bit"
1308       ()
1309       "movt $rn"
1310       (+ (f-op4 0) rn (f-sub8 41))
1311       (set rn (zext SI tbit)))
1312
1313(dshci mull "Multiply"
1314       ()
1315       "mul.l $rm, $rn"
1316       (+ (f-op4 0) rn rm (f-sub4 7))
1317       (set macl (mul rm rn)))
1318
1319(dshci mulsw "Multiply words (signed)"
1320       ()
1321       "muls.w $rm, $rn"
1322       (+ (f-op4 2) rn rm (f-sub4 15))
1323       (set macl (mul (ext SI (subword HI rm 1)) (ext SI (subword HI rn 1)))))
1324
1325(dshci muluw "Multiply words (unsigned)"
1326       ()
1327       "mulu.w $rm, $rn"
1328       (+ (f-op4 2) rn rm (f-sub4 14))
1329       (set macl (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1)))))
1330
1331(dshci neg "Negate"
1332       ()
1333       "neg $rm, $rn"
1334       (+ (f-op4 6) rn rm (f-sub4 11))
1335       (set rn (neg rm)))
1336
1337(dshci negc "Negate with carry"
1338       ()
1339       "negc $rm, $rn"
1340       (+ (f-op4 6) rn rm (f-sub4 10))
1341       (sequence ((BI flag))
1342		 (set flag (sub-cflag 0 rm tbit))
1343		 (set rn (subc 0 rm tbit))
1344		 (set tbit flag)))
1345
1346(dshci nop "No operation"
1347       ()
1348       "nop"
1349       (+ (f-op16 9))
1350       (nop))
1351
1352(dshci not "Bitwise NOT"
1353       ()
1354       "not $rm64, $rn64"
1355       (+ (f-op4 6) rn64 rm64 (f-sub4 7))
1356       (set rn64 (inv rm64)))
1357
1358(dshci ocbi "Invalidate operand cache block"
1359       ()
1360       "ocbi @$rn"
1361       (+ (f-op4 0) rn (f-sub8 147))
1362       (unimp "ocbi"))
1363
1364(dshci ocbp "Purge operand cache block"
1365       ()
1366       "ocbp @$rn"
1367       (+ (f-op4 0) rn (f-sub8 163))
1368       (unimp "ocbp"))
1369
1370(dshci ocbwb "Write back operand cache block"
1371       ()
1372       "ocbwb @$rn"
1373       (+ (f-op4 0) rn (f-sub8 179))
1374       (unimp "ocbwb"))
1375
1376(dshci or "Bitwise OR"
1377       ()
1378       "or $rm64, $rn64"
1379       (+ (f-op4 2) rn64 rm64 (f-sub4 11))
1380       (set rn64 (or rm64 rn64)))
1381
1382(dshci ori "Bitwise OR immediate"
1383       ()
1384       "or #$uimm8, r0"
1385       (+ (f-op8 #xcb) uimm8)
1386       (set r0 (or r0 (zext DI uimm8))))
1387
1388(dshci orb "Bitwise OR immediate"
1389       ()
1390       "or.b #$imm8, @(r0, gbr)"
1391       (+ (f-op8 #xcf) imm8)
1392       (sequence ((DI addr) (UQI data))
1393		 (set addr (add r0 gbr))
1394		 (set data (or (mem UQI addr) imm8))
1395		 (set (mem UQI addr) data)))
1396
1397(dshci pref "Prefetch data"
1398       ()
1399       "pref @$rn"
1400       (+ (f-op4 0) rn (f-sub8 131))
1401       (unimp "pref"))
1402
1403(dshci rotcl "Rotate with carry left"
1404       ()
1405       "rotcl $rn"
1406       (+ (f-op4 4) rn (f-sub8 36))
1407       (sequence ((BI temp))
1408		 (set temp (srl rn 31))
1409		 (set rn (or (sll rn 1) tbit))
1410		 (set tbit (if BI temp 1 0))))
1411
1412(dshci rotcr "Rotate with carry right"
1413       ()
1414       "rotcr $rn"
1415       (+ (f-op4 4) rn (f-sub8 37))
1416       (sequence ((BI lsbit) (SI temp))
1417		 (set lsbit (if BI (eq (and rn 1) 0) 0 1))
1418		 (set temp tbit)
1419		 (set rn (or (srl rn 1) (sll temp 31)))
1420		 (set tbit (if BI lsbit 1 0))))
1421
1422(dshci rotl "Rotate left"
1423       ()
1424       "rotl $rn"
1425       (+ (f-op4 4) rn (f-sub8 4))
1426       (sequence ((BI temp))
1427		 (set temp (srl rn 31))
1428		 (set rn (or (sll rn 1) temp))
1429		 (set tbit (if BI temp 1 0))))
1430
1431(dshci rotr "Rotate right"
1432       ()
1433       "rotr $rn"
1434       (+ (f-op4 4) rn (f-sub8 5))
1435       (sequence ((BI lsbit) (SI temp))
1436		 (set lsbit (if BI (eq (and rn 1) 0) 0 1))
1437		 (set temp lsbit)
1438		 (set rn (or (srl rn 1) (sll temp 31)))
1439		 (set tbit (if BI lsbit 1 0))))
1440
1441(dshci rts "Return from subroutine"
1442       ()
1443       "rts"
1444       (+ (f-op16 11))
1445       (delay 1 (set pc pr)))
1446
1447(dshci sets "Set S-bit"
1448       ()
1449       "sets"
1450       (+ (f-op16 88))
1451       (set sbit 1))
1452
1453(dshci sett "Set T-bit"
1454       ()
1455       "sett"
1456       (+ (f-op16 24))
1457       (set tbit 1))
1458
1459(dshci shad "Shift arithmetic dynamic"
1460       ()
1461       "shad $rm, $rn"
1462       (+ (f-op4 4) rn rm (f-sub4 12))
1463       (sequence ((QI shamt))
1464		 (set shamt (and QI rm 31))
1465		 (if (ge rm 0)
1466		     (set rn (sll rn shamt))
1467		     (if (ne shamt 0)
1468			 (set rn (sra rn (sub 32 shamt)))
1469			 (if (lt rn 0)
1470			     (set rn (neg 1))
1471			     (set rn 0))))))
1472
1473(dshci shal "Shift left arithmetic one bit"
1474       ()
1475       "shal $rn"
1476       (+ (f-op4 4) rn (f-sub8 32))
1477       (sequence ((BI t))
1478		 (set t (srl rn 31))
1479		 (set rn (sll rn 1))
1480		 (set tbit (if BI t 1 0))))
1481
1482(dshci shar "Shift right arithmetic one bit"
1483       ()
1484       "shar $rn"
1485       (+ (f-op4 4) rn (f-sub8 33))
1486       (sequence ((BI t))
1487		 (set t (and rn 1))
1488		 (set rn (sra rn 1))
1489		 (set tbit (if BI t 1 0))))
1490
1491(dshci shld "Shift logical dynamic"
1492       ()
1493       "shld $rm, $rn"
1494       (+ (f-op4 4) rn rm (f-sub4 13))
1495       (sequence ((QI shamt))
1496		 (set shamt (and QI rm 31))
1497		 (if (ge rm 0)
1498		     (set rn (sll rn shamt))
1499		     (if (ne shamt 0)
1500			 (set rn (srl rn (sub 32 shamt)))
1501			 (set rn 0)))))
1502
1503(dshci shll "Shift left logical one bit"
1504       ()
1505       "shll $rn"
1506       (+ (f-op4 4) rn (f-sub8 0))
1507       (sequence ((BI t))
1508		 (set t (srl rn 31))
1509		 (set rn (sll rn 1))
1510		 (set tbit (if BI t 1 0))))
1511
1512(dshci shll2 "Shift left logical two bits"
1513       ()
1514       "shll2 $rn"
1515       (+ (f-op4 4) rn (f-sub8 8))
1516       (set rn (sll rn 2)))
1517
1518(dshci shll8 "Shift left logical eight bits"
1519       ()
1520       "shll8 $rn"
1521       (+ (f-op4 4) rn (f-sub8 24))
1522       (set rn (sll rn 8)))
1523
1524(dshci shll16 "Shift left logical sixteen bits"
1525       ()
1526       "shll16 $rn"
1527       (+ (f-op4 4) rn (f-sub8 40))
1528       (set rn (sll rn 16)))
1529
1530(dshci shlr "Shift right logical one bit"
1531       ()
1532       "shlr $rn"
1533       (+ (f-op4 4) rn (f-sub8 1))
1534       (sequence ((BI t))
1535		 (set t (and rn 1))
1536		 (set rn (srl rn 1))
1537		 (set tbit (if BI t 1 0))))
1538
1539(dshci shlr2 "Shift right logical two bits"
1540       ()
1541       "shlr2 $rn"
1542       (+ (f-op4 4) rn (f-sub8 9))
1543       (set rn (srl rn 2)))
1544
1545(dshci shlr8 "Shift right logical eight bits"
1546       ()
1547       "shlr8 $rn"
1548       (+ (f-op4 4) rn (f-sub8 25))
1549       (set rn (srl rn 8)))
1550
1551(dshci shlr16 "Shift right logical sixteen bits"
1552       ()
1553       "shlr16 $rn"
1554       (+ (f-op4 4) rn (f-sub8 41))
1555       (set rn (srl rn 16)))
1556
1557(dshci stc-gbr "Store control register (GBR)"
1558       ()
1559       "stc gbr, $rn"
1560       (+ (f-op4 0) rn (f-sub8 18))
1561       (set rn gbr))
1562
1563(dshci stcl-gbr "Store control register (GBR)"
1564       ()
1565       "stc.l gbr, @-$rn"
1566       (+ (f-op4 4) rn (f-sub8 19))
1567       (sequence ((DI addr))
1568		 (set addr (sub rn 4))
1569		 (set (mem SI addr) gbr)
1570		 (set rn addr)))
1571
1572(dshci sts-fpscr "Store status register (FPSCR)"
1573       ()
1574       "sts fpscr, $rn"
1575       (+ (f-op4 0) rn (f-sub8 106))
1576       (set rn fpscr))
1577
1578(dshci stsl-fpscr "Store status register (FPSCR)"
1579       ()
1580       "sts.l fpscr, @-$rn"
1581       (+ (f-op4 4) rn (f-sub8 98))
1582       (sequence ((DI addr))
1583		 (set addr (sub rn 4))
1584		 (set (mem SI addr) fpscr)
1585		 (set rn addr)))
1586
1587(dshci sts-fpul "Store status register (FPUL)"
1588       ()
1589       "sts fpul, $rn"
1590       (+ (f-op4 0) rn (f-sub8 90))
1591       (set rn (subword SI fpul 0)))
1592
1593(dshci stsl-fpul "Store status register (FPUL)"
1594       ()
1595       "sts.l fpul, @-$rn"
1596       (+ (f-op4 4) rn (f-sub8 82))
1597       (sequence ((DI addr))
1598		 (set addr (sub rn 4))
1599		 (set (mem SF addr) fpul)
1600		 (set rn addr)))
1601
1602(dshci sts-mach "Store status register (MACH)"
1603       ()
1604       "sts mach, $rn"
1605       (+ (f-op4 0) rn (f-sub8 10))
1606       (set rn mach))
1607
1608(dshci stsl-mach "Store status register (MACH)"
1609       ()
1610       "sts.l mach, @-$rn"
1611       (+ (f-op4 4) rn (f-sub8 2))
1612       (sequence ((DI addr))
1613		 (set addr (sub rn 4))
1614		 (set (mem SI addr) mach)
1615		 (set rn addr)))
1616
1617(dshci sts-macl "Store status register (MACL)"
1618       ()
1619       "sts macl, $rn"
1620       (+ (f-op4 0) rn (f-sub8 26))
1621       (set rn macl))
1622
1623(dshci stsl-macl "Store status register (MACL)"
1624       ()
1625       "sts.l macl, @-$rn"
1626       (+ (f-op4 4) rn (f-sub8 18))
1627       (sequence ((DI addr))
1628		 (set addr (sub rn 4))
1629		 (set (mem SI addr) macl)
1630		 (set rn addr)))
1631
1632(dshci sts-pr "Store status register (PR)"
1633       ()
1634       "sts pr, $rn"
1635       (+ (f-op4 0) rn (f-sub8 42))
1636       (set rn pr))
1637
1638(dshci stsl-pr "Store status register (PR)"
1639       ()
1640       "sts.l pr, @-$rn"
1641       (+ (f-op4 4) rn (f-sub8 34))
1642       (sequence ((DI addr))
1643		 (set addr (sub rn 4))
1644		 (set (mem SI addr) pr)
1645		 (set rn addr)))
1646
1647(dshci sub "Subtract"
1648       ()
1649       "sub $rm, $rn"
1650       (+ (f-op4 3) rn rm (f-sub4 8))
1651       (set rn (sub rn rm)))
1652
1653(dshci subc "Subtract and detect carry"
1654       ()
1655       "subc $rm, $rn"
1656       (+ (f-op4 3) rn rm (f-sub4 10))
1657       (sequence ((BI flag))
1658		 (set flag (sub-cflag rn rm tbit))
1659		 (set rn (subc rn rm tbit))
1660		 (set tbit flag)))
1661
1662(dshci subv "Subtract and detect overflow"
1663       ()
1664       "subv $rm, $rn"
1665       (+ (f-op4 3) rn rm (f-sub4 11))
1666       (sequence ((BI t))
1667		 (set t (sub-oflag rn rm 0))
1668		 (set rn (sub rn rm))
1669		 (set tbit (if BI t 1 0))))
1670
1671(dshci swapb "Swap bytes"
1672       ()
1673       "swap.b $rm, $rn"
1674       (+ (f-op4 6) rn rm (f-sub4 8))
1675       (sequence ((UHI top-half) (UQI byte1) (UQI byte0))
1676		 (set top-half (subword HI rm 0))
1677		 (set byte1 (subword QI rm 2))
1678		 (set byte0 (subword QI rm 3))
1679		 (set rn (or SI (sll SI top-half 16) (or SI (sll SI byte0 8) byte1)))))
1680
1681(dshci swapw "Swap words"
1682       ()
1683       "swap.w $rm, $rn"
1684       (+ (f-op4 6) rn rm (f-sub4 9))
1685       (set rn (or (srl rm 16) (sll rm 16))))
1686
1687(dshci tasb "Test and set byte"
1688       ()
1689       "tas.b @$rn"
1690       (+ (f-op4 4) rn (f-sub8 27))
1691       (sequence ((UQI byte))
1692		 (set byte (mem UQI rn))
1693		 (set tbit (if BI (eq byte 0) 1 0))
1694		 (set byte (or byte 128))
1695		 (set (mem UQI rn) byte)))
1696
1697(dshci trapa "Trap"
1698       (ILLSLOT)
1699       "trapa #$uimm8"
1700       (+ (f-op8 #xc3) uimm8)
1701       (c-call "sh64_compact_trapa" uimm8 pc))
1702
1703(dshci tst "Test and set t-bit"
1704       ()
1705       "tst $rm, $rn"
1706       (+ (f-op4 2) rn rm (f-sub4 8))
1707       (set tbit (if BI (eq (and rm rn) 0) 1 0)))
1708
1709(dshci tsti "Test and set t-bit immediate"
1710       ()
1711       "tst #$uimm8, r0"
1712       (+ (f-op8 #xc8) uimm8)
1713       (set tbit (if BI (eq (and r0 (zext SI uimm8)) 0) 1 0)))
1714
1715(dshci tstb "Test and set t-bit immedate with memory byte"
1716       ()
1717       "tst.b #$imm8, @(r0, gbr)"
1718       (+ (f-op8 #xcc) imm8)
1719       (sequence ((DI addr))
1720		 (set addr (add r0 gbr))
1721		 (set tbit (if BI (eq (and (mem UQI addr) imm8) 0) 1 0))))
1722
1723(dshci xor "Exclusive OR"
1724       ()
1725       "xor $rm64, $rn64"
1726       (+ (f-op4 2) rn64 rm64 (f-sub4 10))
1727       (set rn64 (xor rn64 rm64)))
1728
1729(dshci xori "Exclusive OR immediate"
1730       ()
1731       "xor #$uimm8, r0"
1732       (+ (f-op8 #xca) uimm8)
1733       (set (reg h-gr 0) (xor (reg h-gr 0) (zext DI uimm8))))
1734
1735(dshci xorb "Exclusive OR immediate with memory byte"
1736       ()
1737       "xor.b #$imm8, @(r0, gbr)"
1738       (+ (f-op8 #xce) imm8)
1739       (sequence ((DI addr) (UQI data))
1740		 (set addr (add r0 gbr))
1741		 (set data (xor (mem UQI addr) imm8))
1742		 (set (mem UQI addr) data)))
1743
1744(dshci xtrct "Extract"
1745       ()
1746       "xtrct $rm, $rn"
1747       (+ (f-op4 2) rn rm (f-sub4 13))
1748       (set rn (or (sll rm 16) (srl rn 16))))
1749