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Searched refs:Rd (Results 1 – 25 of 26) sorted by relevance

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/toolchain/binutils/binutils-2.25/cpu/
Dxstormy16.cpu199 (dnf f-Rd "general register destination" () 12 4)
200 (dnop Rd "general register destination" () h-gr f-Rd)
434 ; Update the PSW for destination register Rd, set Rd to value.
435 (define-pmacro (set-psw Rd index value ws)
443 ; Update the PSW for destination register Rd.
460 (define-pmacro (set-psw-carry Rd index value carry ws)
472 (define-pmacro (set-psw-add Rd index a b c)
486 ; Set the PSW for a subtraction of a-b into Rd, but don't actually
488 (define-pmacro (set-psw-cmp Rd index a b)
502 (define-pmacro (set-psw-sub Rd index a b c)
[all …]
Dcris.cpu154 ((Rd INT -1))
262 ((Rs INT -1) (Rd INT -1))
265 ((Rs INT -1) (Rd INT -1))
268 ((Rs INT -1) (Rd INT -1))
292 ((Rd INT -1) (Rs INT -1))
293 ((Rd INT -1))
296 ; Special case of u-exec for movem: don't treat Rd as an incoming
300 ((Rd INT -1))
317 (define-pmacro (cris-timing-Rd-sfield)
318 (crisv32-timing-destreg ((out Rd Rd-sfield)))
[all …]
Diq2000.cpu146 (dnf f-rd "register field Rd" () 15 5)
156 (comment "register Rd implied from Rs")
171 (comment "register Rd implied from Rt")
363 (dnop rd "register Rd" () h-gr f-rd)
364 (dnop rd-rs "register Rd from Rs" () h-gr f-rd-rs)
365 (dnop rd-rt "register Rd from Rt" () h-gr f-rd-rt)
/toolchain/binutils/binutils-2.25/opcodes/
Daarch64-tbl.h1236 {"adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
1237 {"adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
1238 …{"sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS |…
1239 {"ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, CORE, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF},
1240 …{"sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS …
1241 {"ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, CORE, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF},
1244 …{"adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_AL…
1247 …{"subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_AL…
1252 …{"adds", 0x31000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS…
1255 …{"subs", 0x71000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS…
[all …]
Di386-dis-evex.h3601 { "vpbroadcastb", { XM, Rd } },
3605 { "vpbroadcastw", { XM, Rd } },
Di386-dis.c263 #define Rd { OP_R, d_mode } macro
11663 { "movL", { Rd, Td } },
11668 { "movL", { Td, Rd } },
DChangeLog-20071702 (Rd): Updated.
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/
Dmul-overlap.l2 [^:]*:5: Rd and Rm should be different in mul
3 [^:]*:6: Rd and Rm should be different in mla
Darchv6t2-bad.s49 @ ldsttv4 Rd == Rn (warning)
/toolchain/binutils/binutils-2.25/gas/config/
Dtc-arm.c8350 unsigned Rd; in do_co_reg() local
8353 Rd = inst.operands[2].reg; in do_co_reg()
8359 reject_bad_reg (Rd); in do_co_reg()
8362 constraint (Rd == REG_SP, BAD_SP); in do_co_reg()
8368 constraint (Rd == REG_PC, BAD_PC); in do_co_reg()
8391 inst.instruction |= Rd << 12; in do_co_reg()
8413 unsigned Rd, Rn; in do_co_reg2c() local
8415 Rd = inst.operands[2].reg; in do_co_reg2c()
8420 reject_bad_reg (Rd); in do_co_reg2c()
8425 constraint (Rd == REG_PC, BAD_PC); in do_co_reg2c()
[all …]
/toolchain/binutils/binutils-2.25/gas/doc/
Dc-avr.texi302 z @r{Z pointer register (for [e]lpm Rd,Z[+])}
Dc-h8300.texi200 Rd @r{destination register}
/toolchain/binutils/binutils-2.25/gas/
DChangeLog-20072059 Rd and Rm operands when assembling for v6 or above.
2551 * config/tc-arm.c (do_t_add_sub): Use Rd and Rs.
DChangeLog-00017040 * config/tc-arm.c (do_t_adr): Flag "adr Rd,label"
7041 instruction operand bad if Rd > 7 when generating
DChangeLog-20053245 is_mls parameter; do not diagnose Rm==Rd when is_mls.
/toolchain/binutils/binutils-2.25/include/opcode/
DChangeLog461 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
/toolchain/binutils/binutils-2.25/gas/po/
Des.po2558 msgid "Rd and Rm should be different in mla"
2559 msgstr "Rd y Rm deben ser diferentes en mla"
2586 msgid "Rd and Rm should be different in mul"
2587 msgstr "Rd y Rm deben ser diferentes en mul"
18517 #~ msgid "Rd equal to Rm or Rn yields unpredictable results"
18518 #~ msgstr "Rd igual a Rm o Rn produce resultados impredecibles"
18574 #~ msgid "Rs and Rd must be different in MUL"
18575 #~ msgstr "Rs y Rd deben ser diferentes en MUL"
18583 #~ msgid "syntax: ldrs[b] Rd, [Rb, Ro]"
18584 #~ msgstr "sintaxis: ldrs[b] Rd, [Rb, Ro]"
Dtr.po2234 msgid "Rd and Rm should be different in mla"
2259 msgid "Rd and Rm should be different in mul"
15064 #~ msgid "Rs and Rd must be different in MUL"
15065 #~ msgstr "MUL içinde Rs ve Rd farklı olmalı"
15075 #~ msgid "syntax: ldrs[b] Rd, [Rb, Ro]"
15076 #~ msgstr "Sözdizim: ldrs[b] Rd, [Rb, Ro]"
Duk.po3355 msgid "Rd and Rm should be different in mla"
3356 msgstr "Rd і Rm мають бути різними у mla"
3379 msgid "Rd and Rm should be different in mul"
3380 msgstr "Rd і Rm мають бути різними у mul"
Did.po2391 msgid "Rd and Rm should be different in mla"
2392 msgstr "Rd dan Rm seharusnya berbeda dalam mla"
2411 msgid "Rd and Rm should be different in mul"
2412 msgstr "Rd dan Rm seharusnya berbeda dalam mul"
Dfi.po2570 msgid "Rd and Rm should be different in mla"
2571 msgstr "”Rd” ja ”Rm” pitäisi olla eri ”mla”:ssa"
2598 msgid "Rd and Rm should be different in mul"
2599 msgstr "”Rd” ja ”Rm” pitäisi olla erilainen ”mul”:ssa"
Dfr.po2565 msgid "Rd and Rm should be different in mla"
2566 msgstr "Rd et Rm devraient être différents dans mla"
2593 msgid "Rd and Rm should be different in mul"
2594 msgstr "Rd et Rm devraient être différents dans mul"
Dru.po2381 msgid "Rd and Rm should be different in mla"
2401 msgid "Rd and Rm should be different in mul"
Drw.po2094 msgid "Rd and Rm should be different in mla"
2114 msgid "Rd and Rm should be different in mul"
Dja.po2457 msgid "Rd and Rm should be different in mla"
2485 msgid "Rd and Rm should be different in mul"

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