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Searched refs:Rs (Results 1 – 11 of 11) sorted by relevance

/toolchain/binutils/binutils-2.25/cpu/
Dxstormy16.cpu208 (dnf f-Rs "general register source" () 8 4)
209 (dnop Rs "general register source" () h-gr f-Rs)
616 ("mov$ws2 $Rdm,($Rs)")
617 (+ OP1_7 OP2A_0 ws2 Rs OP4M_0 Rdm)
619 (set-psw Rdm (index-of Rdm) (alignfix-mem Rs) ws2)
620 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI Rs)) ws2))
627 ("mov$ws2 $Rdm,($Rs++)")
628 (+ OP1_6 OP2A_0 ws2 Rs OP4M_0 Rdm)
631 (set-psw Rdm (index-of Rdm) (alignfix-mem Rs) ws2)
632 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI Rs)) ws2))
[all …]
Dcris.cpu254 ((Rs INT -1))
262 ((Rs INT -1) (Rd INT -1))
265 ((Rs INT -1) (Rd INT -1))
268 ((Rs INT -1) (Rd INT -1))
274 ((Rs INT -1))
292 ((Rd INT -1) (Rs INT -1))
299 ((Rs INT -1))
306 ((Rs INT -1))
1537 ; Rs := source operand, register addressing mode
1538 (dnop Rs "Source general register" () h-gr f-source)
[all …]
Diq2000.cpu144 (dnf f-rs "register field Rs" () 25 5)
156 (comment "register Rd implied from Rs")
186 (comment "register Rt implied from Rs")
361 (dnop rs "register Rs" () h-gr f-rs)
364 (dnop rd-rs "register Rd from Rs" () h-gr f-rd-rs)
366 (dnop rt-rs "register Rt from Rs" () h-gr f-rt-rs)
Dfr30.cpu152 (dnf f-Rs1 "register Rs" () 8 4)
153 (dnf f-Rs2 "register Rs" () 12 4)
1193 "st Rs,@-R15 reg/mem"
1239 "mov Ri,Rs reg/reg"
/toolchain/binutils/binutils-2.25/opcodes/
Daarch64-tbl.h1998 {"stxrb", 0x8007c00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
1999 …{"stlxrb", 0x800fc00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2004 …{"stxrh", 0x48007c00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2005 …{"stlxrh", 0x4800fc00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0…
2010 …{"stxr", 0x88007c00, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_G…
2011 …{"stlxr", 0x8800fc00, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_…
2012 …{"stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, CORE, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC…
2013 …{"stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, CORE, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EX…
2064 {"casb", 0x8a07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2065 …{"cash", 0x48a07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
[all …]
/toolchain/binutils/binutils-2.25/gas/config/
Dtc-arm.c10175 int Rd, Rs, Rn; in do_t_add_sub() local
10178 Rs = (inst.operands[1].present in do_t_add_sub()
10201 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); in do_t_add_sub()
10210 if (Rd == REG_SP && Rs == REG_SP && !flags) in do_t_add_sub()
10212 else if (Rd <= 7 && Rs == REG_SP && add && !flags) in do_t_add_sub()
10214 else if (Rd <= 7 && Rs == REG_PC && add && !flags) in do_t_add_sub()
10216 else if (Rd <= 7 && Rs <= 7 && narrow) in do_t_add_sub()
10226 inst.instruction |= (Rd << 4) | Rs; in do_t_add_sub()
10240 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, in do_t_add_sub()
10252 else if (Rs == REG_PC) in do_t_add_sub()
[all …]
/toolchain/binutils/binutils-2.25/gas/doc/
Dc-h8300.texi199 Rs @r{source register}
/toolchain/binutils/binutils-2.25/include/opcode/
DChangeLog462 and mov.b/w/l Rs,@(d:32,ERd).
/toolchain/binutils/binutils-2.25/gas/
DChangeLog-20072551 * config/tc-arm.c (do_t_add_sub): Use Rd and Rs.
/toolchain/binutils/binutils-2.25/gas/po/
Dtr.po15064 #~ msgid "Rs and Rd must be different in MUL"
15065 #~ msgstr "MUL içinde Rs ve Rd farklı olmalı"
Des.po18574 #~ msgid "Rs and Rd must be different in MUL"
18575 #~ msgstr "Rs y Rd deben ser diferentes en MUL"