1; Fujitsu FR30 CPU description. -*- Scheme -*- 2; Copyright 2011 Free Software Foundation, Inc. 3; 4; Contributed by Red Hat Inc; 5; 6; This file is part of the GNU Binutils. 7; 8; This program is free software; you can redistribute it and/or modify 9; it under the terms of the GNU General Public License as published by 10; the Free Software Foundation; either version 3 of the License, or 11; (at your option) any later version. 12; 13; This program is distributed in the hope that it will be useful, 14; but WITHOUT ANY WARRANTY; without even the implied warranty of 15; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16; GNU General Public License for more details. 17; 18; You should have received a copy of the GNU General Public License 19; along with this program; if not, write to the Free Software 20; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 21; MA 02110-1301, USA. 22 23(define-rtl-version 0 8) 24 25(include "simplify.inc") 26 27; define-arch must appear first 28 29(define-arch 30 (name fr30) ; name of cpu family 31 (comment "Fujitsu FR30") 32 (default-alignment forced) 33 (insn-lsb0? #f) 34 (machs fr30) 35 (isas fr30) 36) 37 38(define-isa 39 (name fr30) 40 (base-insn-bitsize 16) 41 (decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by. 42 (liw-insns 1) ; The fr30 fetches 1 insn at a time. 43 (parallel-insns 1) ; The fr30 executes 1 insn at a time. 44) 45 46(define-cpu 47 ; cpu names must be distinct from the architecture name and machine names. 48 ; The "b" suffix stands for "base" and is the convention. 49 ; The "f" suffix stands for "family" and is the convention. 50 (name fr30bf) 51 (comment "Fujitsu FR30 base family") 52 (endian big) 53 (word-bitsize 32) 54) 55 56(define-mach 57 (name fr30) 58 (comment "Generic FR30 cpu") 59 (cpu fr30bf) 60) 61 62; Model descriptions. 63; 64(define-model 65 (name fr30-1) (comment "fr30-1") (attrs) 66 (mach fr30) 67 68 (pipeline all "" () ((fetch) (decode) (execute) (writeback))) 69 70 ; `state' is a list of variables for recording model state 71 (state 72 ; bit mask of h-gr registers loaded from memory by previous insn 73 (load-regs UINT) 74 ; bit mask of h-gr registers loaded from memory by current insn 75 (load-regs-pending UINT) 76 ) 77 78 (unit u-exec "Execution Unit" () 79 1 1 ; issue done 80 () ; state 81 ((Ri INT -1) (Rj INT -1)) ; inputs 82 ((Ri INT -1)) ; outputs 83 () ; profile action (default) 84 ) 85 (unit u-cti "Branch Unit" () 86 1 1 ; issue done 87 () ; state 88 ((Ri INT -1)) ; inputs 89 ((pc)) ; outputs 90 () ; profile action (default) 91 ) 92 (unit u-load "Memory Load Unit" () 93 1 1 ; issue done 94 () ; state 95 ((Rj INT -1) 96 ;(ld-mem AI) 97 ) ; inputs 98 ((Ri INT -1)) ; outputs 99 () ; profile action (default) 100 ) 101 (unit u-store "Memory Store Unit" () 102 1 1 ; issue done 103 () ; state 104 ((Ri INT -1) (Rj INT -1)) ; inputs 105 () ; ((st-mem AI)) ; outputs 106 () ; profile action (default) 107 ) 108 (unit u-ldm "LDM Memory Load Unit" () 109 1 1 ; issue done 110 () ; state 111 ((reglist INT)) ; inputs 112 () ; outputs 113 () ; profile action (default) 114 ) 115 (unit u-stm "STM Memory Store Unit" () 116 1 1 ; issue done 117 () ; state 118 ((reglist INT)) ; inputs 119 () ; outputs 120 () ; profile action (default) 121 ) 122) 123 124; The instruction fetch/execute cycle. 125; 126; This is how to fetch and decode an instruction. 127; Leave it out for now 128 129; (define-extract (const SI 0)) 130 131; This is how to execute a decoded instruction. 132; Leave it out for now 133 134; (define-execute (const SI 0)) 135 136; Instruction fields. 137; 138; Attributes: 139; PCREL-ADDR: pc relative value (for reloc and disassembly purposes) 140; ABS-ADDR: absolute address (for reloc and disassembly purposes?) 141; RESERVED: bits are not used to decode insn, must be all 0 142 143(dnf f-op1 "1st 4 bits of opcode" () 0 4) 144(dnf f-op2 "2nd 4 bits of opcode" () 4 4) 145(dnf f-op3 "3rd 4 bits of opcode" () 8 4) 146(dnf f-op4 "4th 4 bits of opcode" () 12 4) 147(dnf f-op5 "5th bit of opcode" () 4 1) 148(dnf f-cc "condition code" () 4 4) 149(dnf f-ccc "coprocessor calc code" () 16 8) 150(dnf f-Rj "register Rj" () 8 4) 151(dnf f-Ri "register Ri" () 12 4) 152(dnf f-Rs1 "register Rs" () 8 4) 153(dnf f-Rs2 "register Rs" () 12 4) 154(dnf f-Rjc "register Rj" () 24 4) 155(dnf f-Ric "register Ri" () 28 4) 156(dnf f-CRj "coprocessor register" () 24 4) 157(dnf f-CRi "coprocessor register" () 28 4) 158(dnf f-u4 "4 bit 0 extended" () 8 4) 159(dnf f-u4c "4 bit 0 extended" () 12 4) 160(df f-i4 "4 bit sign extended" () 8 4 INT #f #f) 161(df f-m4 "4 bit minus extended" () 8 4 UINT 162 ((value pc) (and WI value (const #xf))) 163 ; ??? On a 64 bit host this doesn't get completely sign extended 164 ; if the value is recorded in a long, as it is during extraction. 165 ; Various fixes exist, pick one. 166 ((value pc) (or WI value (sll WI (const -1) (const 4)))) 167) 168(dnf f-u8 "8 bit unsigned" () 8 8) 169(dnf f-i8 "8 bit unsigned" () 4 8) 170 171(dnf f-i20-4 "upper 4 bits of i20" () 8 4) 172(dnf f-i20-16 "lower 16 bits of i20" () 16 16) 173(dnmf f-i20 "20 bit unsigned" () UINT 174 (f-i20-4 f-i20-16) 175 (sequence () ; insert 176 (set (ifield f-i20-4) (srl (ifield f-i20) (const 16))) 177 (set (ifield f-i20-16) (and (ifield f-i20) (const #xffff))) 178 ) 179 (sequence () ; extract 180 (set (ifield f-i20) (or (sll (ifield f-i20-4) (const 16)) 181 (ifield f-i20-16))) 182 ) 183) 184 185(dnf f-i32 "32 bit immediate" (SIGN-OPT) 16 32) 186 187(df f-udisp6 "6 bit unsigned offset" () 8 4 UINT 188 ((value pc) (srl UWI value (const 2))) 189 ((value pc) (sll UWI value (const 2))) 190) 191(df f-disp8 "8 bit signed offset" () 4 8 INT #f #f) 192(df f-disp9 "9 bit signed offset" () 4 8 INT 193 ((value pc) (sra WI value (const 1))) 194 ((value pc) (sll WI value (const 1))) 195) 196(df f-disp10 "10 bit signed offset" () 4 8 INT 197 ((value pc) (sra WI value (const 2))) 198 ((value pc) (sll WI value (const 2))) 199) 200(df f-s10 "10 bit signed offset" () 8 8 INT 201 ((value pc) (sra WI value (const 2))) 202 ((value pc) (sll WI value (const 2))) 203) 204(df f-u10 "10 bit unsigned offset" () 8 8 UINT 205 ((value pc) (srl UWI value (const 2))) 206 ((value pc) (sll UWI value (const 2))) 207) 208(df f-rel9 "9 pc relative signed offset" (PCREL-ADDR) 8 8 INT 209 ((value pc) (sra WI (sub WI value (add WI pc (const 2))) (const 1))) 210 ((value pc) (add WI (sll WI value (const 1)) (add WI pc (const 2)))) 211) 212(dnf f-dir8 "8 bit direct address" () 8 8) 213(df f-dir9 "9 bit direct address" () 8 8 UINT 214 ((value pc) (srl UWI value (const 1))) 215 ((value pc) (sll UWI value (const 1))) 216) 217(df f-dir10 "10 bit direct address" () 8 8 UINT 218 ((value pc) (srl UWI value (const 2))) 219 ((value pc) (sll UWI value (const 2))) 220) 221(df f-rel12 "12 bit pc relative signed offset" (PCREL-ADDR) 5 11 INT 222 ((value pc) (sra WI (sub WI value (add WI pc (const 2))) (const 1))) 223 ((value pc) (add WI (sll WI value (const 1)) (add WI pc (const 2)))) 224) 225 226(dnf f-reglist_hi_st "8 bit register mask for stm" () 8 8) 227(dnf f-reglist_low_st "8 bit register mask for stm" () 8 8) 228(dnf f-reglist_hi_ld "8 bit register mask for ldm" () 8 8) 229(dnf f-reglist_low_ld "8 bit register mask for ldm" () 8 8) 230 231; Enums. 232 233; insn-op1: bits 0-3 234; FIXME: should use die macro or some such 235(define-normal-insn-enum insn-op1 "insn op1 enums" () OP1_ f-op1 236 ("0" "1" "2" "3" "4" "5" "6" "7" 237 "8" "9" "A" "B" "C" "D" "E" "F") 238) 239 240; insn-op2: bits 4-7 241; FIXME: should use die macro or some such 242(define-normal-insn-enum insn-op2 "insn op2 enums" () OP2_ f-op2 243 ("0" "1" "2" "3" "4" "5" "6" "7" 244 "8" "9" "A" "B" "C" "D" "E" "F") 245) 246 247; insn-op3: bits 8-11 248; FIXME: should use die macro or some such 249(define-normal-insn-enum insn-op3 "insn op3 enums" () OP3_ f-op3 250 ("0" "1" "2" "3" "4" "5" "6" "7" 251 "8" "9" "A" "B" "C" "D" "E" "F") 252) 253 254; insn-op4: bits 12-15 255; FIXME: should use die macro or some such 256(define-normal-insn-enum insn-op4 "insn op4 enums" () OP4_ f-op4 257 ("0") 258) 259 260; insn-op5: bit 4 (5th bit origin 0) 261; FIXME: should use die macro or some such 262(define-normal-insn-enum insn-op5 "insn op5 enums" () OP5_ f-op5 263 ("0" "1") 264) 265 266; insn-cc: condition codes 267; FIXME: should use die macro or some such 268(define-normal-insn-enum insn-cc "insn cc enums" () CC_ f-cc 269 ("ra" "no" "eq" "ne" "c" "nc" "n" "p" "v" "nv" "lt" "ge" "le" "gt" "ls" "hi") 270) 271 272; Hardware pieces. 273; These entries list the elements of the raw hardware. 274; They're also used to provide tables and other elements of the assembly 275; language. 276 277(dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) 278 279(define-keyword 280 (name gr-names) 281 (enum-prefix H-GR-) 282 (values (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7) 283 (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15) 284 (ac 13) (fp 14) (sp 15)) 285) 286 287(define-hardware 288 (name h-gr) 289 (comment "general registers") 290 (attrs PROFILE CACHE-ADDR) 291 (type register WI (16)) 292 (indices extern-keyword gr-names) 293) 294 295(define-keyword 296 (name cr-names) 297 (enum-prefix H-CR-) 298 (values (cr0 0) (cr1 1) (cr2 2) (cr3 3) 299 (cr4 4) (cr5 5) (cr6 6) (cr7 7) 300 (cr8 8) (cr9 9) (cr10 10) (cr11 11) 301 (cr12 12) (cr13 13) (cr14 14) (cr15 15)) 302) 303 304(define-hardware 305 (name h-cr) 306 (comment "coprocessor registers") 307 (attrs) 308 (type register WI (16)) 309 (indices extern-keyword cr-names) 310) 311 312(define-keyword 313 (name dr-names) 314 (enum-prefix H-DR-) 315 (values (tbr 0) (rp 1) (ssp 2) (usp 3) (mdh 4) (mdl 5)) 316) 317 318(define-hardware 319 (name h-dr) 320 (comment "dedicated registers") 321 (type register WI (6)) 322 (indices extern-keyword dr-names) 323 (get (index) (c-call WI "@cpu@_h_dr_get_handler" index)) 324 (set (index newval) (c-call VOID "@cpu@_h_dr_set_handler" index newval)) 325) 326 327(define-hardware 328 (name h-ps) 329 (comment "processor status") 330 (type register UWI) 331 (indices keyword "" ((ps 0))) 332 (get () (c-call UWI "@cpu@_h_ps_get_handler")) 333 (set (newval) (c-call VOID "@cpu@_h_ps_set_handler" newval)) 334) 335 336(dnh h-r13 "General Register 13 explicitly required" 337 () 338 (register WI) 339 (keyword "" ((r13 0))) 340 () () 341) 342 343(dnh h-r14 "General Register 14 explicitly required" 344 () 345 (register WI) 346 (keyword "" ((r14 0))) 347 () () 348) 349 350(dnh h-r15 "General Register 15 explicitly required" 351 () 352 (register WI) 353 (keyword "" ((r15 0))) 354 () () 355) 356 357; These bits are actually part of the PS register but are accessed more 358; often than the entire register, so define them directly. We can assemble 359; the PS register from its components when necessary. 360 361(dsh h-nbit "negative bit" () (register BI)) 362(dsh h-zbit "zero bit" () (register BI)) 363(dsh h-vbit "overflow bit" () (register BI)) 364(dsh h-cbit "carry bit" () (register BI)) 365(dsh h-ibit "interrupt enable bit" () (register BI)) 366(define-hardware 367 (name h-sbit) 368 (comment "stack bit") 369 (type register BI) 370 (get () (c-call BI "@cpu@_h_sbit_get_handler")) 371 (set (newval) (c-call VOID "@cpu@_h_sbit_set_handler" newval)) 372) 373(dsh h-tbit "trace trap bit" () (register BI)) 374(dsh h-d0bit "division 0 bit" () (register BI)) 375(dsh h-d1bit "division 1 bit" () (register BI)) 376 377; These represent sub-registers within the program status register 378 379(define-hardware 380 (name h-ccr) 381 (comment "condition code bits") 382 (type register UQI) 383 (get () (c-call UQI "@cpu@_h_ccr_get_handler")) 384 (set (newval) (c-call VOID "@cpu@_h_ccr_set_handler" newval)) 385) 386(define-hardware 387 (name h-scr) 388 (comment "system condition bits") 389 (type register UQI) 390 (get () (c-call UQI "@cpu@_h_scr_get_handler")) 391 (set (newval) (c-call VOID "@cpu@_h_scr_set_handler" newval)) 392) 393(define-hardware 394 (name h-ilm) 395 (comment "interrupt level mask") 396 (type register UQI) 397 (get () (c-call UQI "@cpu@_h_ilm_get_handler")) 398 (set (newval) (c-call VOID "@cpu@_h_ilm_set_handler" newval)) 399) 400 401; Instruction Operands. 402; These entries provide a layer between the assembler and the raw hardware 403; description, and are used to refer to hardware elements in the semantic 404; code. Usually there's a bit of over-specification, but in more complicated 405; instruction sets there isn't. 406 407; FR30 specific operand attributes: 408 409(define-attr 410 (for operand) 411 (type boolean) 412 (name HASH-PREFIX) 413 (comment "immediates have an optional '#' prefix") 414) 415 416; ??? Convention says this should be o-sr, but then the insn definitions 417; should refer to o-sr which is clumsy. The "o-" could be implicit, but 418; then it should be implicit for all the symbols here, but then there would 419; be confusion between (f-)simm8 and (h-)simm8. 420; So for now the rule is exactly as it appears here. 421 422(dnop Ri "destination register" () h-gr f-Ri) 423(dnop Rj "source register" () h-gr f-Rj) 424(dnop Ric "target register coproc insn" () h-gr f-Ric) 425(dnop Rjc "source register coproc insn" () h-gr f-Rjc) 426(dnop CRi "coprocessor register" () h-cr f-CRi) 427(dnop CRj "coprocessor register" () h-cr f-CRj) 428(dnop Rs1 "dedicated register" () h-dr f-Rs1) 429(dnop Rs2 "dedicated register" () h-dr f-Rs2) 430(dnop R13 "General Register 13" () h-r13 f-nil) 431(dnop R14 "General Register 14" () h-r14 f-nil) 432(dnop R15 "General Register 15" () h-r15 f-nil) 433(dnop ps "Program Status register" () h-ps f-nil) 434(dnop u4 "4 bit unsigned immediate" (HASH-PREFIX) h-uint f-u4) 435(dnop u4c "4 bit unsigned immediate" (HASH-PREFIX) h-uint f-u4c) 436(dnop u8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-u8) 437(dnop i8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-i8) 438(dnop udisp6 "6 bit unsigned immediate" (HASH-PREFIX) h-uint f-udisp6) 439(dnop disp8 "8 bit signed immediate" (HASH-PREFIX) h-sint f-disp8) 440(dnop disp9 "9 bit signed immediate" (HASH-PREFIX) h-sint f-disp9) 441(dnop disp10 "10 bit signed immediate" (HASH-PREFIX) h-sint f-disp10) 442 443(dnop s10 "10 bit signed immediate" (HASH-PREFIX) h-sint f-s10) 444(dnop u10 "10 bit unsigned immediate" (HASH-PREFIX) h-uint f-u10) 445(dnop i32 "32 bit immediate" (HASH-PREFIX) h-uint f-i32) 446 447(define-operand 448 (name m4) 449 (comment "4 bit negative immediate") 450 (attrs HASH-PREFIX) 451 (type h-sint) 452 (index f-m4) 453 (handlers (print "m4")) 454) 455 456(define-operand 457 (name i20) 458 (comment "20 bit immediate") 459 (attrs HASH-PREFIX) 460 (type h-uint) 461 (index f-i20) 462) 463 464(dnop dir8 "8 bit direct address" () h-uint f-dir8) 465(dnop dir9 "9 bit direct address" () h-uint f-dir9) 466(dnop dir10 "10 bit direct address" () h-uint f-dir10) 467 468(dnop label9 "9 bit pc relative address" () h-iaddr f-rel9) 469(dnop label12 "12 bit pc relative address" () h-iaddr f-rel12) 470 471(define-operand 472 (name reglist_low_ld) 473 (comment "8 bit low register mask for ldm") 474 (attrs) 475 (type h-uint) 476 (index f-reglist_low_ld) 477 (handlers (parse "low_register_list_ld") 478 (print "low_register_list_ld")) 479) 480 481(define-operand 482 (name reglist_hi_ld) 483 (comment "8 bit high register mask for ldm") 484 (attrs) 485 (type h-uint) 486 (index f-reglist_hi_ld) 487 (handlers (parse "hi_register_list_ld") 488 (print "hi_register_list_ld")) 489) 490 491(define-operand 492 (name reglist_low_st) 493 (comment "8 bit low register mask for stm") 494 (attrs) 495 (type h-uint) 496 (index f-reglist_low_st) 497 (handlers (parse "low_register_list_st") 498 (print "low_register_list_st")) 499) 500 501(define-operand 502 (name reglist_hi_st) 503 (comment "8 bit high register mask for stm") 504 (attrs) 505 (type h-uint) 506 (index f-reglist_hi_st) 507 (handlers (parse "hi_register_list_st") 508 (print "hi_register_list_st")) 509) 510 511(dnop cc "condition codes" () h-uint f-cc) 512(dnop ccc "coprocessor calc" (HASH-PREFIX) h-uint f-ccc) 513 514(dnop nbit "negative bit" (SEM-ONLY) h-nbit f-nil) 515(dnop vbit "overflow bit" (SEM-ONLY) h-vbit f-nil) 516(dnop zbit "zero bit" (SEM-ONLY) h-zbit f-nil) 517(dnop cbit "carry bit" (SEM-ONLY) h-cbit f-nil) 518(dnop ibit "interrupt bit" (SEM-ONLY) h-ibit f-nil) 519(dnop sbit "stack bit" (SEM-ONLY) h-sbit f-nil) 520(dnop tbit "trace trap bit" (SEM-ONLY) h-tbit f-nil) 521(dnop d0bit "division 0 bit" (SEM-ONLY) h-d0bit f-nil) 522(dnop d1bit "division 1 bit" (SEM-ONLY) h-d1bit f-nil) 523 524(dnop ccr "condition code bits" (SEM-ONLY) h-ccr f-nil) 525(dnop scr "system condition bits" (SEM-ONLY) h-scr f-nil) 526(dnop ilm "interrupt level mask" (SEM-ONLY) h-ilm f-nil) 527 528; Instruction definitions. 529; 530; Notes: 531; - dni is short for "define-normal-instruction" 532 533; FR30 specific insn attributes: 534 535(define-attr 536 (for insn) 537 (type boolean) 538 (name NOT-IN-DELAY-SLOT) 539 (comment "insn can't go in delay slot") 540) 541 542; Sets zbit and nbit based on the value of x 543; 544(define-pmacro (set-z-and-n x) 545 (sequence () 546 (set zbit (eq x (const 0))) 547 (set nbit (lt x (const 0)))) 548) 549 550; Binary integer instruction which sets status bits 551; 552(define-pmacro (binary-int-op name insn comment opc1 opc2 op arg1 arg2) 553 (dni name 554 (.str insn " " comment) 555 () 556 (.str insn " $" arg1 ",$" arg2) 557 (+ opc1 opc2 arg1 arg2) 558 (sequence () 559 (set vbit ((.sym op -oflag) arg2 arg1 (const 0))) 560 (set cbit ((.sym op -cflag) arg2 arg1 (const 0))) 561 (set arg2 (op arg2 arg1)) 562 (set-z-and-n arg2)) 563 () 564 ) 565) 566 567; Binary integer instruction which does *not* set status bits 568; 569(define-pmacro (binary-int-op-n name insn comment opc1 opc2 op arg1 arg2) 570 (dni name 571 (.str insn " " comment) 572 () 573 (.str insn " $" arg1 ",$" arg2) 574 (+ opc1 opc2 arg1 arg2) 575 (set arg2 (op arg2 arg1)) 576 () 577 ) 578) 579 580; Binary integer instruction with carry which sets status bits 581; 582(define-pmacro (binary-int-op-c name insn comment opc1 opc2 op arg1 arg2) 583 (dni name 584 (.str insn " " comment) 585 () 586 (.str insn " $" arg1 ",$" arg2) 587 (+ opc1 opc2 arg1 arg2) 588 (sequence ((WI tmp)) 589 (set tmp ((.sym op c) arg2 arg1 cbit)) 590 (set vbit ((.sym op -oflag) arg2 arg1 cbit)) 591 (set cbit ((.sym op -cflag) arg2 arg1 cbit)) 592 (set arg2 tmp) 593 (set-z-and-n arg2)) 594 () 595 ) 596) 597 598(binary-int-op add add "reg/reg" OP1_A OP2_6 add Rj Ri) 599(binary-int-op addi add "immed/reg" OP1_A OP2_4 add u4 Ri) 600(binary-int-op add2 add2 "immed/reg" OP1_A OP2_5 add m4 Ri) 601(binary-int-op-c addc addc "reg/reg" OP1_A OP2_7 add Rj Ri) 602(binary-int-op-n addn addn "reg/reg" OP1_A OP2_2 add Rj Ri) 603(binary-int-op-n addni addn "immed/reg" OP1_A OP2_0 add u4 Ri) 604(binary-int-op-n addn2 addn2 "immed/reg" OP1_A OP2_1 add m4 Ri) 605 606(binary-int-op sub sub "reg/reg" OP1_A OP2_C sub Rj Ri) 607(binary-int-op-c subc subc "reg/reg" OP1_A OP2_D sub Rj Ri) 608(binary-int-op-n subn subn "reg/reg" OP1_A OP2_E sub Rj Ri) 609 610; Integer compare instruction 611; 612(define-pmacro (int-cmp name insn comment opc1 opc2 arg1 arg2) 613 (dni name 614 (.str insn " " comment) 615 () 616 (.str insn " $" arg1 ",$" arg2) 617 (+ opc1 opc2 arg1 arg2) 618 (sequence ((WI tmp1)) 619 (set vbit (sub-oflag arg2 arg1 (const 0))) 620 (set cbit (sub-cflag arg2 arg1 (const 0))) 621 (set tmp1 (sub arg2 arg1)) 622 (set-z-and-n tmp1) 623 ) 624 () 625 ) 626) 627 628(int-cmp cmp cmp "reg/reg" OP1_A OP2_A Rj Ri) 629(int-cmp cmpi cmp "immed/reg" OP1_A OP2_8 u4 Ri) 630(int-cmp cmp2 cmp2 "immed/reg" OP1_A OP2_9 m4 Ri) 631 632; Binary logical instruction 633; 634(define-pmacro (binary-logical-op name insn comment opc1 opc2 op arg1 arg2) 635 (dni name 636 (.str insn " " comment) 637 () 638 (.str insn " $" arg1 ",$" arg2) 639 (+ opc1 opc2 arg1 arg2) 640 (sequence () 641 (set arg2 (op arg2 arg1)) 642 (set-z-and-n arg2)) 643 () 644 ) 645) 646 647(binary-logical-op and and "reg/reg" OP1_8 OP2_2 and Rj Ri) 648(binary-logical-op or or "reg/reg" OP1_9 OP2_2 or Rj Ri) 649(binary-logical-op eor eor "reg/reg" OP1_9 OP2_A xor Rj Ri) 650 651(define-pmacro (les-units model) ; les: load-exec-store 652 (model (unit u-exec) (unit u-load) (unit u-store)) 653) 654 655; Binary logical instruction to memory 656; 657(define-pmacro (binary-logical-op-m name insn comment opc1 opc2 mode op arg1 arg2) 658 (dni name 659 (.str insn " " comment) 660 (NOT-IN-DELAY-SLOT) 661 (.str insn " $" arg1 ",@$" arg2) 662 (+ opc1 opc2 arg1 arg2) 663 (sequence ((mode tmp)) 664 (set mode tmp (op mode (mem mode arg2) arg1)) 665 (set-z-and-n tmp) 666 (set mode (mem mode arg2) tmp)) 667 ((les-units fr30-1)) 668 ) 669) 670 671(binary-logical-op-m andm and "reg/mem" OP1_8 OP2_4 WI and Rj Ri) 672(binary-logical-op-m andh andh "reg/mem" OP1_8 OP2_5 HI and Rj Ri) 673(binary-logical-op-m andb andb "reg/mem" OP1_8 OP2_6 QI and Rj Ri) 674(binary-logical-op-m orm or "reg/mem" OP1_9 OP2_4 WI or Rj Ri) 675(binary-logical-op-m orh orh "reg/mem" OP1_9 OP2_5 HI or Rj Ri) 676(binary-logical-op-m orb orb "reg/mem" OP1_9 OP2_6 QI or Rj Ri) 677(binary-logical-op-m eorm eor "reg/mem" OP1_9 OP2_C WI xor Rj Ri) 678(binary-logical-op-m eorh eorh "reg/mem" OP1_9 OP2_D HI xor Rj Ri) 679(binary-logical-op-m eorb eorb "reg/mem" OP1_9 OP2_E QI xor Rj Ri) 680 681; Binary logical instruction to low half of byte in memory 682; 683(dni bandl 684 "bandl #u4,@Ri" 685 (NOT-IN-DELAY-SLOT) 686 "bandl $u4,@$Ri" 687 (+ OP1_8 OP2_0 u4 Ri) 688 (set QI (mem QI Ri) 689 (and QI 690 (or QI u4 (const #xf0)) 691 (mem QI Ri))) 692 ((les-units fr30-1)) 693) 694 695(dni borl 696 "borl #u4,@Ri" 697 (NOT-IN-DELAY-SLOT) 698 "borl $u4,@$Ri" 699 (+ OP1_9 OP2_0 u4 Ri) 700 (set QI (mem QI Ri) (or QI u4 (mem QI Ri))) 701 ((les-units fr30-1)) 702) 703 704(dni beorl 705 "beorl #u4,@Ri" 706 (NOT-IN-DELAY-SLOT) 707 "beorl $u4,@$Ri" 708 (+ OP1_9 OP2_8 u4 Ri) 709 (set QI (mem QI Ri) (xor QI u4 (mem QI Ri))) 710 ((les-units fr30-1)) 711) 712 713; Binary logical instruction to high half of byte in memory 714; 715(dni bandh 716 "bandh #u4,@Ri" 717 (NOT-IN-DELAY-SLOT) 718 "bandh $u4,@$Ri" 719 (+ OP1_8 OP2_1 u4 Ri) 720 (set QI (mem QI Ri) 721 (and QI 722 (or QI (sll QI u4 (const 4)) (const #x0f)) 723 (mem QI Ri))) 724 ((les-units fr30-1)) 725) 726 727(define-pmacro (binary-or-op-mh name insn opc1 opc2 op arg1 arg2) 728 (dni name 729 (.str name " #" arg1 ",@" args) 730 (NOT-IN-DELAY-SLOT) 731 (.str name " $" arg1 ",@$" arg2) 732 (+ opc1 opc2 arg1 arg2) 733 (set QI (mem QI arg2) 734 (insn QI 735 (sll QI arg1 (const 4)) 736 (mem QI arg2))) 737 ((les-units fr30-1)) 738 ) 739) 740 741(binary-or-op-mh borh or OP1_9 OP2_1 or u4 Ri) 742(binary-or-op-mh beorh xor OP1_9 OP2_9 xor u4 Ri) 743 744(dni btstl 745 "btstl #u4,@Ri" 746 (NOT-IN-DELAY-SLOT) 747 "btstl $u4,@$Ri" 748 (+ OP1_8 OP2_8 u4 Ri) 749 (sequence ((QI tmp)) 750 (set tmp (and QI u4 (mem QI Ri))) 751 (set zbit (eq tmp (const 0))) 752 (set nbit (const 0))) 753 ((fr30-1 (unit u-load) (unit u-exec (cycles 2)))) 754) 755 756(dni btsth 757 "btsth #u4,@Ri" 758 (NOT-IN-DELAY-SLOT) 759 "btsth $u4,@$Ri" 760 (+ OP1_8 OP2_9 u4 Ri) 761 (sequence ((QI tmp)) 762 (set tmp (and QI (sll QI u4 (const 4)) (mem QI Ri))) 763 (set zbit (eq tmp (const 0))) 764 (set nbit (lt tmp (const 0)))) 765 ((fr30-1 (unit u-load) (unit u-exec (cycles 2)))) 766) 767 768(dni mul 769 "mul Rj,Ri" 770 (NOT-IN-DELAY-SLOT) 771 "mul $Rj,$Ri" 772 (+ OP1_A OP2_F Rj Ri) 773 (sequence ((DI tmp)) 774 (set tmp (mul DI (ext DI Rj) (ext DI Ri))) 775 (set (reg h-dr 5) (trunc WI tmp)) 776 (set (reg h-dr 4) (trunc WI (srl tmp (const 32)))) 777 (set nbit (lt (reg h-dr 5) (const 0))) 778 (set zbit (eq tmp (const DI 0))) 779 (set vbit (orif 780 (gt tmp (const DI #x7fffffff)) 781 (lt tmp (neg (const DI #x80000000)))))) 782 ((fr30-1 (unit u-exec (cycles 5)))) 783) 784 785(dni mulu 786 "mulu Rj,Ri" 787 (NOT-IN-DELAY-SLOT) 788 "mulu $Rj,$Ri" 789 (+ OP1_A OP2_B Rj Ri) 790 (sequence ((DI tmp)) 791 (set tmp (mul DI (zext DI Rj) (zext DI Ri))) 792 (set (reg h-dr 5) (trunc WI tmp)) 793 (set (reg h-dr 4) (trunc WI (srl tmp (const 32)))) 794 (set nbit (lt (reg h-dr 4) (const 0))) 795 (set zbit (eq (reg h-dr 5) (const 0))) 796 (set vbit (ne (reg h-dr 4) (const 0)))) 797 ((fr30-1 (unit u-exec (cycles 5)))) 798) 799 800(dni mulh 801 "mulh Rj,Ri" 802 (NOT-IN-DELAY-SLOT) 803 "mulh $Rj,$Ri" 804 (+ OP1_B OP2_F Rj Ri) 805 (sequence () 806 (set (reg h-dr 5) (mul (trunc HI Rj) (trunc HI Ri))) 807 (set nbit (lt (reg h-dr 5) (const 0))) 808 (set zbit (ge (reg h-dr 5) (const 0)))) 809 ((fr30-1 (unit u-exec (cycles 3)))) 810) 811 812(dni muluh 813 "muluh Rj,Ri" 814 (NOT-IN-DELAY-SLOT) 815 "muluh $Rj,$Ri" 816 (+ OP1_B OP2_B Rj Ri) 817 (sequence () 818 (set (reg h-dr 5) (mul (and Rj (const #xffff)) 819 (and Ri (const #xffff)))) 820 (set nbit (lt (reg h-dr 5) (const 0))) 821 (set zbit (ge (reg h-dr 5) (const 0)))) 822 ((fr30-1 (unit u-exec (cycles 3)))) 823) 824 825(dni div0s 826 "div0s Ri" 827 () 828 "div0s $Ri" 829 (+ OP1_9 OP2_7 OP3_4 Ri) 830 (sequence () 831 (set d0bit (lt (reg h-dr 5) (const 0))) 832 (set d1bit (xor d0bit (lt Ri (const 0)))) 833 (if (ne d0bit (const 0)) 834 (set (reg h-dr 4) (const #xffffffff)) 835 (set (reg h-dr 4) (const 0)))) 836 () 837) 838 839(dni div0u 840 "div0u Ri" 841 () 842 "div0u $Ri" 843 (+ OP1_9 OP2_7 OP3_5 Ri) 844 (sequence () 845 (set d0bit (const 0)) 846 (set d1bit (const 0)) 847 (set (reg h-dr 4) (const 0))) 848 () 849) 850 851(dni div1 852 "div1 Ri" 853 () 854 "div1 $Ri" 855 (+ OP1_9 OP2_7 OP3_6 Ri) 856 (sequence ((WI tmp)) 857 (set (reg h-dr 4) (sll (reg h-dr 4) (const 1))) 858 (if (lt (reg h-dr 5) (const 0)) 859 (set (reg h-dr 4) (add (reg h-dr 4) (const 1)))) 860 (set (reg h-dr 5) (sll (reg h-dr 5) (const 1))) 861 (if (eq d1bit (const 1)) 862 (sequence () 863 (set tmp (add (reg h-dr 4) Ri)) 864 (set cbit (add-cflag (reg h-dr 4) Ri (const 0)))) 865 (sequence () 866 (set tmp (sub (reg h-dr 4) Ri)) 867 (set cbit (sub-cflag (reg h-dr 4) Ri (const 0))))) 868 (if (not (xor (xor d0bit d1bit) cbit)) 869 (sequence () 870 (set (reg h-dr 4) tmp) 871 (set (reg h-dr 5) (or (reg h-dr 5) (const 1))))) 872 (set zbit (eq (reg h-dr 4) (const 0)))) 873 () 874) 875 876(dni div2 877 "div2 Ri" 878 () 879 "div2 $Ri" 880 (+ OP1_9 OP2_7 OP3_7 Ri) 881 (sequence ((WI tmp)) 882 (if (eq d1bit (const 1)) 883 (sequence () 884 (set tmp (add (reg h-dr 4) Ri)) 885 (set cbit (add-cflag (reg h-dr 4) Ri (const 0)))) 886 (sequence () 887 (set tmp (sub (reg h-dr 4) Ri)) 888 (set cbit (sub-cflag (reg h-dr 4) Ri (const 0))))) 889 (if (eq tmp (const 0)) 890 (sequence () 891 (set zbit (const 1)) 892 (set (reg h-dr 4) (const 0))) 893 (set zbit (const 0)))) 894 () 895) 896 897(dni div3 898 "div3" 899 () 900 "div3" 901 (+ OP1_9 OP2_F OP3_6 OP4_0) 902 (if (eq zbit (const 1)) 903 (set (reg h-dr 5) (add (reg h-dr 5) (const 1)))) 904 () 905) 906 907(dni div4s 908 "div4s" 909 () 910 "div4s" 911 (+ OP1_9 OP2_F OP3_7 OP4_0) 912 (if (eq d1bit (const 1)) 913 (set (reg h-dr 5) (neg (reg h-dr 5)))) 914 () 915) 916 917(define-pmacro (leftshift-op name insn opc1 opc2 arg1 arg2 shift-expr) 918 (dni name 919 (.str insn " " arg1 "," arg2) 920 () 921 (.str insn " $" arg1 ",$" arg2) 922 (+ opc1 opc2 arg1 arg2) 923 (sequence ((WI shift)) 924 (set shift shift-expr) 925 (if (ne shift (const 0)) 926 (sequence () 927 (set cbit (ne (and arg2 928 (sll (const 1) 929 (sub (const 32) shift))) 930 (const 0))) 931 (set arg2 (sll arg2 shift))) 932 (set cbit (const 0))) 933 (set nbit (lt arg2 (const 0))) 934 (set zbit (eq arg2 (const 0)))) 935 () 936 ) 937) 938(leftshift-op lsl lsl OP1_B OP2_6 Rj Ri (and Rj (const #x1f))) 939(leftshift-op lsli lsl OP1_B OP2_4 u4 Ri u4) 940(leftshift-op lsl2 lsl2 OP1_B OP2_5 u4 Ri (add u4 (const #x10))) 941 942(define-pmacro (rightshift-op name insn opc1 opc2 op arg1 arg2 shift-expr) 943 (dni name 944 (.str insn " " arg1 "," arg2) 945 () 946 (.str insn " $" arg1 ",$" arg2) 947 (+ opc1 opc2 arg1 arg2) 948 (sequence ((WI shift)) 949 (set shift shift-expr) 950 (if (ne shift (const 0)) 951 (sequence () 952 (set cbit (ne (and arg2 953 (sll (const 1) 954 (sub shift (const 1)))) 955 (const 0))) 956 (set arg2 (op arg2 shift))) 957 (set cbit (const 0))) 958 (set nbit (lt arg2 (const 0))) 959 (set zbit (eq arg2 (const 0)))) 960 () 961 ) 962) 963(rightshift-op lsr lsr OP1_B OP2_2 srl Rj Ri (and Rj (const #x1f))) 964(rightshift-op lsri lsr OP1_B OP2_0 srl u4 Ri u4) 965(rightshift-op lsr2 lsr2 OP1_B OP2_1 srl u4 Ri (add u4 (const #x10))) 966(rightshift-op asr asr OP1_B OP2_A sra Rj Ri (and Rj (const #x1f))) 967(rightshift-op asri asr OP1_B OP2_8 sra u4 Ri u4) 968(rightshift-op asr2 asr2 OP1_B OP2_9 sra u4 Ri (add u4 (const #x10))) 969 970(dni ldi8 971 "load 8 bit unsigned immediate" 972 () 973 "ldi:8 $i8,$Ri" 974 (+ OP1_C i8 Ri) 975 (set Ri i8) 976 () 977) 978 979; Typing ldi:8 in in emacs is a pain. 980(dnmi ldi8m "ldi:8 without the colon" 981 (NO-DIS) 982 "ldi8 $i8,$Ri" 983 (emit ldi8 i8 Ri) 984) 985 986(dni ldi20 987 "load 20 bit unsigned immediate" 988 (NOT-IN-DELAY-SLOT) 989 "ldi:20 $i20,$Ri" 990 (+ OP1_9 OP2_B Ri i20) 991 (set Ri i20) 992 ((fr30-1 (unit u-exec (cycles 2)))) 993) 994 995; Typing ldi:20 in in emacs is a pain. 996(dnmi ldi20m "ldi:20 without the colon" 997 (NO-DIS) 998 "ldi20 $i20,$Ri" 999 (emit ldi20 i20 Ri) 1000) 1001 1002(dni ldi32 1003 "load 32 bit immediate" 1004 (NOT-IN-DELAY-SLOT) 1005 "ldi:32 $i32,$Ri" 1006 (+ OP1_9 OP2_F OP3_8 Ri i32) 1007 (set Ri i32) 1008 ((fr30-1 (unit u-exec (cycles 3)))) 1009) 1010 1011; Typing ldi:32 in in emacs is a pain. 1012(dnmi ldi32m "ldi:32 without the colon" 1013 (NO-DIS) 1014 "ldi32 $i32,$Ri" 1015 (emit ldi32 i32 Ri) 1016) 1017 1018(define-pmacro (basic-ld name insn opc1 opc2 mode arg1 arg2) 1019 (dni name 1020 (.str name " @" arg1 "," arg2) 1021 () 1022 (.str name " @$" arg1 ",$" arg2) 1023 (+ opc1 opc2 arg1 arg2) 1024 (set arg2 (mem mode arg1)) 1025 ((fr30-1 (unit u-load))) 1026 ) 1027) 1028 1029(basic-ld ld ld OP1_0 OP2_4 WI Rj Ri) 1030(basic-ld lduh lduh OP1_0 OP2_5 UHI Rj Ri) 1031(basic-ld ldub ldub OP1_0 OP2_6 UQI Rj Ri) 1032 1033(define-pmacro (r13base-ld name insn opc1 opc2 mode arg1 arg2) 1034 (dni name 1035 (.str insn " @(R13," arg1 ")," arg2) 1036 () 1037 (.str insn " @($R13,$" arg1 "),$" arg2) 1038 (+ opc1 opc2 arg1 arg2) 1039 (set arg2 (mem mode (add arg1 (reg h-gr 13)))) 1040 ((fr30-1 (unit u-load))) 1041 ) 1042) 1043 1044(r13base-ld ldr13 ld OP1_0 OP2_0 WI Rj Ri) 1045(r13base-ld ldr13uh lduh OP1_0 OP2_1 UHI Rj Ri) 1046(r13base-ld ldr13ub ldub OP1_0 OP2_2 UQI Rj Ri) 1047 1048(define-pmacro (r14base-ld name insn opc1 mode arg1 arg2) 1049 (dni name 1050 (.str insn " @(R14," arg1 ")," arg2) 1051 () 1052 (.str insn " @($R14,$" arg1 "),$" arg2) 1053 (+ opc1 arg1 arg2) 1054 (set arg2 (mem mode (add arg1 (reg h-gr 14)))) 1055 ((fr30-1 (unit u-load))) 1056 ) 1057) 1058 1059(r14base-ld ldr14 ld OP1_2 WI disp10 Ri) 1060(r14base-ld ldr14uh lduh OP1_4 UHI disp9 Ri) 1061(r14base-ld ldr14ub ldub OP1_6 UQI disp8 Ri) 1062 1063(dni ldr15 1064 "ld @(R15,udisp6),Ri mem/reg" 1065 () 1066 "ld @($R15,$udisp6),$Ri" 1067 (+ OP1_0 OP2_3 udisp6 Ri) 1068 (set Ri (mem WI (add udisp6 (reg h-gr 15)))) 1069 ((fr30-1 (unit u-load))) 1070) 1071 1072(dni ldr15gr 1073 "ld @R15+,Ri" 1074 () 1075 "ld @$R15+,$Ri" 1076 (+ OP1_0 OP2_7 OP3_0 Ri) 1077 (sequence () 1078 (set Ri (mem WI (reg h-gr 15))) 1079 (if (ne (ifield f-Ri) (const 15)) 1080 (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) 1081 ((fr30-1 (unit u-load))) 1082) 1083 1084; This insn loads a value from where r15 points into the target register and 1085; then increments r15. If the target register is also r15, then the post 1086; increment is not performed. 1087; 1088(dni ldr15dr 1089 "ld @R15+,Rs2" 1090 () 1091 "ld @$R15+,$Rs2" 1092 (+ OP1_0 OP2_7 OP3_8 Rs2) 1093; This seems more straight forward, but doesn't work due to a problem in 1094; cgen. We're trying to not increment r15 if it is the target register. 1095; (sequence () 1096; (set Rs2 (mem WI (reg h-gr 15))) 1097; (if (not (or (and (eq (ifield f-Rs2) (const 2)) 1098; (eq sbit (const 0))) 1099; (and (eq (ifield f-Rs2) (const 3)) 1100; (eq sbit (const 1))))) 1101; (set (reg h-gr 15) (add (reg h-gr 15) (const 4))) 1102; ) 1103; ) 1104 (sequence ((WI tmp)) 1105 (set tmp (mem WI (reg h-gr 15))) ; save in case target is r15 1106 (set (reg h-gr 15) (add (reg h-gr 15) (const 4))) 1107 (set Rs2 tmp)) 1108 ((fr30-1 (unit u-load))) 1109) 1110 1111(dni ldr15ps 1112 "ld @R15+,ps mem/reg" 1113 (NOT-IN-DELAY-SLOT) 1114 "ld @$R15+,$ps" 1115 (+ OP1_0 OP2_7 OP3_9 OP4_0) 1116 (sequence () 1117 (set ps (mem WI (reg h-gr 15))) 1118 (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))) 1119 ((fr30-1 (unit u-load))) 1120) 1121 1122(define-pmacro (basic-st name insn opc1 opc2 mode arg1 arg2) 1123 (dni name 1124 (.str name " " arg1 ",@" arg2) 1125 () 1126 (.str name " $" arg1 ",@$" arg2) 1127 (+ opc1 opc2 arg1 arg2) 1128 (set (mem mode arg2) arg1) 1129 ((fr30-1 (unit u-store))) 1130 ) 1131) 1132 1133(basic-st st st OP1_1 OP2_4 WI Ri Rj) 1134(basic-st sth sth OP1_1 OP2_5 HI Ri Rj) 1135(basic-st stb stb OP1_1 OP2_6 QI Ri Rj) 1136 1137(define-pmacro (r13base-st name insn opc1 opc2 mode arg1 arg2) 1138 (dni name 1139 (.str insn " " arg1 ",@(R13," arg2 ")") 1140 () 1141 (.str insn " $" arg1 ",@($R13,$" arg2 ")") 1142 (+ opc1 opc2 arg1 arg2) 1143 (set (mem mode (add arg2 (reg h-gr 13))) arg1) 1144 ((fr30-1 (unit u-store))) 1145 ) 1146) 1147 1148(r13base-st str13 st OP1_1 OP2_0 WI Ri Rj) 1149(r13base-st str13h sth OP1_1 OP2_1 HI Ri Rj) 1150(r13base-st str13b stb OP1_1 OP2_2 QI Ri Rj) 1151 1152(define-pmacro (r14base-st name insn opc1 mode arg1 arg2) 1153 (dni name 1154 (.str insn " " arg1 ",@(R14," arg2 ")") 1155 () 1156 (.str insn " $" arg1 ",@($R14,$" arg2 ")") 1157 (+ opc1 arg1 arg2) 1158 (set (mem mode (add arg2 (reg h-gr 14))) arg1) 1159 ((fr30-1 (unit u-store))) 1160 ) 1161) 1162 1163(r14base-st str14 st OP1_3 WI Ri disp10) 1164(r14base-st str14h sth OP1_5 HI Ri disp9) 1165(r14base-st str14b stb OP1_7 QI Ri disp8) 1166 1167(dni str15 1168 "st Ri,@(R15,udisp6) reg/mem" 1169 () 1170 "st $Ri,@($R15,$udisp6)" 1171 (+ OP1_1 OP2_3 udisp6 Ri) 1172 (set (mem WI (add (reg h-gr 15) udisp6)) Ri) 1173 ((fr30-1 (unit u-store))) 1174) 1175 1176; These store insns predecrement r15 and then store the contents of the source 1177; register where r15 then points. If the source register is also r15, then the 1178; original value of r15 is stored. 1179; 1180(dni str15gr 1181 "st Ri,@-R15 reg/mem" 1182 () 1183 "st $Ri,@-$R15" 1184 (+ OP1_1 OP2_7 OP3_0 Ri) 1185 (sequence ((WI tmp)) 1186 (set tmp Ri) ; save in case it's r15 1187 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) 1188 (set (mem WI (reg h-gr 15)) tmp)) 1189 ((fr30-1 (unit u-store))) 1190) 1191 1192(dni str15dr 1193 "st Rs,@-R15 reg/mem" 1194 () 1195 "st $Rs2,@-$R15" 1196 (+ OP1_1 OP2_7 OP3_8 Rs2) 1197 (sequence ((WI tmp)) 1198 (set tmp Rs2) ; save in case it's r15 1199 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) 1200 (set (mem WI (reg h-gr 15)) tmp)) 1201 ((fr30-1 (unit u-store))) 1202) 1203 1204(dni str15ps 1205 "st ps,@-R15 reg/mem" 1206 () 1207 "st $ps,@-$R15" 1208 (+ OP1_1 OP2_7 OP3_9 OP4_0) 1209 (sequence () 1210 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) 1211 (set (mem WI (reg h-gr 15)) ps)) 1212 ((fr30-1 (unit u-store))) 1213) 1214 1215(define-pmacro (mov2gr name opc1 opc2 arg1 arg2) 1216 (dni name 1217 (.str "mov " arg1 "," arg2) 1218 () 1219 (.str "mov $" arg1 ",$" arg2) 1220 (+ opc1 opc2 arg1 arg2) 1221 (set arg2 arg1) 1222 () 1223 ) 1224) 1225 1226(mov2gr mov OP1_8 OP2_B Rj Ri) 1227(mov2gr movdr OP1_B OP2_7 Rs1 Ri) 1228 1229(dni movps 1230 "mov ps,Ri reg/reg" 1231 () 1232 "mov $ps,$Ri" 1233 (+ OP1_1 OP2_7 OP3_1 Ri) 1234 (set Ri ps) 1235 () 1236) 1237 1238(dni mov2dr 1239 "mov Ri,Rs reg/reg" 1240 () 1241 "mov $Ri,$Rs1" 1242 (+ OP1_B OP2_3 Rs1 Ri) 1243 (set Rs1 Ri) 1244 () 1245) 1246 1247(dni mov2ps 1248 "mov Ri,ps reg/reg" 1249 () 1250 "mov $Ri,$ps" 1251 (+ OP1_0 OP2_7 OP3_1 Ri) 1252 (set ps Ri) 1253 () 1254) 1255 1256(dni jmp 1257 "jmp with no delay slot" 1258 (NOT-IN-DELAY-SLOT) 1259 "jmp @$Ri" 1260 (+ OP1_9 OP2_7 OP3_0 Ri) 1261 (set pc Ri) 1262 ((fr30-1 (unit u-cti))) 1263) 1264 1265(dni jmpd "jmp with delay slot" 1266 (NOT-IN-DELAY-SLOT) 1267 "jmp:d @$Ri" 1268 (+ OP1_9 OP2_F OP3_0 Ri) 1269 (delay (const 1) 1270 (set pc Ri)) 1271 ((fr30-1 (unit u-cti))) 1272) 1273 1274; These versions which use registers must appear before the other 1275; versions which use relative addresses due to a problem in cgen 1276; - DB. 1277(dni callr 1278 "call @Ri" 1279 (NOT-IN-DELAY-SLOT) 1280 "call @$Ri" 1281 (+ OP1_9 OP2_7 OP3_1 Ri) 1282 (sequence () 1283 (set (reg h-dr 1) (add pc (const 2))) 1284 (set pc Ri)) 1285 ((fr30-1 (unit u-cti))) 1286) 1287(dni callrd 1288 "call:d @Ri" 1289 (NOT-IN-DELAY-SLOT) 1290 "call:d @$Ri" 1291 (+ OP1_9 OP2_F OP3_1 Ri) 1292 (delay (const 1) 1293 (sequence () 1294 (set (reg h-dr 1) (add pc (const 4))) 1295 (set pc Ri))) 1296 ((fr30-1 (unit u-cti))) 1297) 1298; end of reordered insns 1299 1300(dni call 1301 "call relative to pc" 1302 (NOT-IN-DELAY-SLOT) 1303 "call $label12" 1304 (+ OP1_D OP5_0 label12) 1305 (sequence () 1306 (set (reg h-dr 1) (add pc (const 2))) 1307 (set pc label12)) 1308 ((fr30-1 (unit u-cti))) 1309) 1310(dni calld 1311 "call relative to pc" 1312 (NOT-IN-DELAY-SLOT) 1313 "call:d $label12" 1314 (+ OP1_D OP5_1 label12) 1315 (delay (const 1) 1316 (sequence () 1317 (set (reg h-dr 1) (add pc (const 4))) 1318 (set pc label12))) 1319 ((fr30-1 (unit u-cti))) 1320) 1321 1322(dni ret 1323 "return from subroutine" 1324 (NOT-IN-DELAY-SLOT) 1325 "ret" 1326 (+ OP1_9 OP2_7 OP3_2 OP4_0) 1327 (set pc (reg h-dr 1)) 1328 ((fr30-1 (unit u-cti))) 1329) 1330 1331(dni ret:d 1332 "return from subroutine with delay slot" 1333 (NOT-IN-DELAY-SLOT) 1334 "ret:d" 1335 (+ OP1_9 OP2_F OP3_2 OP4_0) 1336 (delay (const 1) 1337 (set pc (reg h-dr 1))) 1338 ((fr30-1 (unit u-cti))) 1339) 1340 1341(dni int 1342 "interrupt" 1343 (NOT-IN-DELAY-SLOT) 1344 "int $u8" 1345 (+ OP1_1 OP2_F u8) 1346 (sequence () 1347 ; This is defered to fr30_int because for the breakpoint case 1348 ; we want to change as little of the machine state as possible. 1349 ; Push PS onto the system stack 1350 ;(set (reg h-dr 2) (sub (reg h-dr 2) (const 4))) 1351 ;(set UWI (mem UWI (reg h-dr 2)) ps) 1352 ; Push the return address onto the system stack 1353 ;(set (reg h-dr 2) (sub (reg h-dr 2) (const 4))) 1354 ;(set UWI (mem UWI (reg h-dr 2)) (add pc (const 2))) 1355 ; Set status bits 1356 ;(set ibit (const 0)) 1357 ;(set sbit (const 0)) 1358 1359 ; We still should indicate what is modified by this insn. 1360 (clobber (reg h-dr 2)) 1361 (clobber ibit) 1362 (clobber sbit) 1363 ; ??? (clobber memory)? 1364 1365 ; fr30_int handles operating vs user mode 1366 (set WI pc (c-call WI "fr30_int" pc u8)) 1367 ) 1368 ; This is more properly a cti, but branch stall calculation is different. 1369 ((fr30-1 (unit u-exec (cycles 6)))) 1370) 1371 1372(dni inte 1373 "interrupt for emulator" 1374 (NOT-IN-DELAY-SLOT) 1375 "inte" 1376 (+ OP1_9 OP2_F OP3_3 OP4_0) 1377 (sequence () 1378 ; This is defered to fr30_inte because for the breakpoint case 1379 ; we want to change as little of the machine state as possible. 1380 ; Push PS onto the system stack 1381 ;(set (reg h-dr 2) (sub (reg h-dr 2) (const 4))) 1382 ;(set UWI (mem UWI (reg h-dr 2)) ps) 1383 ; Push the return address onto the system stack 1384 ;(set (reg h-dr 2) (sub (reg h-dr 2) (const 4))) 1385 ;(set UWI (mem UWI (reg h-dr 2)) (add pc (const 2))) 1386 ; Set status bits 1387 ;(set ibit (const 0)) 1388 ;(set ilm (const 4)) 1389 1390 ; We still should indicate what is modified by this insn. 1391 (clobber (reg h-dr 2)) 1392 (clobber ibit) 1393 (clobber ilm) 1394 ; ??? (clobber memory)? 1395 1396 ; fr30_int handles operating vs user mode 1397 (set WI pc (c-call WI "fr30_inte" pc)) 1398 ) 1399 ; This is more properly a cti, but branch stall calculation is different. 1400 ((fr30-1 (unit u-exec (cycles 6)))) 1401) 1402 1403(dni reti 1404 "return from interrupt" 1405 (NOT-IN-DELAY-SLOT) 1406 "reti" 1407 (+ OP1_9 OP2_7 OP3_3 OP4_0) 1408 (if (eq sbit (const 0)) 1409 (sequence () 1410 ; Pop the return address from the system stack 1411 (set UWI pc (mem UWI (reg h-dr 2))) 1412 (set (reg h-dr 2) (add (reg h-dr 2) (const 4))) 1413 ; Pop PS from the system stack 1414 (set UWI ps (mem UWI (reg h-dr 2))) 1415 (set (reg h-dr 2) (add (reg h-dr 2) (const 4))) 1416 ) 1417 (sequence () 1418 ; Pop the return address from the user stack 1419 (set UWI pc (mem UWI (reg h-dr 3))) 1420 (set (reg h-dr 3) (add (reg h-dr 3) (const 4))) 1421 ; Pop PS from the user stack 1422 (set UWI ps (mem UWI (reg h-dr 3))) 1423 (set (reg h-dr 3) (add (reg h-dr 3) (const 4))) 1424 ) 1425 ) 1426 ; This is more properly a cti, but branch stall calculation is different. 1427 ((fr30-1 (unit u-exec (cycles 4)))) 1428) 1429 1430; Conditional branches with and without delay slots 1431; 1432(define-pmacro (cond-branch cc condition) 1433 (begin 1434 (dni (.sym b cc d) 1435 (.str (.sym b cc :d) " label9") 1436 (NOT-IN-DELAY-SLOT) 1437 (.str (.sym b cc :d) " $label9") 1438 (+ OP1_F (.sym CC_ cc) label9) 1439 (delay (const 1) 1440 (if condition (set pc label9))) 1441 ((fr30-1 (unit u-cti))) 1442 ) 1443 (dni (.sym b cc) 1444 (.str (.sym b cc) " label9") 1445 (NOT-IN-DELAY-SLOT) 1446 (.str (.sym b cc) " $label9") 1447 (+ OP1_E (.sym CC_ cc) label9) 1448 (if condition (set pc label9)) 1449 ((fr30-1 (unit u-cti))) 1450 ) 1451 ) 1452) 1453 1454(cond-branch ra (const BI 1)) 1455(cond-branch no (const BI 0)) 1456(cond-branch eq zbit) 1457(cond-branch ne (not zbit)) 1458(cond-branch c cbit) 1459(cond-branch nc (not cbit)) 1460(cond-branch n nbit) 1461(cond-branch p (not nbit)) 1462(cond-branch v vbit) 1463(cond-branch nv (not vbit)) 1464(cond-branch lt (xor vbit nbit)) 1465(cond-branch ge (not (xor vbit nbit))) 1466(cond-branch le (or (xor vbit nbit) zbit)) 1467(cond-branch gt (not (or (xor vbit nbit) zbit))) 1468(cond-branch ls (or cbit zbit)) 1469(cond-branch hi (not (or cbit zbit))) 1470 1471(define-pmacro (dir2r13 name insn opc1 opc2 mode arg1) 1472 (dni name 1473 (.str insn " @" arg1 ",R13") 1474 () 1475 (.str insn " @$" arg1 ",$R13") 1476 (+ opc1 opc2 arg1) 1477 (set (reg h-gr 13) (mem mode arg1)) 1478 ((fr30-1 (unit u-load))) 1479 ) 1480) 1481 1482(define-pmacro (dir2r13-postinc name insn opc1 opc2 mode arg1 incr) 1483 (dni name 1484 (.str insn " @" arg1 ",@R13+") 1485 (NOT-IN-DELAY-SLOT) 1486 (.str insn " @$" arg1 ",@$R13+") 1487 (+ opc1 opc2 arg1) 1488 (sequence () 1489 (set (mem mode (reg h-gr 13)) (mem mode arg1)) 1490 (set (reg h-gr 13) (add (reg h-gr 13) incr))) 1491 ((fr30-1 (unit u-load) (unit u-store))) 1492 ) 1493) 1494 1495(define-pmacro (r132dir name insn opc1 opc2 mode arg1) 1496 (dni name 1497 (.str insn " R13,@" arg1) 1498 () 1499 (.str insn " $R13,@$" arg1) 1500 (+ opc1 opc2 arg1) 1501 (set (mem mode arg1) (reg h-gr 13)) 1502 ((fr30-1 (unit u-store))) 1503 ) 1504) 1505 1506(define-pmacro (r13-postinc2dir name insn opc1 opc2 mode arg1 incr) 1507 (dni name 1508 (.str insn " @R13+,@" arg1) 1509 (NOT-IN-DELAY-SLOT) 1510 (.str insn " @$R13+,@$" arg1) 1511 (+ opc1 opc2 arg1) 1512 (sequence () 1513 (set (mem mode arg1) (mem mode (reg h-gr 13))) 1514 (set (reg h-gr 13) (add (reg h-gr 13) incr))) 1515 ((fr30-1 (unit u-load) (unit u-store))) 1516 ) 1517) 1518 1519; These versions which move from reg to mem must appear before the other 1520; versions which use immediate addresses due to a problem in cgen 1521; - DB. 1522(r132dir dmovr13 dmov OP1_1 OP2_8 WI dir10) 1523(r132dir dmovr13h dmovh OP1_1 OP2_9 HI dir9) 1524(r132dir dmovr13b dmovb OP1_1 OP2_A QI dir8) 1525 1526(r13-postinc2dir dmovr13pi dmov OP1_1 OP2_C WI dir10 (const 4)) 1527(r13-postinc2dir dmovr13pih dmovh OP1_1 OP2_D HI dir9 (const 2)) 1528(r13-postinc2dir dmovr13pib dmovb OP1_1 OP2_E QI dir8 (const 1)) 1529 1530(dni dmovr15pi 1531 "dmov @R15+,@dir10" 1532 (NOT-IN-DELAY-SLOT) 1533 "dmov @$R15+,@$dir10" 1534 (+ OP1_1 OP2_B dir10) 1535 (sequence () 1536 (set (mem WI dir10) (mem WI (reg h-gr 15))) 1537 (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))) 1538 ((fr30-1 (unit u-load) (unit u-store))) 1539) 1540; End of reordered insns. 1541 1542(dir2r13 dmov2r13 dmov OP1_0 OP2_8 WI dir10) 1543(dir2r13 dmov2r13h dmovh OP1_0 OP2_9 HI dir9) 1544(dir2r13 dmov2r13b dmovb OP1_0 OP2_A QI dir8) 1545 1546(dir2r13-postinc dmov2r13pi dmov OP1_0 OP2_C WI dir10 (const 4)) 1547(dir2r13-postinc dmov2r13pih dmovh OP1_0 OP2_D HI dir9 (const 2)) 1548(dir2r13-postinc dmov2r13pib dmovb OP1_0 OP2_E QI dir8 (const 1)) 1549 1550(dni dmov2r15pd 1551 "dmov @dir10,@-R15" 1552 (NOT-IN-DELAY-SLOT) 1553 "dmov @$dir10,@-$R15" 1554 (+ OP1_0 OP2_B dir10) 1555 (sequence () 1556 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) 1557 (set (mem WI (reg h-gr 15)) (mem WI dir10))) 1558 ((fr30-1 (unit u-load) (unit u-store))) 1559) 1560 1561; Leave these insns as stubs for now, except for the increment of $Ri 1562; 1563(dni ldres 1564 "ldres @Ri+,#u4" 1565 () 1566 "ldres @$Ri+,$u4" 1567 (+ OP1_B OP2_C u4 Ri) 1568 (set Ri (add Ri (const 4))) 1569 () 1570) 1571 1572(dni stres 1573 "stres #u4,@Ri+" 1574 () 1575 "stres $u4,@$Ri+" 1576 (+ OP1_B OP2_D u4 Ri) 1577 (set Ri (add Ri (const 4))) 1578 () 1579) 1580 1581; Leave the coprocessor insns as stubs for now. 1582; 1583(define-pmacro (cop-stub name insn opc1 opc2 opc3 arg1 arg2) 1584 (dni name 1585 (.str insn " u4c,ccc,CRj," arg1 "," arg2) 1586 (NOT-IN-DELAY-SLOT) 1587 (.str insn " $u4c,$ccc,$" arg1 ",$" arg2) 1588 (+ opc1 opc2 opc3 u4c ccc arg1 arg2) 1589 (nop) ; STUB 1590 () 1591 ) 1592) 1593 1594(cop-stub copop copop OP1_9 OP2_F OP3_C CRj CRi) 1595(cop-stub copld copld OP1_9 OP2_F OP3_D Rjc CRi) 1596(cop-stub copst copst OP1_9 OP2_F OP3_E CRj Ric) 1597(cop-stub copsv copsv OP1_9 OP2_F OP3_F CRj Ric) 1598 1599(dni nop 1600 "nop" 1601 () 1602 "nop" 1603 (+ OP1_9 OP2_F OP3_A OP4_0) 1604 (nop) 1605 () 1606) 1607 1608(dni andccr 1609 "andccr #u8" 1610 () 1611 "andccr $u8" 1612 (+ OP1_8 OP2_3 u8) 1613 (set ccr (and ccr u8)) 1614 () 1615) 1616 1617(dni orccr 1618 "orccr #u8" 1619 () 1620 "orccr $u8" 1621 (+ OP1_9 OP2_3 u8) 1622 (set ccr (or ccr u8)) 1623 () 1624) 1625 1626(dni stilm 1627 "stilm #u8" 1628 () 1629 "stilm $u8" 1630 (+ OP1_8 OP2_7 u8) 1631 (set ilm (and u8 (const #x1f))) 1632 () 1633) 1634 1635(dni addsp 1636 "addsp #s10" 1637 () 1638 "addsp $s10" 1639 (+ OP1_A OP2_3 s10) 1640 (set (reg h-gr 15) (add (reg h-gr 15) s10)) 1641 () 1642) 1643 1644(define-pmacro (ext-op name opc1 opc2 opc3 op mode mask) 1645 (dni name 1646 (.str name " Ri") 1647 () 1648 (.str name " $Ri") 1649 (+ opc1 opc2 opc3 Ri) 1650 (set Ri (op WI (and mode Ri mask))) 1651 () 1652 ) 1653) 1654 1655(ext-op extsb OP1_9 OP2_7 OP3_8 ext QI (const #xff)) 1656(ext-op extub OP1_9 OP2_7 OP3_9 zext UQI (const #xff)) 1657(ext-op extsh OP1_9 OP2_7 OP3_A ext HI (const #xffff)) 1658(ext-op extuh OP1_9 OP2_7 OP3_B zext UHI (const #xffff)) 1659 1660(dni ldm0 1661 "ldm0 (reglist_low_ld)" 1662 (NOT-IN-DELAY-SLOT) 1663 "ldm0 ($reglist_low_ld)" 1664 (+ OP1_8 OP2_C reglist_low_ld) 1665 (sequence () 1666 (if (and reglist_low_ld (const #x1)) 1667 (sequence () 1668 (set (reg h-gr 0) (mem WI (reg h-gr 15))) 1669 (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) 1670 (if (and reglist_low_ld (const #x2)) 1671 (sequence () 1672 (set (reg h-gr 1) (mem WI (reg h-gr 15))) 1673 (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) 1674 (if (and reglist_low_ld (const #x4)) 1675 (sequence () 1676 (set (reg h-gr 2) (mem WI (reg h-gr 15))) 1677 (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) 1678 (if (and reglist_low_ld (const #x8)) 1679 (sequence () 1680 (set (reg h-gr 3) (mem WI (reg h-gr 15))) 1681 (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) 1682 (if (and reglist_low_ld (const #x10)) 1683 (sequence () 1684 (set (reg h-gr 4) (mem WI (reg h-gr 15))) 1685 (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) 1686 (if (and reglist_low_ld (const #x20)) 1687 (sequence () 1688 (set (reg h-gr 5) (mem WI (reg h-gr 15))) 1689 (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) 1690 (if (and reglist_low_ld (const #x40)) 1691 (sequence () 1692 (set (reg h-gr 6) (mem WI (reg h-gr 15))) 1693 (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) 1694 (if (and reglist_low_ld (const #x80)) 1695 (sequence () 1696 (set (reg h-gr 7) (mem WI (reg h-gr 15))) 1697 (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) 1698 ) 1699 ((fr30-1 (unit u-ldm))) 1700) 1701 1702(dni ldm1 1703 "ldm1 (reglist_hi_ld)" 1704 (NOT-IN-DELAY-SLOT) 1705 "ldm1 ($reglist_hi_ld)" 1706 (+ OP1_8 OP2_D reglist_hi_ld) 1707 (sequence () 1708 (if (and reglist_hi_ld (const #x1)) 1709 (sequence () 1710 (set (reg h-gr 8) (mem WI (reg h-gr 15))) 1711 (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) 1712 (if (and reglist_hi_ld (const #x2)) 1713 (sequence () 1714 (set (reg h-gr 9) (mem WI (reg h-gr 15))) 1715 (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) 1716 (if (and reglist_hi_ld (const #x4)) 1717 (sequence () 1718 (set (reg h-gr 10) (mem WI (reg h-gr 15))) 1719 (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) 1720 (if (and reglist_hi_ld (const #x8)) 1721 (sequence () 1722 (set (reg h-gr 11) (mem WI (reg h-gr 15))) 1723 (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) 1724 (if (and reglist_hi_ld (const #x10)) 1725 (sequence () 1726 (set (reg h-gr 12) (mem WI (reg h-gr 15))) 1727 (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) 1728 (if (and reglist_hi_ld (const #x20)) 1729 (sequence () 1730 (set (reg h-gr 13) (mem WI (reg h-gr 15))) 1731 (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) 1732 (if (and reglist_hi_ld (const #x40)) 1733 (sequence () 1734 (set (reg h-gr 14) (mem WI (reg h-gr 15))) 1735 (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) 1736 (if (and reglist_hi_ld (const #x80)) 1737 (set (reg h-gr 15) (mem WI (reg h-gr 15)))) 1738 ) 1739 ((fr30-1 (unit u-ldm))) 1740) 1741 1742(dni stm0 1743 "stm0 (reglist_low_st)" 1744 (NOT-IN-DELAY-SLOT) 1745 "stm0 ($reglist_low_st)" 1746 (+ OP1_8 OP2_E reglist_low_st) 1747 (sequence () 1748 (if (and reglist_low_st (const #x1)) 1749 (sequence () 1750 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) 1751 (set (mem WI (reg h-gr 15)) (reg h-gr 7)))) 1752 (if (and reglist_low_st (const #x2)) 1753 (sequence () 1754 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) 1755 (set (mem WI (reg h-gr 15)) (reg h-gr 6)))) 1756 (if (and reglist_low_st (const #x4)) 1757 (sequence () 1758 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) 1759 (set (mem WI (reg h-gr 15)) (reg h-gr 5)))) 1760 (if (and reglist_low_st (const #x8)) 1761 (sequence () 1762 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) 1763 (set (mem WI (reg h-gr 15)) (reg h-gr 4)))) 1764 (if (and reglist_low_st (const #x10)) 1765 (sequence () 1766 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) 1767 (set (mem WI (reg h-gr 15)) (reg h-gr 3)))) 1768 (if (and reglist_low_st (const #x20)) 1769 (sequence () 1770 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) 1771 (set (mem WI (reg h-gr 15)) (reg h-gr 2)))) 1772 (if (and reglist_low_st (const #x40)) 1773 (sequence () 1774 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) 1775 (set (mem WI (reg h-gr 15)) (reg h-gr 1)))) 1776 (if (and reglist_low_st (const #x80)) 1777 (sequence () 1778 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) 1779 (set (mem WI (reg h-gr 15)) (reg h-gr 0)))) 1780 ) 1781 ((fr30-1 (unit u-stm))) 1782) 1783 1784(dni stm1 1785 "stm1 (reglist_hi_st)" 1786 (NOT-IN-DELAY-SLOT) 1787 "stm1 ($reglist_hi_st)" 1788 (+ OP1_8 OP2_F reglist_hi_st) 1789 (sequence () 1790 (if (and reglist_hi_st (const #x1)) 1791 (sequence ((WI save-r15)) 1792 (set save-r15 (reg h-gr 15)) 1793 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) 1794 (set (mem WI (reg h-gr 15)) save-r15))) 1795 (if (and reglist_hi_st (const #x2)) 1796 (sequence () 1797 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) 1798 (set (mem WI (reg h-gr 15)) (reg h-gr 14)))) 1799 (if (and reglist_hi_st (const #x4)) 1800 (sequence () 1801 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) 1802 (set (mem WI (reg h-gr 15)) (reg h-gr 13)))) 1803 (if (and reglist_hi_st (const #x8)) 1804 (sequence () 1805 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) 1806 (set (mem WI (reg h-gr 15)) (reg h-gr 12)))) 1807 (if (and reglist_hi_st (const #x10)) 1808 (sequence () 1809 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) 1810 (set (mem WI (reg h-gr 15)) (reg h-gr 11)))) 1811 (if (and reglist_hi_st (const #x20)) 1812 (sequence () 1813 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) 1814 (set (mem WI (reg h-gr 15)) (reg h-gr 10)))) 1815 (if (and reglist_hi_st (const #x40)) 1816 (sequence () 1817 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) 1818 (set (mem WI (reg h-gr 15)) (reg h-gr 9)))) 1819 (if (and reglist_hi_st (const #x80)) 1820 (sequence () 1821 (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) 1822 (set (mem WI (reg h-gr 15)) (reg h-gr 8)))) 1823 ) 1824 ((fr30-1 (unit u-stm))) 1825) 1826 1827(dni enter 1828 "enter #u10" 1829 (NOT-IN-DELAY-SLOT) 1830 "enter $u10" 1831 (+ OP1_0 OP2_F u10) 1832 (sequence ((WI tmp)) 1833 (set tmp (sub (reg h-gr 15) (const 4))) 1834 (set (mem WI tmp) (reg h-gr 14)) 1835 (set (reg h-gr 14) tmp) 1836 (set (reg h-gr 15) (sub (reg h-gr 15) u10))) 1837 ((fr30-1 (unit u-exec (cycles 2)))) 1838) 1839 1840(dni leave 1841 "leave" 1842 () 1843 "leave" 1844 (+ OP1_9 OP2_F OP3_9 OP4_0) 1845 (sequence () 1846 (set (reg h-gr 15) (add (reg h-gr 14) (const 4))) 1847 (set (reg h-gr 14) (mem WI (sub (reg h-gr 15) (const 4))))) 1848 () 1849) 1850 1851(dni xchb 1852 "xchb @Rj,Ri" 1853 (NOT-IN-DELAY-SLOT) 1854 "xchb @$Rj,$Ri" 1855 (+ OP1_8 OP2_A Rj Ri) 1856 (sequence ((WI tmp)) 1857 (set tmp Ri) 1858 (set Ri (mem UQI Rj)) 1859 (set (mem UQI Rj) tmp)) 1860 ((fr30-1 (unit u-load) (unit u-store))) 1861) 1862