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/toolchain/binutils/binutils-2.25/opcodes/
Ds390-opc.txt83 b229 iske RRE_RR "insert storage key extended" g5 esa,zarch
87 51 lae RX_RRRD "load address extended" g5 esa,zarch
162 b22a rrbe RRE_RR "reset reference bit extended" g5 esa,zarch
201 b22b sske RRE_RR "set storage key extended" g5 esa,zarch
255 a9 clcle RS_RRRD "compare logical long extended" g5 esa,zarch
257 a8 mvcle RS_RERERD "move long extended" g5 esa,zarch
273 b34a axbr RRE_FEFE "add extended bfp" g5 esa,zarch
278 b349 cxbr RRE_FEFE "compare extended bfp" g5 esa,zarch
283 b348 kxbr RRE_FF "compare and signal extended bfp" g5 esa,zarch
288 b396 cxfbr RRE_FER "convert from fixed 32 to extended bfp" g5 esa,zarch
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/
Dx86-64-opcode.s83 IDIVb (%r8) # -- -- -- 41 F6 38 ; Sign extended result. REX to access upper reg.
84 IDIVb (%rax) # -- -- -- -- F6 38 ; Sign extended result
85 …IDIVw (%r8) # 66 -- -- 41 F7 38 ; Sign extended result. REX to access upper reg. O1…
86 IDIVw (%rax) # 66 -- -- -- F7 38 ; Sign extended result. O16 for 16-bit operand size
87 IDIVl (%r8) # -- -- -- 41 F7 38 ; Sign extended result. REX to access upper reg
88 IDIVl (%rax) # -- -- -- -- F7 38 ; Sign extended result
89 …IDIVq (%r8) # -- -- -- 49 F7 38 ; Sign extended result. REX for 64-bit operand size…
90 IDIVq (%rax) # -- -- -- 48 F7 38 ; Sign extended result. REX for 64-bit operand size
93 IMULb (%r8) # -- -- -- 41 F6 28 ; Sign extended result. REX to access upper reg
94 IMULb (%rax) # -- -- -- -- F6 28 ; Sign extended result
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/toolchain/binutils/binutils-2.25/gas/doc/
Dc-pdp11.texi87 Enable (or disable) the use of the extended instruction set, which
121 Enable (or disable) the use of the limited extended instruction set:
165 KB11 CPU. Enable extended instruction set and @code{SPL}.
169 KD11-A CPU. Enable limited extended instruction set.
181 KD11-E CPU. Enable extended instruction set, @code{MFPS}, and @code{MTPS}.
187 KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended instruction set,
192 KD11-K CPU. Enable extended instruction set, @code{LDUB}, @code{MED},
197 KD11-Z CPU. Enable extended instruction set, @code{CSM}, @code{MFPS},
202 F11 CPU. Enable extended instruction set, @code{MFPS}, @code{MFPT}, and
207 J11 CPU. Enable extended instruction set, @code{CSM}, @code{MFPS},
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Dc-ip2k.texi34 @code{@value{AS}} can assemble the extended IP2022 instructions, but
43 permitting the extended IP2022 instructions to be assembled.
Dc-tilepro.texi163 sign-extended to a 32-bit value (sign-extension allows it to be
170 address, also sign-extended to a 32-bit value.
192 This modifier is used to load the sign-extended low 16 bits of the
197 This modifier is used to load the sign-extended high 16 bits of the
225 This modifier is used to load the sign-extended low 16 bits of the
231 This modifier is used to load the sign-extended high 16 bits of the
Dc-i960.texi138 @samp{.float}, @samp{.double}, @samp{.extended}, and @samp{.single}.
157 @cindex @code{extended} directive, i960
158 @item .extended @var{flonums}
159 @code{.extended} expects zero or more flonums, separated by commas; for
160 each flonum, @samp{.extended} emits an @sc{ieee} extended-format (80-bit)
Dc-ns32k.texi25 32x32 understands extended precision numbers.
Dc-tic54x.texi40 You can use the @samp{-mfar-mode} option to enable extended addressing mode.
308 The @code{LDX} pseudo-op is provided for loading the extended addressing bits
310 in extended program memory, the value of @code{_label} may be loaded as
313 ldx #_label,16,a ; loads extended bits of _label
425 Use extended addressing when assembling statements. This should appear
/toolchain/binutils/binutils-2.25/gas/config/
Dtc-msp430.c1813 int extended = 0x1800; in msp430_operands() local
1942 extended |= (repeat_count - 1); in msp430_operands()
1944 extended |= (1 << 7) | (- repeat_count); in msp430_operands()
1990 extended |= BYTE_OPERATION; in msp430_operands()
1995 bfd_putl16 (extended, frag); in msp430_operands()
2047 extended |= BYTE_OPERATION; in msp430_operands()
2049 if (op1.ol != 0 && ((extended & 0xf) != 0)) in msp430_operands()
2052 extended &= ~ 0xf; in msp430_operands()
2058 extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7; in msp430_operands()
2069 bfd_putl16 (extended, frag); in msp430_operands()
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/tic54x/
Dextaddr.s8 ldx #F1,16,a ; load upper 8 bits of extended address
11 ; extended addressing functions
Daddrfar.d3 #name: c54x addressing modes, w/extended addressing (far mode)
Dextaddr.d2 #name: c54x extended addressing
Dconsfar.d3 #name: c54x cons tests, w/extended addressing
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/sh/
Dsign-extension.d3 #name: Sign-extended immediate
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/s390/
Desa-z9-109.s7 # z9-109 z/Architecture mode extended sske with an additional parameter
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/
Dmips16e-save.s6 # Un-extended version
/toolchain/binutils/binutils-2.25/cpu/
Dmep-c5.cpu25 (dnf f-c5n4 "extended field" (all-mep-core-isas) 16 4)
26 (dnf f-c5n5 "extended field" (all-mep-core-isas) 20 4)
27 (dnf f-c5n6 "extended field" (all-mep-core-isas) 24 4)
28 (dnf f-c5n7 "extended field" (all-mep-core-isas) 28 4)
30 (df f-12s20 "extended field" (all-mep-core-isas) 20 12 INT #f #f)
Dsh64-media.cpu211 (dshmi addzl "Add zero extended long"
507 (dshmi fldxd "Floating point extended load (double)"
513 (dshmi fldxp "Floating point extended load (pair of singles)"
522 (dshmi fldxs "Floating point extended load (single)"
659 (dshmi fstxd "Floating point extended store (double)"
665 (dshmi fstxp "Floating point extended store (pair of singles)"
674 (dshmi fstxs "Floating point extended store (single)"
810 (dshmi ldxb "Load byte (extended displacement)"
816 (dshmi ldxl "Load long word (extended displacement)"
822 (dshmi ldxq "Load quad word (extended displacement)"
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Dxc16x.cpu147 (dnf f-extccode "extended condcode" () 15 5) ;condition code required in other jmpa and calla
326 (comment "extended condition codes")
581 (dnop extcond "extended condition code" () h-ecc f-extccode)
2445 ;extended register sequence
2447 (dni extr "begin extended register sequence"
2465 ;extended page sequence
2467 (dni extp "begin extended page sequence"
2485 ;extended page sequence
2487 (dni extp1 "begin extended page sequence"
2506 (dni extpg1 "begin extended page sequence"
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Dcris.cpu1103 (dsh h-xbit "extended-arithmetic bit" () (register BI))
1340 ;The 6-bit value may be sign or zero extended depending on the instruction.
2428 cmps-m "cmp sign-extended from memory to register"
2440 cmpscbr "cmp sign-extended constant byte to register"
2448 cmpscwr "cmp sign-extended constant word to register"
2459 cmpu-m "cmp zero-extended from memory to register"
2471 cmpucbr "cmp zero-extended constant byte to register"
2479 cmpucwr "cmp zero-extended constant word to register"
3073 adds "add sign-extended from register to register"
3082 adds-m "add sign-extended from memory to register"
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/toolchain/binutils/binutils-2.25/ld/testsuite/ld-m68hc11/
Drelax-direct.s1 ;;; Test 68HC11 linker relaxation from extended addressing to direct
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/m68hc11/
D9s12x-exg-sex-tfr.d3 #name: s12x extended forms of exg,tfr,sex
D9s12x-mov.s5 ;; Test all s12x extended forms of movb, movw
D9s12x-mov.d3 #name: s12x extended forms of movb,movw
D9s12x-exg-sex-tfr.s5 ;; Test all s12x extended forms of exg,tfr,sex where supported

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