1; Infineon XC16X CPU description. -*- Scheme -*- 2; 3; Copyright 2006, 2007, 2009 Free Software Foundation, Inc. 4; 5; Contributed by KPIT Cummins Infosystems Ltd.; developed under contract 6; from Infineon Systems, GMBH , Germany. 7; 8; This file is part of the GNU Binutils. 9; 10; This program is free software; you can redistribute it and/or modify 11; it under the terms of the GNU General Public License as published by 12; the Free Software Foundation; either version 3 of the License, or 13; (at your option) any later version. 14; 15; This program is distributed in the hope that it will be useful, 16; but WITHOUT ANY WARRANTY; without even the implied warranty of 17; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18; GNU General Public License for more details. 19; 20; You should have received a copy of the GNU General Public License 21; along with this program; if not, write to the Free Software 22; Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 23; 02110-1301, USA. 24 25(define-rtl-version 0 8) 26 27(include "simplify.inc") 28 29; define-arch appears first 30 31(define-arch 32 (name xc16x) ; name of cpu family 33 (comment "Infineon XC16X") 34 (default-alignment aligned) 35 (insn-lsb0? #t) 36 (machs xc16x) 37 (isas xc16x) 38) 39 40; Attributes. 41; An attribute to describe which pipeline an insn runs in generally OS. 42(define-attr 43 (for insn) 44 (type enum) 45 (name PIPE) 46 (comment "parallel execution pipeline selection") 47 (values NONE OS) 48) 49 50; Instruction set parameters. 51 52(define-isa 53 (name xc16x) 54 (default-insn-bitsize 32) 55 (base-insn-bitsize 32) 56 (default-insn-word-bitsize 16) 57 (decode-assist (15 14 13 12)) 58 ; The XC16X fetches 1 insn at a time. 59 (liw-insns 1) 60 (parallel-insns 1) 61) 62 63; Cpu family definitions. 64 65(define-cpu 66 ; cpu names must be distinct from the architecture name and machine names. 67 ; The "b" suffix stands for "base" and is the convention. 68 ; The "f" suffix stands for "family" and is the convention. 69 (name xc16xbf) 70 (comment "Infineon XC16X base family") 71 (endian little) 72 (insn-chunk-bitsize 32) 73 (word-bitsize 16) 74 (parallel-insns 1) 75) 76 77(define-mach 78 (name xc16x) 79 (comment "Infineon XC16X cpu") 80 (cpu xc16xbf) 81) 82 83; Model descriptions. 84 85(define-model 86 (name xc16x) (comment "XC16X") (attrs) 87 (mach xc16x) 88 89 (pipeline p-mem "" () ((prefetch) (fetch) (decode) (address) (memory) (execute) (writeback))) 90 91 ; `state' is a list of variables for recording model state 92 (state 93 ; bit mask of h-gr registers, =1 means value being loaded from memory 94 (h-gr UINT) 95 ) 96 97 (unit u-exec "Execution Unit" () 98 1 1 ; issue done 99 () ; state 100 ((dr INT -1) (sr INT -1)) ; inputs 101 ((dr INT -1)) ; outputs 102 () ; profile action (default) 103 ) 104 (unit u-cmp "Compare Unit" () 105 1 1 ; issue done 106 () ; state 107 ((src1 INT -1) (src2 INT -1)) ; inputs 108 () ; outputs 109 () ; profile action (default) 110 ) 111 (unit u-cti "Jump & Call Unit" () 112 1 1 ; issue done 113 () ; state 114 ((condbit) (sr INT -1)) ; inputs 115 ((pc)) ; outputs 116 () ; profile action (default) 117 ) 118 (unit u-mov "Data Movement Unit" () 119 1 1 ; issue done 120 () ;state 121 ((dr INT -1) (sr INT -1)) ; inputs 122 ((dr INT -1)) ; output 123 () ; profile action (default) 124 ) 125 ) 126 127; Instruction fields. 128; 129; Attributes: 130; PCREL-ADDR: pc relative value (for reloc and disassembly purposes) 131; ABS-ADDR: absolute address (for reloc and disassembly purposes) 132; RELOC: there is a relocation associated with this field (experiment) 133 134(define-attr 135 (for ifield operand) 136 (type boolean) 137 (name RELOC) 138 (comment "there is a reloc associated with this field (experiment)") 139) 140 141(dnf f-op1 "op1" () 7 4) 142(dnf f-op2 "op2" () 3 4) 143(dnf f-condcode "condcode" () 7 4) ;condition code required in other jmps and calls 144(dnf f-icondcode "indrct condcode" () 15 4) ;condition code required in other jmpi and calli 145(dnf f-rcond "relative-cond" () 7 4) ;condition code required in JMPR 146(dnf f-qcond "qbit" () 7 4) ;used in enum of bset/bclear macro 147(dnf f-extccode "extended condcode" () 15 5) ;condition code required in other jmpa and calla 148(dnf f-r0 "r0" () 9 2) ;required where 2 bit register used(only R0-R3) 149(dnf f-r1 "r1" () 15 4) 150(dnf f-r2 "r2" () 11 4) 151(dnf f-r3 "r3" () 12 4) 152(dnf f-r4 "r4" () 11 4) 153(dnf f-uimm2 "uimm2" () 13 2) ;used for immediate data,eg in ADD,MOV insns 154(dnf f-uimm3 "uimm3" () 10 3) ;used for immediate data,eg in ADD,SUB insns 155(dnf f-uimm4 "uimm4" () 15 4) ;used for immediate data,eg in MOV insns 156(dnf f-uimm7 "uimm7" (PCREL-ADDR RELOC) 15 7) ;used in TRAP 157(dnf f-uimm8 "uimm8" () 23 8) ;used in immediate byte data,eg in ADDB,MOVB insns 158(dnf f-uimm16 "uimm16" () 31 16) ;used for immediate word data 159(dnf f-memory "memory" () 31 16) ; used for memory operands 160(dnf f-memgr8 "memory" () 31 16) ; memory location of gr 161(dnf f-rel8 "rel8" (PCREL-ADDR RELOC) 15 8) ;used in JMPR,CALLR 162(dnf f-relhi8 "relhi8" (PCREL-ADDR RELOC) 23 8) ;used in JB,JBC,JNB,JNBS 163(dnf f-reg8 "reg8" () 15 8) ;required where 8bit gp register used 164(dnf f-regmem8 "regmem8" () 15 8) ;required where 8bit register used 165(dnf f-regoff8 "regoff8" () 15 8) ;required for offset calc 166(dnf f-reghi8 "reghi8" () 23 8) ;required where 8bit register number used 167(dnf f-regb8 "regb8" () 15 8) ;required for byte registers RL0,RH0, till RL8,RH8 168(dnf f-seg8 "seg8" () 15 8) ;used as segment number in JMPS,CALLS 169(dnf f-segnum8 "segnum8" () 23 8) ;used in EXTS,EXTSR 170(dnf f-mask8 "mask8" () 23 8) ;used as mask in BFLDH,BFLDL insns 171(dnf f-pagenum "page num" () 25 10);used in EXTP,EXTPR 172(dnf f-datahi8 "datahi8" () 31 8) ;used for filling with const data 173(dnf f-data8 "data8" () 23 8) ;used for filling with const data 174(dnf f-offset16 "address offset16" (ABS-ADDR RELOC) 31 16) ;used in JMPS,JMPA,CALLA,CALLS 175(dnf f-op-bit1 "gap of 1 bit" () 11 1) ;used for filling with const data 176(dnf f-op-bit2 "gap of 2 bits" () 11 2) ;used for filling with const data 177(dnf f-op-bit4 "gap of 4 bits" () 11 4) ;used for filling with const data 178(dnf f-op-bit3 "gap of 3 bits" () 10 3) ;used in CALLA, JMPA 179(dnf f-op-2bit "gap of 2 bits" () 10 2) ;used in CALLA 180(dnf f-op-bitone "gap of 1 bit " () 10 1) ;used in JMPA 181(dnf f-op-onebit "gap of 1 bit " () 9 1) ;used in JMPA 182(dnf f-op-1bit "gap of 1 bit " () 8 1) ;used in JMPA, CALLA 183(dnf f-op-lbit4 "gap of 4 bits" () 15 4) ;used for filling with const data 184(dnf f-op-lbit2 "gap of 2 bits" () 15 2) ;used for filling with const data 185(dnf f-op-bit8 "gap of 8 bits" () 31 8) ;used for filling with const data 186(dnf f-op-bit16 "gap of 16 bits" () 31 16) ;used for filling with const data 187(dnf f-qbit "qbit" () 7 4) ;used in bit field of bset/bclear 188(dnf f-qlobit "qlobit" () 31 4) ;used for filling with const data 189(dnf f-qhibit "qhibit" () 27 4) ;used for filling with const data 190(dnf f-qlobit2 "qlobit2" () 27 2) ;used for filling with const data 191(dnf f-pof "upof16" () 31 16) ; used for memory operands 192 193; Enums. 194; insn-op1: bits 0-3 195(define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1 196 ("0" "1" "2" "3" "4" "5" "6" "7" 197 "8" "9" "10" "11" "12" "13" "14" "15") 198) 199 200; insn-op2: bits 4-7 201(define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2 202 ("0" "1" "2" "3" "4" "5" "6" "7" 203 "8" "9" "10" "11" "12" "13" "14" "15") 204) 205 206;/*for bclr/bset*/ 207; insn-rcond: bits 0-3 208(define-normal-insn-enum insn-qcond "bit set/clear enums" () QBIT_ f-qcond 209 (("0" 0) ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) 210 ("11" 11) ("12" 12) ("13" 13) ("14" 14) ("15" 15)) 211) 212;/************/ 213; insn-rcond: bits 0-3 214(define-normal-insn-enum insn-rcond "relative jump condition code op2 enums" () COND_ f-rcond 215 (("UC" 0) ("NET" 1) ("Z" 2) ("NE_NZ" 3) ("V" 4) ("NV" 5) ("N" 6) ("NN" 7) 216 ("C" 8) ("NC" 9) ("SGT" 10) ("SLE" 11) ("SLT" 12) ("SGE" 13) ("UGT" 14) ("ULE" 15) 217 ("EQ" 2) ("NE" 3) ("ULT" 8) ("UGE" 9)) 218) 219 220 221 222; Hardware pieces. 223; These entries list the elements of the raw hardware. 224; They're also used to provide tables and other elements of the assembly 225; language. 226 227(dnh h-pc "program counter" (PC) (pc) () () ()) 228 229(define-keyword 230 (name gr-names) 231 (enum-prefix H-GR-) 232 (values (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7) 233 (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15)) 234 235) 236(define-hardware 237 (name h-gr) 238 (comment "general registers") 239 (attrs PROFILE CACHE-ADDR) 240 (type register HI (16)) 241 (indices extern-keyword gr-names) 242) 243 244;; HACK: Various semantics refer to h-cr. 245;; This is here to keep things working. 246(define-hardware 247 (name h-cr) 248 (comment "cr registers") 249 (attrs PROFILE CACHE-ADDR) 250 (type register HI (16)) 251 (indices extern-keyword gr-names) 252) 253 254(define-keyword 255 (name ext-names) 256 (enum-prefix H-EXT-) 257 (values (0x1 0) (0x2 1) (0x3 2) (0x4 3) 258 ("1" 0) ("2" 1) ("3" 2) ("4" 3)) 259 260) 261 262(define-hardware 263 (name h-ext) 264 (comment "ext values") 265 (attrs PROFILE CACHE-ADDR) 266 (type register HI (8)) 267 (indices extern-keyword ext-names) 268) 269 270(define-keyword 271 (name psw-names) 272 (enum-prefix H-PSW-) 273 (values ("IEN" 136) ("r0.11" 240) ("r1.11" 241) ("r2.11" 242) ("r3.11" 243) ("r4.11" 244) 274 ("r5.11" 245) ("r6.11" 246) ("r7.11" 247) ("r8.11" 248) 275 ("r9.11" 249) ("r10.11" 250) ("r11.11" 251) ("r12.11" 252) 276 ("r13.11" 253) ("r14.11" 254) ("r15.11" 255)) 277) 278 279(define-hardware 280 (name h-psw) 281 (comment "ext values") 282 (attrs PROFILE CACHE-ADDR) 283 (type register HI (1)) 284 (indices extern-keyword psw-names) 285) 286 287(define-keyword 288 (name grb-names) 289 (enum-prefix H-GRB-) 290 (values (rl0 0) (rh0 1) (rl1 2) (rh1 3) (rl2 4) (rh2 5) (rl3 6) (rh3 7) 291 (rl4 8) (rh4 9) (rl5 10) (rh5 11) (rl6 12) (rh6 13) (rl7 14) (rh7 15)) 292) 293 294(define-hardware 295 (name h-grb) 296 (comment "general registers") 297 (attrs PROFILE CACHE-ADDR) 298 (type register QI (16)) 299 (indices extern-keyword grb-names) 300) 301 302(define-keyword 303 (name conditioncode-names) 304 (enum-prefix H-CC-) 305 (values (cc_UC 0) (cc_NET 1) (cc_Z 2) (cc_EQ 2) (cc_NZ 3) (cc_NE 3) (cc_V 4) (cc_NV 5) (cc_N 6) (cc_NN 7) (cc_ULT 8) (cc_UGE 9) 306 (cc_C 8) (cc_NC 9) (cc_SGT 10) (cc_SLE 11) (cc_SLT 12) (cc_SGE 13) (cc_UGT 14) 307 (cc_ULE 15)) 308) 309(define-hardware 310 (name h-cc) 311 (comment "condition codes") 312 (attrs PROFILE CACHE-ADDR) 313 (type register QI (16)) 314 (indices extern-keyword conditioncode-names) 315) 316 317(define-keyword 318 (name extconditioncode-names) 319 (enum-prefix H-ECC-) 320 (values(cc_UC 0) (cc_NET 2) (cc_Z 4) (cc_EQ 4) (cc_NZ 6) (cc_NE 6) (cc_V 8) (cc_NV 10) (cc_N 12) (cc_NN 14) (cc_ULT 16) (cc_UGE 18) (cc_C 16) (cc_NC 18) (cc_SGT 20) 321 (cc_SLE 22) (cc_SLT 24) (cc_SGE 26) (cc_UGT 28) (cc_ULE 30) (cc_nusr0 1) 322 (cc_nusr1 3) (cc_usr0 5) (cc_usr1 7)) 323) 324(define-hardware 325 (name h-ecc) 326 (comment "extended condition codes") 327 (attrs PROFILE CACHE-ADDR) 328 (type register QI (4)) 329 (indices extern-keyword extconditioncode-names) 330) 331 332(define-keyword 333 (name grb8-names) 334 (enum-prefix H-GRB8-) 335 (values (dpp0 0) (dpp1 1) (dpp2 2) (dpp3 3) 336 (psw 136) (cp 8) (mdl 7) (mdh 6) 337 (mdc 135) (sp 9) (csp 4) (vecseg 137) 338 (stkov 10) (stkun 11) (cpucon1 12) (cpucon2 13) 339 (zeros 142) (ones 143) (spseg 134) (tfr 214) 340 (rl0 240) (rh0 241) (rl1 242) (rh1 243) (rl2 244) (rh2 245) (rl3 246) (rh3 247) 341 (rl4 248) (rh4 249) (rl5 250) (rh5 251) (rl6 252) (rh6 253) (rl7 254) (rh7 255)) 342) 343 344(define-hardware 345 (name h-grb8) 346 (comment "general byte registers") 347 (attrs PROFILE CACHE-ADDR) 348 (type register QI (36)) 349 (indices extern-keyword grb8-names) 350) 351 352(define-keyword 353 (name r8-names) 354 (enum-prefix H-R8-) 355 (values (dpp0 0) (dpp1 1) (dpp2 2) (dpp3 3) 356 (psw 136) (cp 8) (mdl 7) (mdh 6) 357 (mdc 135) (sp 9) (csp 4) (vecseg 137) 358 (stkov 10) (stkun 11) (cpucon1 12) (cpucon2 13) 359 (zeros 142) (ones 143) (spseg 134) (tfr 214) 360 (r0 240) (r1 241) (r2 242) (r3 243) (r4 244) (r5 245) (r6 246) (r7 247) 361 (r8 248) (r9 249) (r10 250) (r11 251) (r12 252) (r13 253) (r14 254) (r15 255)) 362) 363 364(define-hardware 365 (name h-r8) 366 (comment "registers") 367 (attrs PROFILE CACHE-ADDR) 368 (type register HI (36)) 369 (indices extern-keyword r8-names) 370) 371 372(define-keyword 373 (name regmem8-names) 374 (enum-prefix H-REGMEM8-) 375 (values (dpp0 0) (dpp1 1) (dpp2 2) (dpp3 3) 376 (psw 136) (cp 8) (mdl 7) (mdh 6) 377 (mdc 135) (sp 9) (csp 4) (vecseg 137) 378 (stkov 10) (stkun 11) (cpucon1 12) (cpucon2 13) 379 (zeros 142) (ones 143) (spseg 134) (tfr 214) 380 (r0 240) (r1 241) (r2 242) (r3 243) (r4 244) (r5 245) (r6 246) (r7 247) 381 (r8 248) (r9 249) (r10 250) (r11 251) (r12 252) (r13 253) (r14 254) (r15 255)) 382) 383 384(define-hardware 385 (name h-regmem8) 386 (comment "registers") 387 (attrs ) 388 (type register HI (16)) 389 (indices extern-keyword regmem8-names) 390) 391 392(define-keyword 393 (name regdiv8-names) 394 (enum-prefix H-REGDIV8-) 395 (values (r0 0) (r1 17) (r2 34) (r3 51) (r4 68) (r5 85) (r6 102) (r7 119) 396 (r8 136) (r9 153) (r10 170) (r11 187) (r12 204) (r13 221) (r14 238) (r15 255)) 397) 398 399(define-hardware 400 (name h-regdiv8) 401 (comment "division insn registers") 402 (attrs PROFILE CACHE-ADDR) 403 (type register HI (16)) 404 (indices extern-keyword regdiv8-names) 405) 406 407(define-keyword 408 (name reg0-name) 409 (enum-prefix H-REG0-) 410 (values (0x1 1) (0x2 2) (0x3 3) (0x4 4) (0x5 5) (0x6 6) (0x7 7) (0x8 8) (0x9 9) (0xa 10) (0xb 11) 411 (0xc 12) (0xd 13) (0xe 14) (0xf 15) 412 ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) ("11" 11) 413 ("12" 12) ("13" 13) ("14" 14) ("15" 15)) 414) 415 416(define-hardware 417 (name h-r0) 418 (comment "for 4-bit data excuding 0") 419 (attrs PROFILE CACHE-ADDR) 420 (type register HI (30)) 421 (indices extern-keyword reg0-name) 422) 423 424(define-keyword 425 (name reg0-name1) 426 (enum-prefix H-REG01-) 427 (values (0x1 1) (0x2 2) (0x3 3) (0x4 4) (0x5 5) (0x6 6) (0x7 7) 428 ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7)) 429) 430 431(define-hardware 432 (name h-r01) 433 (comment "for 4-bit data excuding 0") 434 (attrs PROFILE CACHE-ADDR) 435 (type register HI (14)) 436 (indices extern-keyword reg0-name1) 437) 438 439(define-keyword 440 (name regbmem8-names) 441 (enum-prefix H-REGBMEM8-) 442 (values (dpp0 0) (dpp1 1) (dpp2 2) (dpp3 3) 443 (psw 136) (cp 8) (mdl 7) (mdh 6) 444 (mdc 135) (sp 9) (csp 4) (vecseg 137) 445 (stkov 10) (stkun 11) (cpucon1 12) (cpucon2 13) 446 (zeros 142) (ones 143) (spseg 134) (tfr 214) 447 (rl0 240) (rh0 241) (rl1 242) (rh1 243) (rl2 244) (rh2 245) (rl3 246) (rh3 247) 448 (rl4 248) (rh4 249) (rl5 250) (rh5 251) (rl6 252) (rh6 253) (rl7 254) (rh7 255)) 449) 450 451(define-hardware 452 (name h-regbmem8) 453 (comment "registers") 454 (attrs PROFILE CACHE-ADDR) 455 (type register HI (36)) 456 (indices extern-keyword regbmem8-names) 457) 458 459(define-keyword 460 (name memgr8-names) 461 (enum-prefix H-MEMGR8-) 462 (values (dpp0 65024) (dpp1 65026) (dpp2 65028) (dpp3 65030) 463 (psw 65296) (cp 65040) (mdl 65038) (mdh 65036) 464 (mdc 65294) (sp 65042) (csp 65032) (vecseg 65298) 465 (stkov 65044) (stkun 65046) (cpucon1 65048) (cpucon2 65050) 466 (zeros 65308) (ones 65310) (spseg 65292) (tfr 65452) ) 467) 468 469(define-hardware 470 (name h-memgr8) 471 (comment "memory location of registers") 472 (attrs ) 473 (type register HI (20)) 474 (indices extern-keyword memgr8-names) 475) 476 477(dsh h-cond "condition bit" () (register BI)) ;any bit from PSW while comparison 478; This bit is part of the PSW register 479(dsh h-cbit "carry bit" () (register BI)) 480 481(dsh h-sgtdis "segmentation enable bit" () (register BI)) ;0 means segmentation enabled 482 483;Instruction operands 484; -- layer between the assembler and the raw hardware description 485; -- the main means of manipulating instruction fields in the semantic code 486 487; XC16X specific operand attributes: 488 489(define-attr 490 (for operand) 491 (type boolean) 492 (name HASH-PREFIX) 493 (comment "immediates have an optional '#' prefix") 494) 495 496(define-attr 497 (for operand) 498 (type boolean) 499 (name DOT-PREFIX) 500 (comment "bit addr have an optional '.' prefix") 501) 502 503(define-attr 504 (for operand) 505 (type boolean) 506 (name POF-PREFIX) 507 (comment "page offset ") 508) 509 510(define-attr 511 (for operand) 512 (type boolean) 513 (name PAG-PREFIX) 514 (comment "page ") 515) 516 517(define-attr 518 (for operand) 519 (type boolean) 520 (name SOF-PREFIX) 521 (comment "segment offset selection") 522) 523 524(define-attr 525 (for operand) 526 (type boolean) 527 (name SEG-PREFIX) 528 (comment "segment") 529) 530 531;; Define an operand that takes a set of handlers. 532;; dowh: define-operand-with-handlers 533(define-pmacro (dowh x-name x-comment x-attrs x-type x-index x-handlers) 534 (define-operand (name x-name) (comment x-comment) 535 (.splice attrs (.unsplice x-attrs)) 536 (type x-type) (index x-index) 537 (.splice handlers (.unsplice x-handlers))) 538) 539 540(dnop sr "source register" () h-gr f-r2) 541(dnop dr "destination register" () h-gr f-r1) 542(dnop dri "destination register" () h-gr f-r4) 543(dnop srb "source register" () h-grb f-r2) 544(dnop drb "destination register" () h-grb f-r1) 545(dnop sr2 "2 bit source register" () h-gr f-r0) 546(dnop src1 "source register 1" () h-gr f-r1) 547(dnop src2 "source register 2" () h-gr f-r2) 548(dnop srdiv "source register 2" () h-regdiv8 f-reg8) 549(dnop RegNam "PSW bits" () h-psw f-reg8) 550(dnop uimm2 "2 bit unsigned number" (HASH-PREFIX) h-ext f-uimm2) 551(dnop uimm3 "3 bit unsigned number" (HASH-PREFIX) h-r01 f-uimm3) 552(dnop uimm4 "4 bit unsigned number" (HASH-PREFIX) h-uint f-uimm4) 553(dnop uimm7 "7 bit trap number" (HASH-PREFIX) h-uint f-uimm7) 554(dnop uimm8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm8) 555(dnop uimm16 "16 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm16) 556(dowh upof16 "16 bit unsigned immediate" (POF-PREFIX) h-addr f-memory ((print "with_pof_prefix"))) 557(dnop reg8 "8 bit word register number" () h-r8 f-reg8) 558(dnop regmem8 "8 bit word register number" () h-regmem8 f-regmem8) 559(dnop regbmem8 "8 bit byte register number" () h-regbmem8 f-regmem8) 560(dnop regoff8 "8 bit word register number" () h-r8 f-regoff8) 561(dnop reghi8 "8 bit word register number" () h-r8 f-reghi8) 562(dnop regb8 "8 bit byte register number" () h-grb8 f-regb8) 563(dnop genreg "8 bit word register number" () h-r8 f-regb8) 564(dnop seg "8 bit segment number" () h-uint f-seg8) 565(dnop seghi8 "8 bit hi segment number" () h-uint f-segnum8) 566(dnop caddr "16 bit address offset" () h-addr f-offset16) 567(dnop rel "8 bit signed relative offset" () h-sint f-rel8) 568(dnop relhi "hi 8 bit signed relative offset" () h-sint f-relhi8) 569(dnop condbit "condition bit" (SEM-ONLY) h-cond f-nil) 570(dnop bit1 "gap of 1 bit" () h-uint f-op-bit1) 571(dnop bit2 "gap of 2 bits" () h-uint f-op-bit2) 572(dnop bit4 "gap of 4 bits" () h-uint f-op-bit4) 573(dnop lbit4 "gap of 4 bits" () h-uint f-op-lbit4) 574(dnop lbit2 "gap of 2 bits" () h-uint f-op-lbit2) 575(dnop bit8 "gap of 8 bits" () h-uint f-op-bit8) 576(dnop u4 "gap of 4 bits" () h-r0 f-uimm4) 577(dnop bitone "field of 1 bit" () h-uint f-op-onebit) 578(dnop bit01 "field of 1 bit" () h-uint f-op-1bit) 579(dnop cond "condition code" () h-cc f-condcode) 580(dnop icond "indirect condition code" () h-cc f-icondcode) 581(dnop extcond "extended condition code" () h-ecc f-extccode) 582(dnop memory "16 bit memory" () h-addr f-memory) 583(dnop memgr8 "16 bit memory" () h-memgr8 f-memgr8) 584(dnop cbit "carry bit" (SEM-ONLY) h-cbit f-nil) 585(dowh qbit "bit addr" (DOT-PREFIX) h-uint f-qbit ((print "with_dot_prefix"))) 586(dowh qlobit "bit addr" (DOT-PREFIX) h-uint f-qlobit ((print "with_dot_prefix"))) 587(dowh qhibit "bit addr" (DOT-PREFIX) h-uint f-qhibit ((print "with_dot_prefix"))) 588(dnop mask8 "8 bit mask" (HASH-PREFIX) h-uint f-mask8) 589(dnop masklo8 "8 bit mask" (HASH-PREFIX) h-uint f-datahi8) 590(dnop pagenum "10 bit page number" (HASH-PREFIX) h-uint f-pagenum) 591(dnop data8 "8 bit data" (HASH-PREFIX) h-uint f-data8) 592(dnop datahi8 "8 bit data" (HASH-PREFIX) h-uint f-datahi8) 593(dnop sgtdisbit "segmentation enable bit" (SEM-ONLY) h-sgtdis f-nil) 594(dowh upag16 "16 bit unsigned immediate" (PAG-PREFIX) h-uint f-uimm16 ((print "with_pag_prefix"))) 595(dnop useg8 "8 bit segment " (SEG-PREFIX) h-uint f-seg8) 596(dnop useg16 "16 bit address offset" (SEG-PREFIX) h-uint f-offset16) 597(dnop usof16 "16 bit address offset" (SOF-PREFIX) h-uint f-offset16) 598 599; define hash operator 600(define-operand (name hash) (comment "# prefix") (attrs) 601 (type h-sint) 602 (index f-nil) 603 (handlers (parse "hash") (print "hash")) 604) 605 606; define dot operator 607(define-operand (name dot) (comment ". prefix") (attrs) 608 (type h-sint) 609 (index f-nil) 610 (handlers (parse "dot") (print "dot")) 611) 612 613; define pof operator 614(define-operand (name pof) (comment "pof: prefix") (attrs) 615 (type h-sint) 616 (index f-nil) 617 (handlers (parse "pof") (print "pof")) 618) 619 620; define pag operator 621(define-operand (name pag) (comment "pag: prefix") (attrs) 622 (type h-sint) 623 (index f-nil) 624 (handlers (parse "pag") (print "pag")) 625) 626 627; define sof operator 628(define-operand (name sof) (comment "sof: prefix") (attrs) 629 (type h-sint) 630 (index f-nil) 631 (handlers (parse "sof") (print "sof")) 632) 633 634; define seg operator 635(define-operand (name segm) (comment "seg: prefix") (attrs) 636 (type h-sint) 637 (index f-nil) 638 (handlers (parse "seg") (print "seg")) 639) 640 641; IDOC attribute for instruction documentation. 642(define-attr 643 (for insn) 644 (type enum) 645 (name IDOC) 646 (comment "insn kind for documentation") 647 (attrs META) 648 (values 649 (MOVE - () "Data Movement") 650 (ALU - () "Arithmatic & logical") 651 (CMP - () "Compare") 652 (JMP - () "Jump & Call") 653 (MISC - () "Miscellaneous") 654 (SYSC - () "System control") 655 ) 656) 657 658; Include the instruction set descriptions from their respective 659; source files. 660 661;Arithmatic insns 662;****************************************************************** 663 664;add/sub register and immediate 665(define-pmacro (arithmetic16 name insn insn1 opc1 opc2 op1 op2 mode dir) 666 (dni name 667 (.str name "arithmetic" ) 668 ((PIPE OS) (IDOC ALU)) 669 (.str insn " $"op1 ",$"dir"$"op2) 670 (+ opc1 opc2 op1 op2) 671 (set mode op1 (insn1 mode op1 (mem HI op2))) 672 () 673 ) 674) 675(arithmetic16 addrpof add add OP1_0 OP2_2 reg8 upof16 HI "pof") 676(arithmetic16 subrpof sub sub OP1_2 OP2_2 reg8 upof16 HI "pof") 677(arithmetic16 addbrpof addb add OP1_0 OP2_3 regb8 upof16 QI "pof") 678(arithmetic16 subbrpof subb sub OP1_2 OP2_3 regb8 upof16 QI "pof") 679(arithmetic16 addrpag add add OP1_0 OP2_2 reg8 upag16 HI "pag") 680(arithmetic16 subrpag sub sub OP1_2 OP2_2 reg8 upag16 HI "pag") 681(arithmetic16 addbrpag addb add OP1_0 OP2_3 regb8 upag16 QI "pag") 682(arithmetic16 subbrpag subb sub OP1_2 OP2_3 regb8 upag16 QI "pag") 683 684;add/sub register and immediate 685(define-pmacro (arithmetic17 name insn insn1 opc1 opc2 op1 op2 mode dir) 686 (dni name 687 (.str name "arithmetic" ) 688 ((PIPE OS) (IDOC ALU)) 689 (.str insn " $"op1 ",$"dir"$"op2) 690 (+ opc1 opc2 op1 op2) 691 (set mode op1 (insn1 mode op1 (mem HI op2) cbit)) 692 () 693 ) 694) 695(arithmetic17 addcrpof addc addc OP1_1 OP2_2 reg8 upof16 HI "pof") 696(arithmetic17 subcrpof subc subc OP1_3 OP2_2 reg8 upof16 HI "pof") 697(arithmetic17 addcbrpof addcb addc OP1_1 OP2_3 regb8 upof16 QI "pof") 698(arithmetic17 subcbrpof subcb subc OP1_3 OP2_3 regb8 upof16 QI "pof") 699(arithmetic17 addcrpag addc addc OP1_1 OP2_2 reg8 upag16 HI "pag") 700(arithmetic17 subcrpag subc subc OP1_3 OP2_2 reg8 upag16 HI "pag") 701(arithmetic17 addcbrpag addcb addc OP1_1 OP2_3 regb8 upag16 QI "pag") 702(arithmetic17 subcbrpag subcb subc OP1_3 OP2_3 regb8 upag16 QI "pag") 703 704;add/sub register and immediate 705(define-pmacro (arithmetic18 name insn insn1 opc1 opc2 op1 op2 mode dir) 706 (dni name 707 (.str name "arithmetic" ) 708 ((PIPE OS) (IDOC ALU)) 709 (.str insn " $"dir"$"op1 ",$"op2) 710 (+ opc1 opc2 op2 op1) 711 (set (mem HI op1) (insn1 (mem HI op1) op2 )) 712 () 713 ) 714) 715(arithmetic18 addrpofr add add OP1_0 OP2_4 upof16 reg8 HI "pof") 716(arithmetic18 subrpofr sub sub OP1_2 OP2_4 upof16 reg8 HI "pof") 717(arithmetic18 addbrpofr addb add OP1_0 OP2_5 upof16 regb8 QI "pof") 718(arithmetic18 subbrpofr subb sub OP1_2 OP2_5 upof16 regb8 QI "pof") 719 720;add/sub register and immediate 721(define-pmacro (arithmetic19 name insn insn1 opc1 opc2 op1 op2 mode dir) 722 (dni name 723 (.str name "arithmetic" ) 724 ((PIPE OS) (IDOC ALU)) 725 (.str insn " $"dir"$"op1 ",$"op2) 726 (+ opc1 opc2 op2 op1) 727 (set (mem HI op1) (insn1 mode (mem HI op1) op2 cbit)) 728 () 729 ) 730) 731(arithmetic19 addcrpofr addc addc OP1_1 OP2_4 upof16 reg8 HI "pof") 732(arithmetic19 subcrpofr subc subc OP1_3 OP2_4 upof16 reg8 HI "pof") 733(arithmetic19 addcbrpofr addcb addc OP1_1 OP2_5 upof16 regb8 QI "pof") 734(arithmetic19 subcbrpofr subcb subc OP1_3 OP2_5 upof16 regb8 QI "pof") 735 736;add/sub register and immediate 737(define-pmacro (arithmetic20 name insn insn1 opc1 opc2 op1 op2 mode dir) 738 (dni name 739 (.str name "arithmetic" ) 740 ((PIPE OS) (IDOC ALU)) 741 (.str insn " $"op1 ",$hash$"dir"$"op2) 742 (+ opc1 opc2 op1 op2) 743 (set mode op1 (insn1 mode op1 op2)) 744 () 745 ) 746) 747(arithmetic20 addrhpof add add OP1_0 OP2_6 reg8 uimm16 HI "pof") 748(arithmetic20 subrhpof sub sub OP1_2 OP2_6 reg8 uimm16 HI "pof") 749(arithmetic20 addbrhpof add add OP1_0 OP2_6 reg8 uimm16 HI "pag") 750(arithmetic20 subbrhpof sub sub OP1_2 OP2_6 reg8 uimm16 HI "pag") 751 752;add/sub register and immediate 753(define-pmacro (arithmetic21 name insn insn1 opc1 opc2 op1 op2 mode dir) 754 (dni name 755 (.str name "arithmetic" ) 756 ((PIPE OS) (IDOC ALU)) 757 (.str insn " $"op1 ",$hash$"dir"$"op2) 758 (+ opc1 opc2 op1 (f-op-bit1 0) op2) 759 (set mode op1 (insn1 mode op1 op2)) 760 () 761 ) 762) 763(arithmetic21 addrhpof3 add add OP1_0 OP2_8 dr uimm3 HI "pof") 764(arithmetic21 subrhpof3 sub sub OP1_2 OP2_8 dr uimm3 HI "pof") 765(arithmetic21 addbrhpag3 addb add OP1_0 OP2_9 drb uimm3 QI "pag") 766(arithmetic21 subbrhpag3 subb sub OP1_2 OP2_9 drb uimm3 QI "pag") 767(arithmetic21 addrhpag3 add add OP1_0 OP2_8 dr uimm3 HI "pag") 768(arithmetic21 subrhpag3 sub sub OP1_2 OP2_8 dr uimm3 HI "pag") 769(arithmetic21 addbrhpof3 addb add OP1_0 OP2_9 drb uimm3 QI "pof") 770(arithmetic21 subbrhpof3 subb sub OP1_2 OP2_9 drb uimm3 QI "pof") 771 772;add/sub register and immediate 773(define-pmacro (arithmetic22 name insn insn1 opc1 opc2 op1 op2 mode dir) 774 (dni name 775 (.str name "arithmetic" ) 776 ((PIPE OS) (IDOC ALU)) 777 (.str insn " $"op1 ",$hash$"dir"$"op2) 778 (+ opc1 opc2 op1 op2 (f-op-bit8 0)) 779 (set mode op1 (insn1 mode op1 op2)) 780 () 781 ) 782) 783(arithmetic22 addrbhpof addb add OP1_0 OP2_7 regb8 uimm8 QI "pof") 784(arithmetic22 subrbhpof subb sub OP1_2 OP2_7 regb8 uimm8 QI "pof") 785(arithmetic22 addbrhpag addb add OP1_0 OP2_7 regb8 uimm8 QI "pag") 786(arithmetic22 subbrhpag subb sub OP1_2 OP2_7 regb8 uimm8 QI "pag") 787 788;add/sub register and immediate 789(define-pmacro (arithmetic23 name insn insn1 opc1 opc2 op1 op2 mode dir) 790 (dni name 791 (.str name "arithmetic" ) 792 ((PIPE OS) (IDOC ALU)) 793 (.str insn " $"op1 ",$hash$"dir"$"op2) 794 (+ opc1 opc2 op1 op2) 795 (set mode op1 (insn1 mode op1 op2 cbit)) 796 () 797 ) 798) 799(arithmetic23 addcrhpof addc addc OP1_1 OP2_6 reg8 uimm16 HI "pof") 800(arithmetic23 subcrhpof subc subc OP1_3 OP2_6 reg8 uimm16 HI "pof") 801(arithmetic23 addcbrhpof addc addc OP1_1 OP2_6 reg8 uimm16 HI "pag") 802(arithmetic23 subcbrhpof subc subc OP1_3 OP2_6 reg8 uimm16 HI "pag") 803 804;add/sub register and immediate 805(define-pmacro (arithmetic24 name insn insn1 opc1 opc2 op1 op2 mode dir) 806 (dni name 807 (.str name "arithmetic" ) 808 ((PIPE OS) (IDOC ALU)) 809 (.str insn " $"op1 ",$hash$"dir"$"op2) 810 (+ opc1 opc2 op1 (f-op-bit1 0) op2) 811 (set mode op1 (insn1 mode op1 op2 cbit)) 812 () 813 ) 814) 815(arithmetic24 addcrhpof3 addc addc OP1_1 OP2_8 dr uimm3 HI "pof") 816(arithmetic24 subcrhpof3 subc subc OP1_3 OP2_8 dr uimm3 HI "pof") 817(arithmetic24 addcbrhpag3 addcb addc OP1_1 OP2_9 drb uimm3 QI "pag") 818(arithmetic24 subcbrhpag3 subcb subc OP1_3 OP2_9 drb uimm3 QI "pag") 819(arithmetic24 addcrhpag3 addc addc OP1_1 OP2_8 dr uimm3 HI "pag") 820(arithmetic24 subcrhpag3 subc subc OP1_3 OP2_8 dr uimm3 HI "pag") 821(arithmetic24 addcbrhpof3 addcb addc OP1_1 OP2_9 drb uimm3 QI "pof") 822(arithmetic24 subcbrhpof3 subcb subc OP1_3 OP2_9 drb uimm3 QI "pof") 823 824;add/sub register and immediate 825(define-pmacro (arithmetic25 name insn insn1 opc1 opc2 op1 op2 mode dir) 826 (dni name 827 (.str name "arithmetic" ) 828 ((PIPE OS) (IDOC ALU)) 829 (.str insn " $"op1 ",$hash$"dir"$"op2) 830 (+ opc1 opc2 op1 op2 (f-op-bit8 0)) 831 (set mode op1 (insn1 mode op1 op2 cbit)) 832 () 833 ) 834) 835(arithmetic25 addcrbhpof addcb addc OP1_1 OP2_7 regb8 uimm8 QI "pof") 836(arithmetic25 subcrbhpof subcb subc OP1_3 OP2_7 regb8 uimm8 QI "pof") 837(arithmetic25 addcbrhpag addcb addc OP1_1 OP2_7 regb8 uimm8 QI "pag") 838(arithmetic25 subcbrhpag subcb subc OP1_3 OP2_7 regb8 uimm8 QI "pag") 839 840;add/sub register and immediate 841(define-pmacro (arithmetic10 name insn insn1 opc1 opc2 op1 op2 mode) 842 (dni name 843 (.str name "arithmetic" ) 844 ((PIPE OS) (IDOC ALU)) 845 (.str insn " $"op1 ",$hash$"op2) 846 (+ opc1 opc2 op1 (f-op-bit1 0) op2) 847 (set mode op1 (insn1 mode op1 op2)) 848 () 849 ) 850) 851(arithmetic10 addri add add OP1_0 OP2_8 dr uimm3 HI) 852(arithmetic10 subri sub sub OP1_2 OP2_8 dr uimm3 HI) 853(arithmetic10 addbri addb add OP1_0 OP2_9 drb uimm3 QI) 854(arithmetic10 subbri subb sub OP1_2 OP2_9 drb uimm3 QI) 855 856;add/sub register and immediate 857(define-pmacro (arithmetic11 name insn insn1 opc1 opc2 op1 op2 mode) 858 (dni name 859 (.str name "arithmetic" ) 860 ((PIPE OS) (IDOC ALU)) 861 (.str insn " $"op1 ",$hash$"op2) 862 (+ opc1 opc2 op1 op2) 863 (set mode op1 (insn1 mode op1 op2)) 864 () 865 ) 866) 867(arithmetic11 addrim add add OP1_0 OP2_6 reg8 uimm16 HI) 868(arithmetic11 subrim sub sub OP1_2 OP2_6 reg8 uimm16 HI) 869 870;add/sub register and immediate 871(define-pmacro (arithmetic12 name insn insn1 opc1 opc2 op1 op2 mode) 872 (dni name 873 (.str name "arithmetic" ) 874 ((PIPE OS) (IDOC ALU)) 875 (.str insn " $"op1 ",$hash$"op2) 876 (+ opc1 opc2 op1 op2 (f-op-bit8 0)) 877 (set mode op1 (insn1 mode op1 op2)) 878 () 879 ) 880) 881(arithmetic12 addbrim addb add OP1_0 OP2_7 regb8 uimm8 QI) 882(arithmetic12 subbrim subb sub OP1_2 OP2_7 regb8 uimm8 QI) 883 884;add/sub register and immediate with carry 885(define-pmacro (arithmetic13 name insn insn1 opc1 opc2 op1 op2 mode) 886 (dni name 887 (.str name "arithmetic" ) 888 ((PIPE OS) (IDOC ALU)) 889 (.str insn " $"op1 ",$hash$"op2) 890 (+ opc1 opc2 op1 (f-op-bit1 0) op2) 891 (set mode op1 (insn1 mode op1 op2 cbit)) 892 () 893 ) 894) 895(arithmetic13 addcri addc addc OP1_1 OP2_8 dr uimm3 HI) 896(arithmetic13 subcri subc subc OP1_3 OP2_8 dr uimm3 HI) 897(arithmetic13 addcbri addcb addc OP1_1 OP2_9 drb uimm3 QI) 898(arithmetic13 subcbri subcb subc OP1_3 OP2_9 drb uimm3 QI) 899 900;add/sub register and immediate with carry 901(define-pmacro (arithmetic14 name insn insn1 opc1 opc2 op1 op2 mode) 902 (dni name 903 (.str name "arithmetic" ) 904 ((PIPE OS) (IDOC ALU)) 905 (.str insn " $"op1 ",$hash$"op2) 906 (+ opc1 opc2 op1 op2) 907 (set mode op1 (insn1 mode op1 op2 cbit)) 908 () 909 ) 910) 911(arithmetic14 addcrim addc addc OP1_1 OP2_6 reg8 uimm16 HI) 912(arithmetic14 subcrim subc subc OP1_3 OP2_6 reg8 uimm16 HI) 913 914;add/sub register and immediate with carry 915(define-pmacro (arithmetic15 name insn insn1 opc1 opc2 op1 op2 mode) 916 (dni name 917 (.str name "arithmetic" ) 918 ((PIPE OS) (IDOC ALU)) 919 (.str insn " $"op1 ",$hash$"op2) 920 (+ opc1 opc2 op1 op2 (f-op-bit8 0)) 921 (set mode op1 (insn1 mode op1 op2 cbit)) 922 () 923 ) 924) 925(arithmetic15 addcbrim addcb addc OP1_1 OP2_7 regb8 uimm8 QI) 926(arithmetic15 subcbrim subcb subc OP1_3 OP2_7 regb8 uimm8 QI) 927 928 929;add/sub registers 930(define-pmacro (arithmetic name insn insn1 opc1 opc2 op1 op2 mode) 931 (dni name 932 (.str name "arithmetic" ) 933 ((PIPE OS) (IDOC ALU)) 934 (.str insn " $"op1 ",$"op2) 935 (+ opc1 opc2 op1 op2) 936 (set mode op1 (insn1 mode op1 op2)) 937 () 938 ) 939) 940(arithmetic addr add add OP1_0 OP2_0 dr sr HI) 941(arithmetic subr sub sub OP1_2 OP2_0 dr sr HI) 942(arithmetic addbr addb add OP1_0 OP2_1 drb srb QI) 943(arithmetic subbr subb sub OP1_2 OP2_1 drb srb QI) 944 945;add/sub register and indirect memory 946(define-pmacro (arithmetic1 name insn insn1 opc1 opc2 op1 op2 mode) 947 (dni name 948 (.str name "arithmetic" ) 949 ((PIPE OS) (IDOC ALU)) 950 (.str insn " $"op1 ",[$"op2"]") 951 (+ opc1 opc2 op1 (f-op-bit2 2) op2) 952 (set mode op1 (insn1 mode op1 (mem HI op2))) 953 () 954 ) 955) 956(arithmetic1 add2 add add OP1_0 OP2_8 dr sr2 HI) 957(arithmetic1 sub2 sub sub OP1_2 OP2_8 dr sr2 HI) 958(arithmetic1 addb2 addb add OP1_0 OP2_9 drb sr2 QI) 959(arithmetic1 subb2 subb sub OP1_2 OP2_9 drb sr2 QI) 960 961;add/sub register and indirect memory post increment 962(define-pmacro (arithmetic2 name insn insn1 opc1 opc2 op1 op2 mode) 963 (dni name 964 (.str name "arithmetic" ) 965 ((PIPE OS) (IDOC ALU)) 966 (.str insn " $"op1 ",[$"op2"+]") 967 (+ opc1 opc2 op1 (f-op-bit2 3) op2) 968 (sequence () 969 (set mode op1 (insn1 mode op1 (mem HI op2))) 970 (set HI op2 (add HI op2 (const 2))) 971 ) 972 () 973 ) 974) 975(arithmetic2 add2i add add OP1_0 OP2_8 dr sr2 HI) 976(arithmetic2 sub2i sub sub OP1_2 OP2_8 dr sr2 HI) 977(arithmetic2 addb2i addb add OP1_0 OP2_9 drb sr2 QI) 978(arithmetic2 subb2i subb sub OP1_2 OP2_9 drb sr2 QI) 979 980;add/sub registers with carry 981(define-pmacro (arithmetic3 name insn insn1 opc1 opc2 op1 op2 mode) 982 (dni name 983 (.str name "arithmetic" ) 984 ((PIPE OS) (IDOC ALU)) 985 (.str insn " $"op1 ",$"op2) 986 (+ opc1 opc2 op1 op2) 987 (set mode op1 (insn1 mode op1 op2 cbit)) 988 () 989 ) 990) 991(arithmetic3 addcr addc addc OP1_1 OP2_0 dr sr HI) 992(arithmetic3 subcr subc subc OP1_3 OP2_0 dr sr HI) 993(arithmetic3 addbcr addcb addc OP1_1 OP2_1 drb srb QI) 994(arithmetic3 subbcr subcb subc OP1_3 OP2_1 drb srb QI) 995 996 997;add/sub register and indirect memory 998(define-pmacro (arithmetic4 name insn insn1 opc1 opc2 op1 op2 mode) 999 (dni name 1000 (.str name "arithmetic" ) 1001 ((PIPE OS) (IDOC ALU)) 1002 (.str insn " $"op1 ",[$"op2"]") 1003 (+ opc1 opc2 op1 (f-op-bit2 2) op2) 1004 (set mode op1 (insn1 mode op1 (mem HI op2) cbit)) 1005 () 1006 ) 1007) 1008(arithmetic4 addcr2 addc addc OP1_1 OP2_8 dr sr2 HI) 1009(arithmetic4 subcr2 subc subc OP1_3 OP2_8 dr sr2 HI) 1010(arithmetic4 addbcr2 addcb addc OP1_1 OP2_9 drb sr2 QI) 1011(arithmetic4 subbcr2 subcb subc OP1_3 OP2_9 drb sr2 QI) 1012 1013;add/sub register and indirect memory post increment 1014(define-pmacro (arithmetic5 name insn insn1 opc1 opc2 op1 op2 mode) 1015 (dni name 1016 (.str name "arithmetic" ) 1017 ((PIPE OS) (IDOC ALU)) 1018 (.str insn " $"op1 ",[$"op2"+]") 1019 (+ opc1 opc2 op1 (f-op-bit2 3) op2) 1020 (sequence () 1021 (set mode op1 (insn1 mode op1 (mem HI op2) cbit)) 1022 (set HI op2 (add HI op2 (const 2))) 1023 ) 1024 () 1025 ) 1026) 1027(arithmetic5 addcr2i addc addc OP1_1 OP2_8 dr sr2 HI) 1028(arithmetic5 subcr2i subc subc OP1_3 OP2_8 dr sr2 HI) 1029(arithmetic5 addbcr2i addcb addc OP1_1 OP2_9 drb sr2 QI) 1030(arithmetic5 subbcr2i subcb subc OP1_3 OP2_9 drb sr2 QI) 1031 1032;add/sub register and direct memory 1033(define-pmacro (arithmetic6 name insn insn1 opc1 opc2 op1 op2 mode) 1034 (dni name 1035 (.str name "arithmetic" ) 1036 ((PIPE OS) (IDOC ALU)) 1037 (.str insn " $"op1 ",$"op2) 1038 (+ opc1 opc2 op1 op2) 1039 (set mode op1 (insn1 mode op1 op2)) 1040 () 1041 ) 1042) 1043 1044;add/sub register and direct memory 1045(define-pmacro (arithmetic7 name insn insn1 opc1 opc2 op1 op2 mode) 1046 (dni name 1047 (.str name "arithmetic" ) 1048 ((PIPE OS) (IDOC ALU)) 1049 (.str insn " $"op1 ",$"op2) 1050 (+ opc1 opc2 op2 op1) 1051 (set (mem HI op1) (insn1 (mem HI op1) op2)) 1052 () 1053 ) 1054) 1055(arithmetic6 addrm2 add add OP1_0 OP2_2 regmem8 memgr8 HI) 1056(arithmetic7 addrm3 add add OP1_0 OP2_4 memgr8 regmem8 HI) 1057(arithmetic6 addrm add add OP1_0 OP2_2 reg8 memory HI) 1058(arithmetic7 addrm1 add add OP1_0 OP2_4 memory reg8 HI) 1059(arithmetic6 subrm3 sub sub OP1_2 OP2_2 regmem8 memgr8 HI) 1060(arithmetic7 subrm2 sub sub OP1_2 OP2_4 memgr8 regmem8 HI) 1061(arithmetic6 subrm1 sub sub OP1_2 OP2_2 reg8 memory HI) 1062(arithmetic7 subrm sub sub OP1_2 OP2_4 memory reg8 HI) 1063(arithmetic6 addbrm2 addb add OP1_0 OP2_3 regbmem8 memgr8 QI) 1064(arithmetic7 addbrm3 addb add OP1_0 OP2_5 memgr8 regbmem8 QI) 1065(arithmetic6 addbrm addb add OP1_0 OP2_3 regb8 memory QI) 1066(arithmetic7 addbrm1 addb add OP1_0 OP2_5 memory regb8 QI) 1067(arithmetic6 subbrm3 subb sub OP1_2 OP2_3 regbmem8 memgr8 QI) 1068(arithmetic7 subbrm2 subb sub OP1_2 OP2_5 memgr8 regbmem8 QI) 1069(arithmetic6 subbrm1 subb sub OP1_2 OP2_3 regb8 memory QI) 1070(arithmetic7 subbrm subb sub OP1_2 OP2_5 memory regb8 QI) 1071 1072;add/sub registers with carry 1073(define-pmacro (arithmetic8 name insn insn1 opc1 opc2 op1 op2 mode) 1074 (dni name 1075 (.str name "arithmetic" ) 1076 ((PIPE OS) (IDOC ALU)) 1077 (.str insn " $"op1 ",$"op2) 1078 (+ opc1 opc2 op1 op2) 1079 (set mode op1 (insn1 mode op1 op2 cbit)) 1080 () 1081 ) 1082) 1083 1084;add/sub registers with carry 1085(define-pmacro (arithmetic9 name insn insn1 opc1 opc2 op1 op2 mode) 1086 (dni name 1087 (.str name "arithmetic" ) 1088 ((PIPE OS) (IDOC ALU)) 1089 (.str insn " $"op1 ",$"op2) 1090 (+ opc1 opc2 op2 op1) 1091 (set (mem HI op1) (insn1 (mem HI op1) op2 cbit)) 1092 () 1093 ) 1094) 1095(arithmetic8 addcrm2 addc addc OP1_1 OP2_2 regmem8 memgr8 HI) 1096(arithmetic9 addcrm3 addc addc OP1_1 OP2_4 memgr8 regmem8 HI) 1097(arithmetic8 addcrm addc addc OP1_1 OP2_2 reg8 memory HI) 1098(arithmetic9 addcrm1 addc addc OP1_1 OP2_4 memory reg8 HI) 1099(arithmetic8 subcrm3 subc subc OP1_3 OP2_2 regmem8 memgr8 HI) 1100(arithmetic9 subcrm2 subc subc OP1_3 OP2_4 memgr8 regmem8 HI) 1101(arithmetic8 subcrm1 subc subc OP1_3 OP2_2 reg8 memory HI) 1102(arithmetic9 subcrm subc subc OP1_3 OP2_4 memory reg8 HI) 1103(arithmetic8 addcbrm2 addcb addc OP1_1 OP2_3 regbmem8 memgr8 QI) 1104(arithmetic9 addcbrm3 addcb addc OP1_1 OP2_5 memgr8 regbmem8 QI) 1105(arithmetic8 addcbrm addcb addc OP1_1 OP2_3 regb8 memory QI) 1106(arithmetic9 addcbrm1 addcb addc OP1_1 OP2_5 memory regb8 QI) 1107(arithmetic8 subcbrm3 subcb subc OP1_3 OP2_3 regbmem8 memgr8 QI) 1108(arithmetic9 subcbrm2 subcb subc OP1_3 OP2_5 memgr8 regbmem8 QI) 1109(arithmetic8 subcbrm1 subcb subc OP1_3 OP2_3 regb8 memory QI) 1110(arithmetic9 subcbrm subcb subc OP1_3 OP2_5 memory regb8 QI) 1111 1112; MUL Rwn,Rwm 1113(dni muls "signed multiplication" 1114 ((PIPE OS) (IDOC ALU)) 1115 "mul $src1,$src2" 1116 (+ OP1_0 OP2_11 src1 src2) 1117 (nop) ;; FIXME: (reg SI h-md 0) 1118 () 1119) 1120; MULU Rwn,Rwm 1121(dni mulu "unsigned multiplication" 1122 ((PIPE OS) (IDOC ALU)) 1123 "mulu $src1,$src2" 1124 (+ OP1_1 OP2_11 src1 src2) 1125 (nop) ;; FIXME: (reg SI h-md 0) 1126 () 1127) 1128; DIV Rwn 1129(dni div "16-by-16 signed division" 1130 ((PIPE OS) (IDOC ALU)) 1131 "div $srdiv" 1132 (+ OP1_4 OP2_11 srdiv ) 1133 (sequence () 1134 (set HI (reg HI h-cr 6) (div HI (reg HI h-cr 6) srdiv)) 1135 (set HI (reg HI h-cr 7) (mod HI (reg HI h-cr 6) srdiv)) 1136 ) 1137 () 1138) 1139; DIVL Rwn 1140(dni divl "32-by16 signed division" 1141 ((PIPE OS) (IDOC ALU)) 1142 "divl $srdiv" 1143 (+ OP1_6 OP2_11 srdiv ) 1144 (sequence () 1145 (set HI (reg HI h-cr 6) 0) ;; FIXME: (div SI (reg SI h-md 0) srdiv)) 1146 (set HI (reg HI h-cr 7) 0) ;; FIXME: (mod SI (reg SI h-md 0) srdiv)) 1147 ) 1148 () 1149) 1150; DIVLU Rwn 1151(dni divlu "32-by16 unsigned division" 1152 ((PIPE OS) (IDOC ALU)) 1153 "divlu $srdiv" 1154 (+ OP1_7 OP2_11 srdiv ) 1155 (sequence () 1156 (set HI (reg HI h-cr 6) 0) ;; FIXME: (udiv SI (reg SI h-md 0) srdiv)) 1157 (set HI (reg HI h-cr 7) 0) ;; FIXME: (umod SI (reg SI h-md 0) srdiv)) 1158 ) 1159 () 1160) 1161; DIVU Rwn 1162(dni divu "16-by-16 unsigned division" 1163 ((PIPE OS) (IDOC ALU)) 1164 "divu $srdiv" 1165 (+ OP1_5 OP2_11 srdiv ) 1166 (sequence () 1167 (set HI (reg HI h-cr 6) (udiv HI (reg HI h-cr 6) srdiv)) 1168 (set HI (reg HI h-cr 7) (umod HI (reg HI h-cr 6) srdiv)) 1169 ) 1170 () 1171) 1172 1173;Integer one's complement 1174; CPL Rwn 1175(dni cpl "Integer Ones complement" 1176 ((PIPE OS) (IDOC MISC)) 1177 "cpl $dr" 1178 (+ OP1_9 OP2_1 dr (f-op-bit4 0)) 1179 (set dr (inv HI dr)) 1180 () 1181) 1182 1183;Bytes one's complement 1184; CPLB Rbn 1185(dni cplb "Byte Ones complement" 1186 ((PIPE OS) (IDOC MISC)) 1187 "cplb $drb" 1188 (+ OP1_11 OP2_1 drb (f-op-bit4 0)) 1189 (set drb (inv QI drb)) 1190 () 1191) 1192;Integer two's complement 1193; NEG Rwn 1194(dni neg "Integer two's complement" 1195 ((PIPE OS) (IDOC MISC)) 1196 "neg $dr" 1197 (+ OP1_8 OP2_1 dr (f-op-bit4 0)) 1198 (set dr (neg HI dr)) 1199 () 1200) 1201;Bytes two's complement 1202; NEGB Rbn 1203(dni negb "byte twos complement" 1204 ((PIPE OS) (IDOC MISC)) 1205 "negb $drb" 1206 (+ OP1_10 OP2_1 drb (f-op-bit4 0)) 1207 (set drb (neg QI drb)) 1208 () 1209) 1210 1211;**************************************************************** 1212;logical insn 1213;**************************************************************** 1214;and/or/xor registers 1215(define-pmacro (logical name insn insn1 opc1 opc2 op1 op2 mode) 1216 (dni name 1217 (.str name "logical" ) 1218 ((PIPE OS) (IDOC ALU)) 1219 (.str insn " $"op1 ",$"op2) 1220 (+ opc1 opc2 op1 op2) 1221 (set mode op1 (insn1 mode op1 op2)) 1222 () 1223 ) 1224) 1225 1226(logical andr and and OP1_6 OP2_0 dr sr HI) 1227(logical orr or or OP1_7 OP2_0 dr sr HI) 1228(logical xorr xor xor OP1_5 OP2_0 dr sr HI) 1229(logical andbr andb and OP1_6 OP2_1 drb srb QI) 1230(logical orbr orb or OP1_7 OP2_1 drb srb QI) 1231(logical xorbr xorb xor OP1_5 OP2_1 drb srb QI) 1232 1233;and/or/xor register and immediate 1234(define-pmacro (logical1 name insn insn1 opc1 opc2 op1 op2 mode) 1235 (dni name 1236 (.str name "logical" ) 1237 ((PIPE OS) (IDOC ALU)) 1238 (.str insn " $"op1 ",$hash$"op2) 1239 (+ opc1 opc2 op1 (f-op-bit1 0) op2) 1240 (set mode op1 (insn1 mode op1 op2)) 1241 () 1242 ) 1243) 1244(logical1 andri and and OP1_6 OP2_8 dr uimm3 HI) 1245(logical1 orri or or OP1_7 OP2_8 dr uimm3 HI) 1246(logical1 xorri xor xor OP1_5 OP2_8 dr uimm3 HI) 1247(logical1 andbri andb and OP1_6 OP2_9 drb uimm3 QI) 1248(logical1 orbri orb or OP1_7 OP2_9 drb uimm3 QI) 1249(logical1 xorbri xorb xor OP1_5 OP2_9 drb uimm3 QI) 1250 1251;and/or/xor register and immediate 1252(define-pmacro (logical2 name insn insn1 opc1 opc2 op1 op2 mode) 1253 (dni name 1254 (.str name "logical" ) 1255 ((PIPE OS) (IDOC ALU)) 1256 (.str insn " $"op1 ",$hash$"op2) 1257 (+ opc1 opc2 op1 op2) 1258 (set mode op1 (insn1 mode op1 op2)) 1259 () 1260 ) 1261) 1262(logical2 andrim and and OP1_6 OP2_6 reg8 uimm16 HI) 1263(logical2 orrim or or OP1_7 OP2_6 reg8 uimm16 HI) 1264(logical2 xorrim xor xor OP1_5 OP2_6 reg8 uimm16 HI) 1265 1266;and/or/xor register and immediate 1267(define-pmacro (logical3 name insn insn1 opc1 opc2 op1 op2 mode) 1268 (dni name 1269 (.str name "logical" ) 1270 ((PIPE OS) (IDOC ALU)) 1271 (.str insn " $"op1 ",$hash$"op2) 1272 (+ opc1 opc2 op1 op2 (f-op-bit8 0)) 1273 (set mode op1 (insn1 mode op1 op2)) 1274 () 1275 ) 1276) 1277(logical3 andbrim andb and OP1_6 OP2_7 regb8 uimm8 QI) 1278(logical3 orbrim orb or OP1_7 OP2_7 regb8 uimm8 QI) 1279(logical3 xorbrim xorb xor OP1_5 OP2_7 regb8 uimm8 QI) 1280 1281;and/or/xor register and indirect memory 1282(define-pmacro (logical4 name insn insn1 opc1 opc2 op1 op2 mode) 1283 (dni name 1284 (.str name "logical" ) 1285 ((PIPE OS) (IDOC ALU)) 1286 (.str insn " $"op1 ",[$"op2"]") 1287 (+ opc1 opc2 op1 (f-op-bit2 2) op2) 1288 (set mode op1 (insn1 mode op1 (mem HI op2))) 1289 () 1290 ) 1291) 1292(logical4 and2 and and OP1_6 OP2_8 dr sr2 HI) 1293(logical4 or2 or or OP1_7 OP2_8 dr sr2 HI) 1294(logical4 xor2 xor xor OP1_5 OP2_8 dr sr2 HI) 1295(logical4 andb2 andb and OP1_6 OP2_9 drb sr2 QI) 1296(logical4 orb2 orb or OP1_7 OP2_9 drb sr2 QI) 1297(logical4 xorb2 xorb xor OP1_5 OP2_9 drb sr2 QI) 1298 1299;and/or/xor register and indirect memory post increment 1300(define-pmacro (logical5 name insn insn1 opc1 opc2 op1 op2 mode) 1301 (dni name 1302 (.str name "logical" ) 1303 ((PIPE OS) (IDOC ALU)) 1304 (.str insn " $"op1 ",[$"op2"+]") 1305 (+ opc1 opc2 op1 (f-op-bit2 3) op2) 1306 (sequence () 1307 (set mode op1 (insn1 mode op1 (mem HI op2))) 1308 (set HI op2 (add HI op2 (const 2))) 1309 ) 1310 () 1311 ) 1312) 1313(logical5 and2i and and OP1_6 OP2_8 dr sr2 HI) 1314(logical5 or2i or or OP1_7 OP2_8 dr sr2 HI) 1315(logical5 xor2i xor xor OP1_5 OP2_8 dr sr2 HI) 1316(logical5 andb2i andb and OP1_6 OP2_9 drb sr2 QI) 1317(logical5 orb2i orb or OP1_7 OP2_9 drb sr2 QI) 1318(logical5 xorb2i xorb xor OP1_5 OP2_9 drb sr2 QI) 1319 1320;add/sub register and immediate 1321(define-pmacro (logical7 name insn insn1 opc1 opc2 op1 op2 mode dir) 1322 (dni name 1323 (.str name "arithmetic" ) 1324 ((PIPE OS) (IDOC ALU)) 1325 (.str insn " $"dir"$"op1 ",$"op2) 1326 (+ opc1 opc2 op1 op2) 1327 (set (mem HI op1) (insn1 (mem HI op1) op2 )) 1328 () 1329 ) 1330) 1331(logical7 andpofr and and OP1_6 OP2_2 reg8 upof16 HI "pof") 1332(logical7 orpofr or or OP1_7 OP2_2 reg8 upof16 HI "pof") 1333(logical7 xorpofr xor xor OP1_5 OP2_2 reg8 upof16 HI "pof") 1334(logical7 andbpofr andb and OP1_6 OP2_3 regb8 upof16 QI "pof") 1335(logical7 orbpofr orb or OP1_7 OP2_3 regb8 upof16 QI "pof") 1336(logical7 xorbpofr xorb xor OP1_5 OP2_3 regb8 upof16 QI "pof") 1337 1338;add/sub register and immediate 1339(define-pmacro (logical8 name insn insn1 opc1 opc2 op1 op2 mode dir) 1340 (dni name 1341 (.str name "arithmetic" ) 1342 ((PIPE OS) (IDOC ALU)) 1343 (.str insn " $"dir"$"op1 ",$"op2) 1344 (+ opc1 opc2 op1 op2) 1345 (set (mem HI op1) (insn1 (mem HI op1) op2 )) 1346 () 1347 ) 1348) 1349(logical8 andrpofr and and OP1_6 OP2_4 upof16 reg8 HI "pof") 1350(logical8 orrpofr or or OP1_7 OP2_4 upof16 reg8 HI "pof") 1351(logical8 xorrpofr xor xor OP1_5 OP2_4 upof16 reg8 HI "pof") 1352(logical8 andbrpofr andb and OP1_6 OP2_5 upof16 regb8 QI "pof") 1353(logical8 orbrpofr orb or OP1_7 OP2_5 upof16 regb8 QI "pof") 1354(logical8 xorbrpofr xorb xor OP1_5 OP2_5 upof16 regb8 QI "pof") 1355 1356;and/or/xor register and direct memory 1357(define-pmacro (logical6 name insn insn1 opc1 opc2 op1 op2 mode) 1358 (dni name 1359 (.str name "arithmetic" ) 1360 ((PIPE OS) (IDOC ALU)) 1361 (.str insn " $"op1 ",$"op2) 1362 (+ opc1 opc2 op1 op2) 1363 (set mode op1 (insn1 mode op1 op2)) 1364 () 1365 ) 1366) 1367 1368;and/or/xor register and direct memory 1369(define-pmacro (logical7 name insn insn1 opc1 opc2 op1 op2 mode) 1370 (dni name 1371 (.str name "arithmetic" ) 1372 ((PIPE OS) (IDOC ALU)) 1373 (.str insn " $"op1 ",$"op2) 1374 (+ opc1 opc2 op2 op1) 1375 (set (mem HI op1) (insn1 (mem HI op1) op2)) 1376 () 1377 ) 1378) 1379(logical6 andrm2 and and OP1_6 OP2_2 regmem8 memgr8 HI) 1380(logical7 andrm3 and and OP1_6 OP2_4 memgr8 regmem8 HI) 1381(logical6 andrm and and OP1_6 OP2_2 reg8 memory HI) 1382(logical7 andrm1 and and OP1_6 OP2_4 memory reg8 HI) 1383(logical6 orrm3 or or OP1_7 OP2_2 regmem8 memgr8 HI) 1384(logical7 orrm2 or or OP1_7 OP2_4 memgr8 regmem8 HI) 1385(logical6 orrm1 or or OP1_7 OP2_2 reg8 memory HI) 1386(logical7 orrm or or OP1_7 OP2_4 memory reg8 HI) 1387(logical6 xorrm3 xor xor OP1_5 OP2_2 regmem8 memgr8 HI) 1388(logical7 xorrm2 xor xor OP1_5 OP2_4 memgr8 regmem8 HI) 1389(logical6 xorrm1 xor xor OP1_5 OP2_2 reg8 memory HI) 1390(logical7 xorrm xor xor OP1_5 OP2_4 memory reg8 HI) 1391(logical6 andbrm2 andb and OP1_6 OP2_3 regbmem8 memgr8 QI) 1392(logical7 andbrm3 andb and OP1_6 OP2_5 memgr8 regbmem8 QI) 1393(logical6 andbrm andb and OP1_6 OP2_3 regb8 memory QI) 1394(logical7 andbrm1 andb and OP1_6 OP2_5 memory regb8 QI) 1395(logical6 orbrm3 orb or OP1_7 OP2_3 regbmem8 memgr8 QI) 1396(logical7 orbrm2 orb or OP1_7 OP2_5 memgr8 regbmem8 QI) 1397(logical6 orbrm1 orb or OP1_7 OP2_3 regb8 memory QI) 1398(logical7 orbrm orb or OP1_7 OP2_5 memory regb8 QI) 1399(logical6 xorbrm3 xorb xor OP1_5 OP2_3 regbmem8 memgr8 QI) 1400(logical7 xorbrm2 xorb xor OP1_5 OP2_5 memgr8 regbmem8 QI) 1401(logical6 xorbrm1 xorb xor OP1_5 OP2_3 regb8 memory QI) 1402(logical7 xorbrm xorb xor OP1_5 OP2_5 memory regb8 QI) 1403 1404;**************************************************************** 1405;logical insn 1406;**************************************************************** 1407;mov registers 1408(define-pmacro (move name insn opc1 opc2 op1 op2 mode) 1409 (dni name 1410 (.str name "mov registers" ) 1411 ((PIPE OS) (IDOC MOVE)) 1412 (.str insn " $"op1 ",$"op2) 1413 (+ opc1 opc2 op1 op2) 1414 (set mode op1 op2) 1415 () 1416 ) 1417) 1418(move movr mov OP1_15 OP2_0 dr sr HI) 1419(move movrb movb OP1_15 OP2_1 drb srb HI) 1420 1421;mov register and immediate 1422(define-pmacro (move1 name insn opc1 opc2 op1 op2 mode) 1423 (dni name 1424 (.str name "move" ) 1425 ((PIPE OS) (IDOC MOVE)) 1426 (.str insn " $"op1 ",$hash$"op2) 1427 (+ opc1 opc2 op2 op1) 1428 (set mode op1 op2) 1429 () 1430 ) 1431) 1432(move1 movri mov OP1_14 OP2_0 dri u4 HI) 1433(move1 movbri movb OP1_14 OP2_1 srb u4 QI) 1434 1435; MOV Rwn,#data16 1436(dni movi "move immediate to register" 1437 ((PIPE OS) (IDOC MOVE)) 1438 "mov $reg8,$hash$uimm16" 1439 (+ OP1_14 OP2_6 reg8 uimm16) 1440 (set HI reg8 uimm16) 1441 () 1442) 1443 1444; MOVB reg,#data8 1445(dni movbi "move immediate to register" 1446 ((PIPE OS) (IDOC MOVE)) 1447 "movb $regb8,$hash$uimm8" 1448 (+ OP1_14 OP2_7 regb8 uimm8 (f-op-bit8 0)) 1449 (set QI regb8 uimm8) 1450 () 1451) 1452 1453;move and indirect memory 1454(define-pmacro (mov2 name insn opc1 opc2 op1 op2 mode) 1455 (dni name 1456 (.str name "move" ) 1457 ((PIPE OS) (IDOC MOVE)) 1458 (.str insn " $"op1 ",[$"op2"]") 1459 (+ opc1 opc2 op1 op2) 1460 (set mode op1 (mem HI op2)) 1461 () 1462 ) 1463) 1464(mov2 movr2 mov OP1_10 OP2_8 dr sr HI) 1465(mov2 movbr2 movb OP1_10 OP2_9 drb sr QI) 1466 1467;move and indirect memory 1468(define-pmacro (mov3 name insn opc1 opc2 op1 op2 mode) 1469 (dni name 1470 (.str name "move" ) 1471 ((PIPE OS) (IDOC MOVE)) 1472 (.str insn " [$"op2 "],$"op1) 1473 (+ opc1 opc2 op1 op2) 1474 (set mode op1 (mem HI op2)) 1475 () 1476 ) 1477) 1478(mov3 movri2 mov OP1_11 OP2_8 dr sr HI) 1479(mov3 movbri2 movb OP1_11 OP2_9 drb sr QI) 1480 1481;move and indirect memory 1482(define-pmacro (mov4 name insn opc1 opc2 op1 op2 mode) 1483 (dni name 1484 (.str name "move" ) 1485 ((PIPE OS) (IDOC MOVE)) 1486 (.str insn " [-$"op2 "],$"op1) 1487 (+ opc1 opc2 op1 op2) 1488 (sequence () 1489 (set op1 (sub op2 (const HI 2))) 1490 (set HI (mem HI op2) op1) 1491 ) 1492 () 1493 ) 1494) 1495(mov4 movri3 mov OP1_8 OP2_8 dr sr HI) 1496(mov4 movbri3 movb OP1_8 OP2_9 drb sr QI) 1497 1498;mov register and indirect memory post increment 1499(define-pmacro (mov5 name insn opc1 opc2 op1 op2 mode) 1500 (dni name 1501 (.str name "move" ) 1502 ((PIPE OS) (IDOC MOVE)) 1503 (.str insn " $"op1 ",[$"op2"+]") 1504 (+ opc1 opc2 op1 op2) 1505 (sequence () 1506 (set mode op1 (mem HI op2)) 1507 (set HI op2 (add HI op2 (const 2))) 1508 ) 1509 () 1510 ) 1511) 1512(mov5 mov2i mov OP1_9 OP2_8 dr sr HI) 1513(mov5 movb2i movb OP1_9 OP2_9 drb sr HI) 1514 1515;mov indirect memory 1516(define-pmacro (mov6 name insn opc1 opc2 op1 op2 mode) 1517 (dni name 1518 (.str name "move" ) 1519 ((PIPE OS) (IDOC MOVE)) 1520 (.str insn " [$"op1 "],[$"op2"]") 1521 (+ opc1 opc2 op1 op2) 1522 (set HI (mem HI op1) (mem HI op2)) 1523 () 1524 ) 1525) 1526(mov6 mov6i mov OP1_12 OP2_8 dr sr HI) 1527(mov6 movb6i movb OP1_12 OP2_9 dr sr HI) 1528 1529;mov indirect memory 1530(define-pmacro (mov7 name insn opc1 opc2 op1 op2 mode) 1531 (dni name 1532 (.str name "move" ) 1533 ((PIPE OS) (IDOC MOVE)) 1534 (.str insn " [$"op1 "+],[$"op2"]") 1535 (+ opc1 opc2 op1 op2) 1536 (sequence () 1537 (set mode (mem mode op1) (mem mode op2)) 1538 (set mode op1 (add mode op1 (const mode 2))) 1539 ) 1540 () 1541 ) 1542) 1543(mov7 mov7i mov OP1_13 OP2_8 dr sr HI) 1544(mov7 movb7i movb OP1_13 OP2_9 dr sr HI) 1545 1546;mov indirect memory 1547(define-pmacro (mov8 name insn opc1 opc2 op1 op2 mode) 1548 (dni name 1549 (.str name "move" ) 1550 ((PIPE OS) (IDOC MOVE)) 1551 (.str insn " [$"op1 "],[$"op2"+]") 1552 (+ opc1 opc2 op1 op2) 1553 (sequence () 1554 (set mode (mem mode op1) (mem mode op2)) 1555 (set mode op2 (add mode op2 (const mode 2))) 1556 ) 1557 () 1558 ) 1559) 1560(mov8 mov8i mov OP1_14 OP2_8 dr sr HI) 1561(mov8 movb8i movb OP1_14 OP2_9 dr sr HI) 1562 1563;mov indirect memory 1564(define-pmacro (mov9 name insn opc1 opc2 op1 op2 mode) 1565 (dni name 1566 (.str name "move" ) 1567 ((PIPE OS) (IDOC MOVE)) 1568 (.str insn " $"op1 ",[$"op2"+$hash$"uimm16"]") 1569 (+ opc1 opc2 op1 op2 uimm16) 1570 (sequence ((mode tmp1)) 1571 (set mode tmp1 (add HI op2 uimm16)) 1572 (set mode op1 (mem HI tmp1)) 1573 ) 1574 () 1575 ) 1576) 1577(mov9 mov9i mov OP1_13 OP2_4 dr sr HI) 1578(mov9 movb9i movb OP1_15 OP2_4 drb sr QI) 1579 1580;mov indirect memory 1581(define-pmacro (mov10 name insn opc1 opc2 op1 op2 mode) 1582 (dni name 1583 (.str name "move" ) 1584 ((PIPE OS) (IDOC MOVE)) 1585 (.str insn " [$"op2"+$hash$"uimm16 "],$"op1) 1586 (+ opc1 opc2 op1 op2 uimm16) 1587 (sequence ((mode tmp1)) 1588 (set mode tmp1 (add HI op1 uimm16)) 1589 (set mode (mem HI tmp1) op1) 1590 ) 1591 () 1592 ) 1593) 1594(mov10 mov10i mov OP1_12 OP2_4 dr sr HI) 1595(mov10 movb10i movb OP1_14 OP2_4 drb sr QI) 1596 1597;move and indirect memory 1598(define-pmacro (mov11 name insn opc1 opc2 op1 op2 mode) 1599 (dni name 1600 (.str name "move" ) 1601 ((PIPE OS) (IDOC MOVE)) 1602 (.str insn " [$"op1 "],$"op2) 1603 (+ opc1 opc2 (f-op-lbit4 0) op1 op2) 1604 (set (mem mode op1) (mem HI op2)) 1605 () 1606 ) 1607) 1608(mov11 movri11 mov OP1_8 OP2_4 src2 memory HI) 1609(mov11 movbri11 movb OP1_10 OP2_4 src2 memory HI) 1610 1611;move and indirect memory 1612(define-pmacro (mov12 name insn opc1 opc2 op1 op2 mode) 1613 (dni name 1614 (.str name "move" ) 1615 ((PIPE OS) (IDOC MOVE)) 1616 (.str insn " $"op2 ",[$"op1"]") 1617 (+ opc1 opc2 (f-op-lbit4 0) op1 op2) 1618 (set (mem HI op2) (mem mode op1)) 1619 () 1620 ) 1621) 1622(mov12 movri12 mov OP1_9 OP2_4 src2 memory HI) 1623(mov12 movbri12 movb OP1_11 OP2_4 src2 memory HI) 1624 1625(define-pmacro (movemem3 name insn opc1 opc2 op1 op2 dir) 1626 (dni name 1627 (.str name "move" ) 1628 ((PIPE OS) (IDOC MOVE)) 1629 (.str insn " $"op1 ",$hash$"dir"$"op2) 1630 (+ opc1 opc2 op1 op2) 1631 (set HI op1 op2) 1632 () 1633 ) 1634) 1635(movemem3 movehm5 mov OP1_14 OP2_6 regoff8 upof16 "pof") 1636(movemem3 movehm6 mov OP1_14 OP2_6 regoff8 upag16 "pag") 1637(movemem3 movehm7 mov OP1_14 OP2_6 regoff8 useg16 "segm") 1638(movemem3 movehm8 mov OP1_14 OP2_6 regoff8 usof16 "sof") 1639 1640(define-pmacro (movemem4 name insn opc1 opc2 op1 op2 dir) 1641 (dni name 1642 (.str name "move" ) 1643 ((PIPE OS) (IDOC MOVE)) 1644 (.str insn " $"op1 ",$hash$"dir"$"op2) 1645 (+ opc1 opc2 op1 op2 (f-op-bit8 0)) 1646 (set QI op1 op2) 1647 () 1648 ) 1649) 1650(movemem4 movehm9 movb OP1_14 OP2_7 regb8 uimm8 "pof") 1651(movemem4 movehm10 movb OP1_14 OP2_7 regoff8 uimm8 "pag") 1652 1653(define-pmacro (movemem name insn opc1 opc2 op1 op2 mode dir) 1654 (dni name 1655 (.str name "move" ) 1656 ((PIPE OS) (IDOC MOVE)) 1657 (.str insn " $"op1 ",$"dir"$"op2) 1658 (+ opc1 opc2 op1 op2) 1659 (set mode op1 (mem HI op2)) 1660 () 1661 ) 1662) 1663(movemem movrmp mov OP1_15 OP2_2 regoff8 upof16 HI "pof") 1664(movemem movrmp1 movb OP1_15 OP2_3 regb8 upof16 QI "pof") 1665(movemem movrmp2 mov OP1_15 OP2_2 regoff8 upag16 HI "pag") 1666(movemem movrmp3 movb OP1_15 OP2_3 regb8 upag16 QI "pag") 1667 1668(define-pmacro (movemem1 name insn opc1 opc2 op1 op2 dir) 1669 (dni name 1670 (.str name "move" ) 1671 ((PIPE OS) (IDOC MOVE)) 1672 (.str insn " $"dir"$"op1 ",$"op2) 1673 (+ opc1 opc2 op2 op1) 1674 (set (mem HI op1) op2 ) 1675 () 1676 ) 1677) 1678(movemem1 movrmp4 mov OP1_15 OP2_6 upof16 regoff8 "pof") 1679(movemem1 movrmp5 movb OP1_15 OP2_7 upof16 regb8 "pof") 1680 1681(define-pmacro (movemem2 name insn opc1 opc2 op1 op2 mode dir) 1682 (dni name 1683 (.str name "move" ) 1684 ((PIPE OS) (IDOC MOVE)) 1685 (.str insn " $"op1 ",$hash$"dir"$"op2) 1686 (+ opc1 opc2 op2 op1) 1687 (set mode op1 op2) 1688 () 1689 ) 1690) 1691(movemem2 movehm1 mov OP1_14 OP2_0 dri u4 HI "pof") 1692(movemem2 movehm2 movb OP1_14 OP2_1 srb u4 QI "pof") 1693(movemem2 movehm3 mov OP1_14 OP2_0 dri u4 HI "pag") 1694(movemem2 movehm4 movb OP1_14 OP2_1 srb u4 QI "pag") 1695 1696;move register and direct memory 1697(define-pmacro (move12 name insn opc1 opc2 op1 op2 mode) 1698 (dni name 1699 (.str name "move" ) 1700 ((PIPE OS) (IDOC MOVE)) 1701 (.str insn " $"op1 ",$"op2) 1702 (+ opc1 opc2 op1 op2) 1703 (set mode op1 (mem HI op2)) 1704 () 1705 ) 1706) 1707 1708;move register and direct memory 1709(define-pmacro (move13 name insn opc1 opc2 op1 op2 mode) 1710 (dni name 1711 (.str name "move" ) 1712 ((PIPE OS) (IDOC MOVE)) 1713 (.str insn " $"op1 ",$"op2) 1714 (+ opc1 opc2 op2 op1) 1715 (set (mem HI op1) op2) 1716 () 1717 ) 1718) 1719(move12 mve12 mov OP1_15 OP2_2 regmem8 memgr8 HI) 1720(move13 mve13 mov OP1_15 OP2_6 memgr8 regmem8 HI) 1721(move12 mover12 mov OP1_15 OP2_2 reg8 memory HI) 1722(move13 mvr13 mov OP1_15 OP2_6 memory reg8 HI) 1723(move12 mver12 movb OP1_15 OP2_3 regbmem8 memgr8 QI) 1724(move13 mver13 movb OP1_15 OP2_7 memgr8 regbmem8 QI) 1725(move12 movr12 movb OP1_15 OP2_3 regb8 memory QI) 1726(move13 movr13 movb OP1_15 OP2_7 memory regb8 QI) 1727 1728; MOVBS Rw,Rb 1729(dni movbsrr "mov byte register with sign extension to word register" 1730 ((PIPE OS) (IDOC MOVE)) 1731 "movbs $sr,$drb" 1732 (+ OP1_13 OP2_0 drb sr) 1733 (sequence () 1734 (if (and QI drb (const 128)) 1735 (set HI sr (or HI (const HI 65280) drb))) 1736 (set HI sr (and HI (const HI 255) drb)) 1737 ) 1738 () 1739) 1740 1741; MOVBZ Rw,Rb 1742(dni movbzrr "mov byte register with zero extension to word register" 1743 ((PIPE OS) (IDOC MOVE)) 1744 "movbz $sr,$drb" 1745 (+ OP1_12 OP2_0 drb sr) 1746 (set HI sr (and HI (const HI 255) drb)) 1747 () 1748) 1749 1750; MOVBS reg,POF mem 1751(dni movbsrpofm "mov memory to byte register" 1752 ((PIPE OS) (IDOC MOVE)) 1753 "movbs $regmem8,$pof$upof16" 1754 (+ OP1_13 OP2_2 regmem8 upof16) 1755 (set QI regmem8 (mem HI upof16)) 1756 () 1757) 1758 1759; MOVBS pof,reg 1760(dni movbspofmr "mov memory to byte register" 1761 ((PIPE OS) (IDOC MOVE)) 1762 "movbs $pof$upof16,$regbmem8" 1763 (+ OP1_13 OP2_5 upof16 regbmem8 ) 1764 (set QI (mem HI upof16) regbmem8) 1765 () 1766) 1767 1768; MOVBZ reg,POF mem 1769(dni movbzrpofm "mov memory to byte register" 1770 ((PIPE OS) (IDOC MOVE)) 1771 "movbz $reg8,$pof$upof16" 1772 (+ OP1_12 OP2_2 reg8 upof16) 1773 (set QI reg8 (mem HI upof16)) 1774 () 1775) 1776 1777; MOVBZ pof,reg 1778(dni movbzpofmr "mov memory to byte register" 1779 ((PIPE OS) (IDOC MOVE)) 1780 "movbz $pof$upof16,$regb8" 1781 (+ OP1_12 OP2_5 upof16 regb8 ) 1782 (set QI (mem HI upof16) regb8) 1783 () 1784) 1785 1786;move register and direct memory 1787(define-pmacro (move14 name insn opc1 opc2 op1 op2 ) 1788 (dni name 1789 (.str name "move" ) 1790 ((PIPE OS) (IDOC MOVE)) 1791 (.str insn " $"op1 ",$"op2) 1792 (+ opc1 opc2 op1 op2) 1793 (set HI op1 (and HI (const HI 255) (mem QI op2))) 1794 () 1795 ) 1796) 1797 1798;move register and direct memory 1799(define-pmacro (move15 name insn opc1 opc2 op1 op2 ) 1800 (dni name 1801 (.str name "move" ) 1802 ((PIPE OS) (IDOC MOVE)) 1803 (.str insn " $"op1 ",$"op2) 1804 (+ opc1 opc2 op2 op1) 1805 (set HI (mem HI op1) (and HI (const HI 255) op2)) 1806 () 1807 ) 1808) 1809(move14 movebs14 movbs OP1_13 OP2_2 regmem8 memgr8 ) 1810(move15 movebs15 movbs OP1_13 OP2_5 memgr8 regbmem8 ) 1811(move14 moverbs14 movbs OP1_13 OP2_2 reg8 memory ) 1812(move15 movrbs15 movbs OP1_13 OP2_5 memory regb8 ) 1813(move14 movebz14 movbz OP1_12 OP2_2 regmem8 memgr8 ) 1814(move15 movebz15 movbz OP1_12 OP2_5 memgr8 regbmem8 ) 1815(move14 moverbz14 movbz OP1_12 OP2_2 reg8 memory ) 1816(move15 movrbz15 movbz OP1_12 OP2_5 memory regb8 ) 1817 1818 1819;mov registers 1820(define-pmacro (moveb1 name insn opc1 opc2 op1 op2) 1821 (dni name 1822 (.str name "move" ) 1823 ((PIPE OS) (IDOC MOVE)) 1824 (.str insn " $"op2 ",$"op1) 1825 (+ opc1 opc2 op1 op2) 1826 (sequence () 1827 (if (and QI op1 (const 128)) 1828 (set HI op2 (or HI (const HI 65280) op1))) 1829 (set HI op2 (and HI (const HI 255) op1)) 1830 ) 1831 () 1832 ) 1833) 1834(moveb1 movrbs movbs OP1_13 OP2_0 drb sr ) 1835(moveb1 movrbz movbz OP1_12 OP2_0 drb sr ) 1836 1837 1838 1839;jump and call insns 1840;****************************************************************** 1841;Absolute conditional jump 1842(define-pmacro (jmpabs name insn) 1843 (dni name 1844 (.str name "Absolute conditional jump" ) 1845 ((PIPE OS) (IDOC JMP)) 1846 (.str insn " $extcond,$caddr") 1847 (+ OP1_14 OP2_10 extcond (f-op-bitone 0) bitone bit01 caddr) 1848 (sequence ((HI tmp1) (HI tmp2)) 1849 (set tmp1 (mem HI caddr)) 1850 (set tmp2 (sub HI pc (mem HI caddr))) 1851 (if (gt tmp2 (const 0)) ;; FIXME: (lt tmp2 (const 32)) (eq tmp2 (const 32)) 1852 (set bitone (const 1))) 1853 (if (lt tmp2 (const 0)) ;; FIXME: (eq tmp2 (const 0)) (gt tmp2 (const 32)) 1854 (set bitone (const 0))) 1855 (if (eq extcond (const 1)) ;; FIXME: (ne extcond cc_Z)) 1856 (set bit01 (const 0)) 1857 (set HI pc (mem HI caddr))) 1858 (if (ne extcond (const 1)) ;; FIXME: (eq extcond cc_Z)) 1859 (set bit01 (const 1)) 1860 (set HI pc (add HI pc (const 2)))) 1861 ) 1862 () 1863 ) 1864) 1865 1866(jmpabs jmpa0 jmpa+) 1867(jmpabs jmpa1 jmpa) 1868 1869; JMPA- cc,caddr 1870(dni jmpa- "Absolute conditional jump" 1871 (COND-CTI (PIPE OS) (IDOC JMP)) 1872 "jmpa- $extcond,$caddr" 1873 (+ OP1_14 OP2_10 extcond (f-op-bitone 0) bitone (f-op-1bit 1) caddr) 1874 (sequence ((HI tmp1) (HI tmp2)) 1875 (set tmp1 (mem HI caddr)) 1876 (set tmp2 (sub HI pc (mem HI caddr))) 1877 (if (gt tmp2 (const 0)) ;; FIXME: (lt tmp2 (const 32)) (eq tmp2 (const 32)) 1878 (set bitone (const 1))) 1879 (if (lt tmp2 (const 0)) ;; FIXME: (eq tmp2 (const 0)) (gt tmp2 (const 32)) 1880 (set bitone (const 0))) 1881 (set HI pc (add HI pc (const 2))) 1882 ) 1883 () 1884) 1885 1886; JMPI cc,[Rwn] 1887(dni jmpi "Indirect conditional jump" 1888 (COND-CTI (PIPE OS) (IDOC JMP)) 1889 "jmpi $icond,[$sr]" 1890 (+ OP1_9 OP2_12 icond sr) 1891 (sequence () 1892 (if (eq icond (const 1)) 1893 (set HI pc (mem HI sr))) 1894 (set HI pc (add HI pc (const 2))) 1895 ) 1896 () 1897) 1898 1899(define-pmacro (jmprel name insn opc1) 1900 (dni name 1901 (.str name "conditional" ) 1902 (COND-CTI (PIPE OS) (IDOC JMP)) 1903 (.str insn " $cond,$rel") 1904 (+ opc1 OP2_13 rel) 1905 (sequence () 1906 (if (eq cond (const 1)) 1907 (sequence () 1908 (if (lt QI rel (const 0)) 1909 (sequence () 1910 ;; FIXME: (neg QI rel) 1911 ;; FIXME: (add QI rel (const 1)) 1912 ;; FIXME: (mul QI rel (const 2)) 1913 (set HI pc (sub HI pc rel)) 1914 )) 1915 (set HI pc (add HI pc (mul QI rel (const 2)))) 1916 ) 1917 ) 1918 (set HI pc pc) 1919 ) 1920 () 1921 ) 1922) 1923 1924(jmprel jmpr_nenz jmpr COND_NE_NZ ) 1925(jmprel jmpr_sgt jmpr COND_SGT ) 1926(jmprel jmpr_z jmpr COND_Z ) 1927(jmprel jmpr_v jmpr COND_V ) 1928(jmprel jmpr_nv jmpr COND_NV ) 1929(jmprel jmpr_n jmpr COND_N ) 1930(jmprel jmpr_nn jmpr COND_NN ) 1931(jmprel jmpr_c jmpr COND_C ) 1932(jmprel jmpr_nc jmpr COND_NC ) 1933(jmprel jmpr_eq jmpr COND_EQ ) 1934(jmprel jmpr_ne jmpr COND_NE ) 1935(jmprel jmpr_ult jmpr COND_ULT ) 1936(jmprel jmpr_ule jmpr COND_ULE ) 1937(jmprel jmpr_uge jmpr COND_UGE ) 1938(jmprel jmpr_ugt jmpr COND_UGT ) 1939(jmprel jmpr_sle jmpr COND_SLE ) 1940(jmprel jmpr_sge jmpr COND_SGE ) 1941(jmprel jmpr_net jmpr COND_NET ) 1942(jmprel jmpr_uc jmpr COND_UC ) 1943(jmprel jmpr_slt jmpr COND_SLT ) 1944 1945 1946 1947 1948; JMPS seg,caddr 1949(dni jmpseg "absolute inter-segment jump" 1950 (UNCOND-CTI(PIPE OS) (IDOC JMP)) 1951 "jmps $hash$segm$useg8,$hash$sof$usof16" 1952 (+ OP1_15 OP2_10 seg usof16) 1953 (sequence () 1954 (if (eq BI sgtdisbit (const BI 0)) 1955 (set QI (reg h-cr 10) useg8)) 1956 ;; FIXME: previous indentation suggested this nop was the `else' 1957 ;; clause of the previous `if'. 1958 (nop) 1959 (set HI pc usof16) 1960 ) 1961 () 1962) 1963 1964; JMPS seg,caddr 1965(dni jmps "absolute inter-segment jump" 1966 (UNCOND-CTI(PIPE OS) (IDOC JMP)) 1967 "jmps $seg,$caddr" 1968 (+ OP1_15 OP2_10 seg caddr) 1969 (sequence () 1970 (if (eq BI sgtdisbit (const BI 0)) 1971 (set QI (reg h-cr 10) seg)) 1972 ;; FIXME: previous indentation suggested this nop was the `else' 1973 ;; clause of the previous `if'. 1974 (nop) 1975 (set HI pc caddr) 1976 ) 1977 () 1978) 1979 1980 1981;relative jump if bit set 1982;JB bitaddrQ.q,rel 1983(dni jb "relative jump if bit set" 1984 ((PIPE OS) (IDOC JMP)) 1985 "jb $genreg$dot$qlobit,$relhi" 1986 (+ OP1_8 OP2_10 genreg relhi qlobit (f-qhibit 0)) 1987 (sequence ((HI tmp1) (HI tmp2)) 1988 (set HI tmp1 genreg) 1989 (set HI tmp2 (const 1)) 1990 ;;(sll HI tmp2 qlobit) - FIXME: missing (set ...) 1991 (set HI tmp2 (and tmp1 tmp2)) 1992 (if (eq tmp2 (const 1)) ;; FIXME: (ne tmp2 0)? 1993 (sequence () 1994 (if (lt QI relhi (const 0)) 1995 (set HI pc (add HI pc (mul QI relhi (const 2))))) 1996 )) 1997 (set HI pc (add HI pc (const 4))) ;; FIXME: Is this right? 1998 ) 1999 () 2000) 2001 2002;relative jump if bit set and clear bit 2003;JBC bitaddrQ.q,rel 2004(dni jbc "relative jump if bit set and clear bit" 2005 ((PIPE OS) (IDOC JMP)) 2006 "jbc $genreg$dot$qlobit,$relhi" 2007 (+ OP1_10 OP2_10 genreg relhi qlobit (f-qhibit 0)) 2008 (sequence ((HI tmp1) (HI tmp2)) 2009 (set HI tmp1 genreg) 2010 (set HI tmp2 (const 1)) 2011 ;;(sll HI tmp2 qlobit) - FIXME: missing (set ...) 2012 (set HI tmp2 (and tmp1 tmp2)) 2013 (if (eq tmp2 (const 1)) ;; FIXME: (ne tmp2 0)? 2014 (sequence () 2015 ;; FIXME: The `else' clause has several statements. 2016 (if (lt QI relhi (const 0)) 2017 (set tmp2 (const 1)) 2018 (set tmp1 genreg) 2019 ;; FIXME: (sll tmp2 qlobit) 2020 ;; FIXME: (inv tmp2) 2021 (set HI tmp1 (and tmp1 tmp2)) 2022 (set HI genreg tmp1) 2023 (set HI pc (add HI pc (mul QI relhi (const 2))))) 2024 )) 2025 (set HI pc (add HI pc (const 4))) ;; FIXME: Is this right? 2026 ) 2027 () 2028) 2029 2030;relative jump if bit set 2031;JNB bitaddrQ.q,rel 2032(dni jnb "relative jump if bit not set" 2033 ((PIPE OS) (IDOC JMP)) 2034 "jnb $genreg$dot$qlobit,$relhi" 2035 (+ OP1_9 OP2_10 genreg relhi qlobit (f-qhibit 0)) 2036 (sequence ((HI tmp1) (HI tmp2)) 2037 (set HI tmp1 genreg) 2038 (set HI tmp2 (const 1)) 2039 ;;(sll HI tmp2 qlobit) - FIXME: missing (set ...) 2040 (set HI tmp2 (and tmp1 tmp2)) 2041 (if (eq tmp2 (const 0)) ;; FIXME: (ne tmp2 0)? 2042 (sequence () 2043 (if (lt QI relhi (const 0)) 2044 (set HI pc (add HI pc (mul QI relhi (const 2))))) 2045 )) 2046 (set HI pc (add HI pc (const 4))) ;; FIXME: Is this right? 2047 ) 2048 () 2049) 2050 2051;relative jump if bit not set and set bit 2052;JNBS bitaddrQ.q,rel 2053(dni jnbs "relative jump if bit not set and set bit" 2054 ((PIPE OS) (IDOC JMP)) 2055 "jnbs $genreg$dot$qlobit,$relhi" 2056 (+ OP1_11 OP2_10 genreg relhi qlobit (f-qhibit 0)) 2057 (sequence ((HI tmp1) (HI tmp2)) 2058 (set HI tmp1 genreg) 2059 (set HI tmp2 (const 1)) 2060 ;;(sll HI tmp2 qlobit) - FIXME: missing (set ...) 2061 (set HI tmp2 (and tmp1 tmp2)) 2062 (if (eq tmp2 (const 0)) 2063 (sequence () 2064 ;; FIXME: The `else' clause has several statements. 2065 (if (lt QI relhi (const 0)) 2066 (set tmp2 (const 1)) 2067 (set tmp1 reg8) 2068 ;; FIXME: (sll tmp2 qbit) 2069 (set BI tmp1(or tmp1 tmp2)) 2070 (set HI reg8 tmp1) 2071 (set HI pc (add HI pc (mul QI relhi (const 2))))) 2072 )) 2073 (set HI pc (add HI pc (const 4))) ;; FIXME: Is this right? 2074 ) 2075 () 2076) 2077 2078 2079;Absolute conditional call 2080(define-pmacro (callabs name insn) 2081 (dni name 2082 (.str name "Absolute conditional call" ) 2083 ((PIPE OS) (IDOC JMP)) 2084 (.str insn " $extcond,$caddr") 2085 (+ OP1_12 OP2_10 extcond (f-op-2bit 0) bit01 caddr) 2086 (sequence () 2087 (if (eq extcond (const 1)) 2088 (set bit01 (const 0)) 2089 (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) 2090 (set HI (mem HI (reg h-cr 9)) pc) 2091 (set HI pc (mem HI caddr))) 2092 (if (ne extcond (const 1)) 2093 (set bit01 (const 1)) 2094 (set HI pc (add HI pc (const 2)))) 2095 ) 2096 () 2097 ) 2098) 2099 2100(callabs calla0 calla+) 2101(callabs calla1 calla) 2102 2103; CALLA- cc,caddr 2104(dni calla- "Absolute conditional call" 2105 (COND-CTI (PIPE OS) (IDOC JMP)) 2106 "calla- $extcond,$caddr" 2107 (+ OP1_12 OP2_10 extcond (f-op-bit3 1) caddr) 2108 (sequence () 2109 (if (eq extcond (const 1)) 2110 (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) 2111 (set HI (mem HI (reg h-cr 9)) pc) 2112 (set HI pc (mem HI caddr))) 2113 (set HI pc (add HI pc (const 2))) 2114 ) 2115 () 2116) 2117 2118; CALLI cc,[Rwn] 2119(dni calli "indirect subroutine call" 2120 (COND-CTI (PIPE OS) (IDOC JMP)) 2121 "calli $icond,[$sr]" 2122 (+ OP1_10 OP2_11 icond sr) 2123 (sequence () 2124 (if (eq icond (const 1)) 2125 (sequence () 2126 (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) 2127 (set HI (mem HI (reg h-cr 9)) pc) 2128 (set HI pc (mem HI sr)) 2129 ) 2130 ) 2131 (set HI pc (add HI pc (const 2))) 2132 ) 2133 () 2134) 2135 2136; CALLR rel 2137(dni callr "Call subroutine with PC relative signed 8 bit offset" 2138 ( COND-CTI (PIPE OS) (IDOC JMP)) 2139 "callr $rel" 2140 (+ OP1_11 OP2_11 rel) 2141 (sequence () 2142 (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) 2143 (set HI (mem HI (reg h-cr 9)) pc) 2144 (sequence () 2145 (if (lt QI rel (const 0)) 2146 (sequence () 2147 ;; FIXME: (neg QI rel) 2148 ;; FIXME: (add QI rel (const 1)) 2149 ;; FIXME: (mul QI rel (const 2)) 2150 (set HI pc (sub HI pc rel)) 2151 )) 2152 (set HI pc (add HI pc (mul QI rel (const 2)))) 2153 ) 2154 ) 2155 () 2156) 2157 2158 2159; CALLS seg,caddr 2160(dni callseg "call inter-segment subroutine" 2161 (UNCOND-CTI (PIPE OS) (IDOC JMP)) 2162 "calls $hash$segm$useg8,$hash$sof$usof16" 2163 (+ OP1_13 OP2_10 useg8 usof16) 2164 (sequence () 2165 (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) 2166 (set HI (mem HI (reg h-cr 9)) (reg h-cr 10)) 2167 (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) 2168 (set HI (mem HI (reg h-cr 9)) pc) 2169 (if (eq BI sgtdisbit (const BI 0)) 2170 (set QI (reg h-cr 10) useg8)) 2171 ;; FIXME: previous indentation suggested this nop was the `else' 2172 ;; clause of the previous `if'. 2173 (nop) 2174 (set HI pc usof16) 2175 ) 2176 () 2177) 2178 2179; CALLS seg,caddr 2180(dni calls "call inter-segment subroutine" 2181 (UNCOND-CTI (PIPE OS) (IDOC JMP)) 2182 "calls $seg,$caddr" 2183 (+ OP1_13 OP2_10 seg caddr) 2184 (sequence () 2185 (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) 2186 (set HI (mem HI (reg h-cr 9)) (reg h-cr 10)) 2187 (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) 2188 (set HI (mem HI (reg h-cr 9)) pc) 2189 (if (eq BI sgtdisbit (const BI 0)) 2190 (set QI (reg h-cr 10) seg)) 2191 ;; FIXME: previous indentation suggested this nop was the `else' 2192 ;; clause of the previous `if'. 2193 (nop) 2194 (set HI pc caddr) 2195 ) 2196 () 2197) 2198 2199; PCALL reg,caddr 2200(dni pcall "push word and call absolute subroutine" 2201 (UNCOND-CTI (PIPE OS) (IDOC JMP)) 2202 "pcall $reg8,$caddr" 2203 (+ OP1_14 OP2_2 reg8 caddr) 2204 (sequence ((HI tmp1)) 2205 (set HI tmp1 reg8) 2206 (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) 2207 (set HI (mem HI (reg h-cr 9)) tmp1) 2208 (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) 2209 (set HI (mem HI (reg h-cr 9)) pc) 2210 (set HI pc caddr) 2211 ) 2212 () 2213) 2214 2215; TRAP #uimm7 2216(dni trap "software trap" 2217 (UNCOND-CTI (PIPE OS) (IDOC JMP)) 2218 "trap $hash$uimm7" 2219 (+ OP1_9 OP2_11 uimm7 (f-op-1bit 0)) 2220 (sequence () 2221 (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) 2222 (set HI (mem HI (reg h-cr 9)) (reg h-cr 4)) 2223 (if (eq BI sgtdisbit (const BI 0)) 2224 (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) 2225 (set HI (mem HI (reg h-cr 9)) (reg h-cr 10) ) 2226 ) 2227 (nop) 2228 (set HI (reg h-cr 10) (reg h-cr 11)) 2229 (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) 2230 (set HI (mem HI (reg h-cr 9)) pc) 2231 (set HI pc (mul QI uimm7 (const 4))) 2232 ) 2233 () 2234) 2235 2236;Return insns 2237; RET 2238(dni ret "return from subroutine" 2239 (UNCOND-CTI (PIPE OS) (IDOC JMP)) 2240 "ret" 2241 (+ OP1_12 OP2_11 (f-op-bit8 0)) 2242 (sequence () 2243 (set HI pc (mem HI (reg h-cr 9))) 2244 (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2))) 2245 ) 2246 () 2247) 2248 2249; RETS 2250(dni rets "return from inter-segment sunroutine" 2251 (UNCOND-CTI (PIPE OS) (IDOC JMP)) 2252 "rets" 2253 (+ OP1_13 OP2_11 (f-op-bit8 0)) 2254 (sequence () 2255 (set HI pc (mem HI (reg h-cr 9))) 2256 (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2))) 2257 (if (eq BI sgtdisbit (const BI 0)) 2258 (set HI (reg h-cr 10) (mem HI (reg h-cr 9))) 2259 ) 2260 (nop) 2261 (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2))) 2262 ) 2263 () 2264) 2265 2266; RETP reg 2267(dni retp "return from subroutine and pop word register" 2268 (UNCOND-CTI (PIPE OS) (IDOC JMP)) 2269 "retp $reg8" 2270 (+ OP1_14 OP2_11 reg8) 2271 (sequence ((HI tmp1)) 2272 (set HI pc (mem HI (reg h-cr 9))) 2273 (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2))) 2274 (set HI tmp1 (mem HI (reg h-cr 9))) 2275 (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2))) 2276 (set HI reg8 tmp1) 2277 ) 2278 () 2279) 2280 2281; RETI 2282(dni reti "return from ISR" 2283 (UNCOND-CTI (PIPE OS) (IDOC JMP)) 2284 "reti" 2285 (+ OP1_15 OP2_11 (f-op-lbit4 8) (f-op-bit4 8)) 2286 (sequence () 2287 (set HI pc (mem HI (reg h-cr 9))) 2288 (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2))) 2289 (if (eq BI sgtdisbit (const BI 0)) 2290 (sequence () 2291 (set HI (reg h-cr 10) (mem HI (reg h-cr 9))) 2292 (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2))) 2293 ) 2294 ) 2295 (nop) 2296 (set HI (reg h-cr 4) (mem HI (reg h-cr 9))) 2297 (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2))) 2298 ) 2299 () 2300) 2301 2302;stack operation insn 2303;****************************************************************** 2304; POP reg 2305(dni pop "restore register from system stack" 2306 ((PIPE OS) (IDOC MISC)) 2307 "pop $reg8" 2308 (+ OP1_15 OP2_12 reg8) 2309 (sequence ((HI tmp1)) 2310 (set HI tmp1 (mem HI (reg h-cr 9))) 2311 (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2))) 2312 (set HI reg8 tmp1) 2313 ) 2314 () 2315) 2316 2317; PUSH reg 2318(dni push "save register on system stack" 2319 ((PIPE OS) (IDOC MISC)) 2320 "push $reg8" 2321 (+ OP1_14 OP2_12 reg8) 2322 (sequence ((HI tmp1)) 2323 (set HI tmp1 reg8) 2324 (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) 2325 (set HI (mem HI (reg h-cr 9)) tmp1) 2326 ) 2327 () 2328) 2329 2330;context switching insns 2331; SCXT reg,#data16 2332(dni scxti "Push word register on stack and update same with immediate data" 2333 ((PIPE OS) (IDOC MISC)) 2334 "scxt $reg8,$hash$uimm16" 2335 (+ OP1_12 OP2_6 reg8 uimm16) 2336 (sequence ((HI tmp1) (HI tmp2)) 2337 (set HI tmp1 reg8) 2338 (set HI tmp2 uimm16) 2339 ;; FIXME: (sub HI (reg HI h-cr 9) (const 2)) 2340 (set HI (reg HI h-cr 9) tmp1) 2341 (set HI reg8 tmp2) 2342 ) 2343 () 2344) 2345 2346; SCXT reg,POF mem 2347(dni scxtrpofm "mov memory to byte register" 2348 ((PIPE OS) (IDOC MOVE)) 2349 "scxt $reg8,$pof$upof16" 2350 (+ OP1_13 OP2_6 reg8 upof16) 2351 (set QI reg8 (mem HI upof16)) 2352 () 2353) 2354 2355; SCXT regmem8,memgr8 2356(dni scxtmg "Push word register on stack and update same with direct memory" 2357 ((PIPE OS) (IDOC MISC)) 2358 "scxt $regmem8,$memgr8" 2359 (+ OP1_13 OP2_6 regmem8 memgr8) 2360 (sequence ((HI tmp1) (HI tmp2)) 2361 (set HI tmp1 regmem8) 2362 (set HI tmp2 memgr8) 2363 ;; FIXME: (sub HI (reg HI h-cr 9) (const 2)) 2364 (set HI (reg HI h-cr 9) tmp1) 2365 (set HI regmem8 tmp2) 2366 ) 2367 () 2368) 2369 2370; SCXT reg,mem 2371(dni scxtm "Push word register on stack and update same with direct memory" 2372 ((PIPE OS) (IDOC MISC)) 2373 "scxt $reg8,$memory" 2374 (+ OP1_13 OP2_6 reg8 memory) 2375 (sequence ((HI tmp1) (HI tmp2)) 2376 (set HI tmp1 reg8) 2377 (set HI tmp2 memory) 2378 ;; FIXME: (sub HI (reg HI h-cr 9) (const 2)) 2379 (set HI (reg HI h-cr 9) tmp1) 2380 (set HI reg8 tmp2) 2381 ) 2382 () 2383) 2384 2385;No operation 2386; NOP 2387(dni nop "nop" 2388 ((PIPE OS) (IDOC MISC)) 2389 "nop" 2390 (+ OP1_12 OP2_12 (f-op-bit8 0)) 2391 () 2392 () 2393) 2394 2395;*********system control instructions *********************/ 2396 2397(define-pmacro (sysctrl name insn opc1 opc2 op1 op2 op3) 2398 (dni name 2399 (.str name "miscellaneous" ) 2400 ((PIPE OS) (IDOC MISC)) 2401 (.str insn ) 2402 (+ opc1 opc2 (f-op-lbit4 op1) (f-op-bit4 op2) (f-data8 op3) (f-op-bit8 op3)) 2403 () 2404 () 2405 ) 2406) 2407(sysctrl srstm srst OP1_11 OP2_7 4 8 183 ) 2408(sysctrl idlem idle OP1_8 OP2_7 7 8 135) 2409(sysctrl pwrdnm pwrdn OP1_9 OP2_7 6 8 151) 2410(sysctrl diswdtm diswdt OP1_10 OP2_5 5 10 165) 2411(sysctrl enwdtm enwdt OP1_8 OP2_5 7 10 133) 2412(sysctrl einitm einit OP1_11 OP2_5 4 10 181) 2413(sysctrl srvwdtm srvwdt OP1_10 OP2_7 5 8 167 ) 2414 2415;s/w brk 2416; SBRK 2417(dni sbrk "sbrk" 2418 ((PIPE OS) (IDOC MISC)) 2419 "sbrk" 2420 (+ OP1_8 OP2_12 (f-op-bit8 0)) 2421 () 2422 () 2423) 2424 2425; atomic sequence 2426; ATOMIC #irang2 2427(dni atomic "begin atomic sequence" 2428 ((PIPE OS) (IDOC SYSC)) 2429 "atomic $hash$uimm2" 2430 (+ OP1_13 OP2_1 (f-op-lbit2 0) uimm2 (f-op-bit4 0)) 2431 (sequence ((HI count)) 2432 (set HI count uimm2) 2433 (cond 2434 ((ne HI count (const 0)) 2435 (sequence () 2436 (set HI pc (add HI pc (const 2))) 2437 (set HI count (sub HI count (const 1))) 2438 )) 2439 ) 2440 (set HI count (const 0)) 2441 ) 2442 () 2443) 2444 2445;extended register sequence 2446; EXTR #irang2 2447(dni extr "begin extended register sequence" 2448 ((PIPE OS) (IDOC SYSC)) 2449 "extr $hash$uimm2" 2450 (+ OP1_13 OP2_1 (f-op-lbit2 2) uimm2 (f-op-bit4 0)) 2451 (sequence ((HI count)) 2452 (set HI count uimm2) 2453 (cond 2454 ((ne HI count (const 0)) 2455 (sequence () 2456 (set HI pc (add HI pc (const 2))) 2457 (set HI count (sub HI count (const 1))) 2458 )) 2459 ) 2460 (set HI count (const 0)) 2461 ) 2462 () 2463) 2464 2465;extended page sequence 2466; EXTP Rw,#irang2 2467(dni extp "begin extended page sequence" 2468 ((PIPE OS) (IDOC SYSC)) 2469 "extp $sr,$hash$uimm2" 2470 (+ OP1_13 OP2_12 (f-op-lbit2 1) uimm2 sr) 2471 (sequence ((HI count)) 2472 (set HI count uimm2) 2473 (cond 2474 ((ne HI count (const 0)) 2475 (sequence () 2476 (set HI pc (add HI pc (const 2))) 2477 (set HI count (sub HI count (const 1))) 2478 )) 2479 ) 2480 (set HI count (const 0)) 2481 ) 2482 () 2483) 2484 2485;extended page sequence 2486; EXTP #pag10,#irang2 2487(dni extp1 "begin extended page sequence" 2488 ((PIPE OS) (IDOC SYSC)) 2489 "extp $hash$pagenum,$hash$uimm2" 2490 (+ OP1_13 OP2_7 (f-op-lbit2 1) uimm2 (f-op-bit4 0) pagenum (f-qlobit 0) (f-qlobit2 0)) 2491 (sequence ((HI count)) 2492 (set HI count uimm2) 2493 (cond 2494 ((ne HI count (const 0)) 2495 (sequence () 2496 (set HI pc (add HI pc (const 2))) 2497 (set HI count (sub HI count (const 1))) 2498 )) 2499 ) 2500 (set HI count (const 0)) 2501 ) 2502 () 2503) 2504 2505; EXTP #pag10,#irang2 2506(dni extpg1 "begin extended page sequence" 2507 ((PIPE OS) (IDOC SYSC)) 2508 "extp $hash$pag$upag16,$hash$uimm2" 2509 (+ OP1_13 OP2_7 (f-op-lbit2 1) uimm2 (f-op-bit4 0) upag16 ) 2510 (sequence ((HI count)) 2511 (set HI count uimm2) 2512 (cond 2513 ((ne HI count (const 0)) 2514 (sequence () 2515 (set HI pc (add HI pc (const 2))) 2516 (set HI count (sub HI count (const 1))) 2517 )) 2518 ) 2519 (set HI count (const 0)) 2520 ) 2521 () 2522) 2523 2524;extended page and register sequence 2525; EXTPR Rw,#irang2 2526(dni extpr "begin extended page and register sequence" 2527 ((PIPE OS) (IDOC SYSC)) 2528 "extpr $sr,$hash$uimm2" 2529 (+ OP1_13 OP2_12 (f-op-lbit2 3) uimm2 sr) 2530 (sequence ((HI count)) 2531 (set HI count uimm2) 2532 (cond 2533 ((ne HI count (const 0)) 2534 (sequence () 2535 (set HI pc (add HI pc (const 2))) 2536 (set HI count (sub HI count (const 1))) 2537 )) 2538 ) 2539 (set HI count (const 0)) 2540 ) 2541 () 2542) 2543 2544;extended page and register sequence 2545; EXTPR #pag10,#irang2 2546(dni extpr1 "begin extended page sequence" 2547 ((PIPE OS) (IDOC SYSC)) 2548 "extpr $hash$pagenum,$hash$uimm2" 2549 (+ OP1_13 OP2_7 (f-op-lbit2 3) uimm2 (f-op-bit4 0) pagenum (f-qlobit 0) (f-qlobit2 0)) 2550 (sequence ((HI count)) 2551 (set HI count uimm2) 2552 (cond 2553 ((ne HI count (const 0)) 2554 (sequence () 2555 (set HI pc (add HI pc (const 2))) 2556 (set HI count (sub HI count (const 1))) 2557 )) 2558 ) 2559 (set HI count (const 0)) 2560 ) 2561 () 2562) 2563 2564;extended segment sequence 2565; EXTS Rw,#irang2 2566(dni exts "begin extended segment sequence" 2567 ((PIPE OS) (IDOC SYSC)) 2568 "exts $sr,$hash$uimm2" 2569 (+ OP1_13 OP2_12 (f-op-lbit2 0) uimm2 sr) 2570 (sequence ((HI count)) 2571 (set HI count uimm2) 2572 (cond 2573 ((ne HI count (const 0)) 2574 (sequence () 2575 (set HI pc (add HI pc (const 2))) 2576 (set HI count (sub HI count (const 1))) 2577 )) 2578 ) 2579 (set HI count (const 0)) 2580 ) 2581 () 2582) 2583 2584;extended segment sequence 2585; EXTS #seg8,#irang2 2586(dni exts1 "begin extended segment sequence" 2587 ((PIPE OS) (IDOC SYSC)) 2588 "exts $hash$seghi8,$hash$uimm2" 2589 (+ OP1_13 OP2_7 (f-op-lbit2 0) uimm2 (f-op-bit4 0) seghi8 (f-op-bit8 0)) 2590 (sequence ((HI count)) 2591 (set HI count uimm2) 2592 (cond 2593 ((ne HI count (const 0)) 2594 (sequence () 2595 (set HI pc (add HI pc (const 2))) 2596 (set HI count (sub HI count (const 1))) 2597 )) 2598 ) 2599 (set HI count (const 0)) 2600 ) 2601 () 2602) 2603 2604;extended segment register sequence 2605; EXTSR Rwm,#irang2 2606(dni extsr "begin extended segment and register sequence" 2607 ((PIPE OS) (IDOC SYSC)) 2608 "extsr $sr,$hash$uimm2" 2609 (+ OP1_13 OP2_12 (f-op-lbit2 2) uimm2 sr) 2610 (sequence ((HI count)) 2611 (set HI count uimm2) 2612 (cond 2613 ((ne HI count (const 0)) 2614 (sequence () 2615 (set HI pc (add HI pc (const 2))) 2616 (set HI count (sub HI count (const 1))) 2617 )) 2618 ) 2619 (set HI count (const 0)) 2620 ) 2621 () 2622) 2623 2624;extended segment register sequence 2625; EXTSR #pag10,#irang2 2626(dni extsr1 "begin extended segment and register sequence" 2627 ((PIPE OS) (IDOC SYSC)) 2628 "extsr $hash$seghi8,$hash$uimm2" 2629 (+ OP1_13 OP2_7 (f-op-lbit2 2) uimm2 (f-op-bit4 0) seghi8 (f-op-bit8 0)) 2630 (sequence ((HI count)) 2631 (set HI count uimm2) 2632 (cond 2633 ((ne HI count (const 0)) 2634 (sequence () 2635 (set HI pc (add HI pc (const 2))) 2636 (set HI count (sub HI count (const 1))) 2637 )) 2638 ) 2639 (set HI count (const 0)) 2640 ) 2641 () 2642) 2643 2644;prioritize register 2645;PRIOR Rwn,Rwm 2646(dni prior "add registers" 2647 ((PIPE OS) (IDOC ALU)) 2648 "prior $dr,$sr" 2649 (+ OP1_2 OP2_11 dr sr) 2650 (sequence ((HI count) (HI tmp1) (HI tmp2)) 2651 (set HI count (const 0)) 2652 (set HI tmp1 sr) 2653 (set HI tmp2 (and tmp1 (const 32768))) 2654 (cond 2655 ((ne HI tmp2 (const 1)) ;;(ne HI sr (const 0)) - FIXME: and? or? 2656 ;;(sll HI tmp1 (const 1)) - FIXME: missing (set ...) 2657 (set HI tmp2 (and tmp1 (const 32768))) 2658 (set HI count (add HI count (const 1))) 2659 ) 2660 ) 2661 (set HI dr count) 2662 ) 2663 () 2664) 2665 2666 2667;bit instructions 2668;****************************************************************** 2669;bit clear 2670(define-pmacro (bclear name insn opc1) 2671 (dni name 2672 (.str name "bit clear" ) 2673 ((PIPE OS) (IDOC ALU)) 2674 (.str insn " $reg8$dot$qbit") 2675 (+ opc1 OP2_14 reg8) 2676 (sequence ((HI tmp1) (HI tmp2)) 2677 (set tmp2 (const 1)) 2678 (set tmp1 reg8) 2679 ;; FIXME: (sll tmp2 qbit) 2680 ;; FIXME: (inv tmp2) 2681 (set BI tmp1(and tmp1 tmp2)) 2682 (set HI reg8 tmp1)) 2683 () 2684 ) 2685) 2686 2687;clear direct bit 2688(dni bclr18 "bit logical MOVN" 2689 ((PIPE OS) (IDOC ALU)) 2690 "bclr $RegNam" 2691 (+ OP1_11 OP2_14 RegNam) 2692 (sequence ((HI tmp1) (HI tmp2)) 2693 (set tmp2 (const 1)) 2694 (set tmp1 reg8) 2695 ;; FIXME: (sll tmp2 qbit) 2696 ;; FIXME: (inv tmp2) 2697 (set BI tmp1(and tmp1 tmp2)) 2698 (set HI reg8 tmp1)) 2699 () 2700) 2701 2702 2703(bclear bclr0 bclr QBIT_0 ) 2704(bclear bclr1 bclr QBIT_1 ) 2705(bclear bclr2 bclr QBIT_2 ) 2706(bclear bclr3 bclr QBIT_3 ) 2707(bclear bclr4 bclr QBIT_4 ) 2708(bclear bclr5 bclr QBIT_5 ) 2709(bclear bclr6 bclr QBIT_6 ) 2710(bclear bclr7 bclr QBIT_7 ) 2711(bclear bclr8 bclr QBIT_8 ) 2712(bclear bclr9 bclr QBIT_9 ) 2713(bclear bclr10 bclr QBIT_10 ) 2714(bclear bclr11 bclr QBIT_11 ) 2715(bclear bclr12 bclr QBIT_12 ) 2716(bclear bclr13 bclr QBIT_13 ) 2717(bclear bclr14 bclr QBIT_14 ) 2718(bclear bclr15 bclr QBIT_15 ) 2719 2720;set direct bit 2721(dni bset19 "bit logical MOVN" 2722 ((PIPE OS) (IDOC ALU)) 2723 "bset $RegNam" 2724 (+ OP1_11 OP2_15 RegNam) 2725 (sequence ((HI tmp1) (HI tmp2)) 2726 (set tmp2 (const 1)) 2727 (set tmp1 reg8) 2728 ;; FIXME: (sll tmp2 qbit) 2729 (set BI tmp1(or tmp1 tmp2)) 2730 (set HI reg8 tmp1)) 2731 () 2732) 2733 2734;bit set 2735(define-pmacro (bitset name insn opc1) 2736 (dni name 2737 (.str name "bit set" ) 2738 ((PIPE OS) (IDOC ALU)) 2739 (.str insn " $reg8$dot$qbit") 2740 (+ opc1 OP2_15 reg8) 2741 (sequence ((HI tmp1) (HI tmp2)) 2742 (set tmp2 (const 1)) 2743 (set tmp1 reg8) 2744 ;; FIXME: (sll tmp2 qbit) 2745 (set BI tmp1(or tmp1 tmp2)) 2746 (set HI reg8 tmp1)) 2747 () 2748 ) 2749) 2750 2751 2752(bitset bset0 bset QBIT_0 ) 2753(bitset bset1 bset QBIT_1 ) 2754(bitset bset2 bset QBIT_2 ) 2755(bitset bset3 bset QBIT_3 ) 2756(bitset bset4 bset QBIT_4 ) 2757(bitset bset5 bset QBIT_5 ) 2758(bitset bset6 bset QBIT_6 ) 2759(bitset bset7 bset QBIT_7 ) 2760(bitset bset8 bset QBIT_8 ) 2761(bitset bset9 bset QBIT_9 ) 2762(bitset bset10 bset QBIT_10 ) 2763(bitset bset11 bset QBIT_11 ) 2764(bitset bset12 bset QBIT_12 ) 2765(bitset bset13 bset QBIT_13 ) 2766(bitset bset14 bset QBIT_14 ) 2767(bitset bset15 bset QBIT_15 ) 2768 2769;mov direct bit 2770;BMOV bitaddrZ.z,bitaddrQ.q 2771(dni bmov "bit logical MOV" 2772 ((PIPE OS) (IDOC ALU)) 2773 "bmov $reghi8$dot$qhibit,$reg8$dot$qlobit" 2774 (+ OP1_4 OP2_10 reg8 reghi8 qhibit qlobit) 2775 (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4)) 2776 (set HI tmp1 reghi8) 2777 (set HI tmp2 reg8) 2778 (set tmp3 (const 1)) 2779 (set tmp4 (const 1)) 2780 ;; FIXME: (sll tmp3 qlobit) 2781 ;; FIXME: (sll tmp4 qhibit) 2782 ;; FIXME: (and tmp1 tmp3) 2783 ;; FIXME: (and tmp2 tmp4) 2784 (set BI tmp1 tmp2) 2785 (set HI reghi8 tmp1) 2786 (set HI reg8 tmp2)) 2787 () 2788) 2789 2790;movn direct bit 2791;BMOVN bitaddrZ.z,bitaddrQ.q 2792(dni bmovn "bit logical MOVN" 2793 ((PIPE OS) (IDOC ALU)) 2794 "bmovn $reghi8$dot$qhibit,$reg8$dot$qlobit" 2795 (+ OP1_3 OP2_10 reg8 reghi8 qhibit qlobit) 2796 (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4)) 2797 (set HI tmp1 reghi8) 2798 (set HI tmp2 reg8) 2799 (set tmp3 (const 1)) 2800 (set tmp4 (const 1)) 2801 ;; FIXME: (sll tmp3 qlobit) 2802 ;; FIXME: (sll tmp4 qhibit) 2803 ;; FIXME: (and tmp1 tmp3) 2804 ;; FIXME: (and tmp2 tmp4) 2805 ;; FIXME: (inv HI tmp2) 2806 (set BI tmp1 tmp2) 2807 (set HI reghi8 tmp1) 2808 (set HI reg8 tmp2)) 2809 () 2810) 2811 2812;and direct bit 2813;BAND bitaddrZ.z,bitaddrQ.q 2814(dni band "bit logical AND" 2815 ((PIPE OS) (IDOC ALU)) 2816 "band $reghi8$dot$qhibit,$reg8$dot$qlobit" 2817 (+ OP1_6 OP2_10 reg8 reghi8 qhibit qlobit) 2818 (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4)) 2819 (set HI tmp1 reghi8) 2820 (set HI tmp2 reg8) 2821 (set tmp3 (const 1)) 2822 (set tmp4 (const 1)) 2823 ;; FIXME: (sll tmp3 qlobit) 2824 ;; FIXME: (sll tmp4 qhibit) 2825 ;; FIXME: (and tmp1 tmp3) 2826 ;; FIXME: (and tmp2 tmp4) 2827 (set BI tmp1(and tmp1 tmp2)) 2828 (set HI reghi8 tmp1) 2829 (set HI reg8 tmp2)) 2830 () 2831) 2832 2833;or direct bit 2834;BOR bitaddrZ.z,bitaddrQ.q 2835(dni bor "bit logical OR" 2836 ((PIPE OS) (IDOC ALU)) 2837 "bor $reghi8$dot$qhibit,$reg8$dot$qlobit" 2838 (+ OP1_5 OP2_10 reg8 reghi8 qhibit qlobit) 2839 (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4)) 2840 (set HI tmp1 reghi8) 2841 (set HI tmp2 reg8) 2842 (set tmp3 (const 1)) 2843 (set tmp4 (const 1)) 2844 ;; FIXME: (sll tmp3 qlobit) 2845 ;; FIXME: (sll tmp4 qhibit) 2846 ;; FIXME: (and tmp1 tmp3) 2847 ;; FIXME: (and tmp2 tmp4) 2848 (set BI tmp1(or tmp1 tmp2)) 2849 (set HI reghi8 tmp1) 2850 (set HI reg8 tmp2)) 2851 () 2852) 2853 2854;xor direct bit 2855;BXOR bitaddrZ.z,bitaddrQ.q 2856(dni bxor "bit logical XOR" 2857 ((PIPE OS) (IDOC ALU)) 2858 "bxor $reghi8$dot$qhibit,$reg8$dot$qlobit" 2859 (+ OP1_7 OP2_10 reg8 reghi8 qhibit qlobit) 2860 (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4)) 2861 (set HI tmp1 reghi8) 2862 (set HI tmp2 reg8) 2863 (set tmp3 (const 1)) 2864 (set tmp4 (const 1)) 2865 ;; FIXME: (sll tmp3 qlobit) 2866 ;; FIXME: (sll tmp4 qhibit) 2867 ;; FIXME: (and tmp1 tmp3) 2868 ;; FIXME: (and tmp2 tmp4) 2869 (set BI tmp1(xor tmp1 tmp2)) 2870 (set HI reghi8 tmp1) 2871 (set HI reg8 tmp2)) 2872 () 2873) 2874 2875;cmp direct bit to bit 2876;BCMP bitaddrZ.z,bitaddrQ.q 2877(dni bcmp "bit to bit compare" 2878 ((PIPE OS) (IDOC ALU)) 2879 "bcmp $reghi8$dot$qhibit,$reg8$dot$qlobit" 2880 (+ OP1_2 OP2_10 reg8 reghi8 qhibit qlobit) 2881 (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4)) 2882 (set HI tmp1 reghi8) 2883 (set HI tmp2 reg8) 2884 (set tmp3 (const 1)) 2885 (set tmp4 (const 1)) 2886 ;; FIXME: (sll tmp3 qlobit) 2887 ;; FIXME: (sll tmp4 qhibit) 2888 ;; FIXME: (and tmp1 tmp3) 2889 ;; FIXME: (and tmp2 tmp4) 2890 (set BI tmp1(xor tmp1 tmp2)) 2891 (set HI reghi8 tmp1) 2892 (set HI reg8 tmp2)) 2893 () 2894) 2895 2896;bit field low byte 2897;BFLDL op1,op2,op3 2898(dni bfldl "bit field low byte" 2899 ((PIPE OS) (IDOC MOVE)) 2900 "bfldl $reg8,$hash$mask8,$hash$datahi8" 2901 (+ OP1_0 OP2_10 reg8 mask8 datahi8) 2902 (sequence ((HI tmp1) (QI tmp2) (QI tmp3)) 2903 (set HI tmp1 reg8) 2904 (set QI tmp2 mask8) 2905 (set QI tmp3 datahi8) 2906 ;; FIXME: (inv QI tmp2) 2907 (set HI tmp1 (and tmp1 tmp2)) 2908 (set HI tmp1 (or tmp1 tmp3)) 2909 (set HI reg8 tmp1) 2910 ) 2911 () 2912) 2913 2914;bit field high byte 2915;BFLDH op1,op2,op3 2916(dni bfldh "bit field high byte" 2917 ((PIPE OS) (IDOC MOVE)) 2918 "bfldh $reg8,$hash$masklo8,$hash$data8" 2919 (+ OP1_1 OP2_10 reg8 masklo8 data8) 2920 (sequence ((HI tmp1) (HI tmp2) (HI tmp3)) 2921 (set HI tmp1 reg8) 2922 (set QI tmp2 masklo8) 2923 (set HI tmp3 data8) 2924 ;; FIXME: (sll tmp2 (const 8)) 2925 ;; FIXME: (inv HI tmp2) 2926 ;; FIXME: (sll tmp3 (const 8)) 2927 (set HI tmp1 (and tmp1 tmp2)) 2928 (set HI tmp1 (or tmp1 tmp3)) 2929 (set HI reg8 tmp1) 2930 ) 2931 () 2932) 2933 2934;/**********compare instructions****************** 2935 2936;Compare register 2937;CMP Rwn,Rwm 2938(dni cmpr "compare two registers" 2939 ((PIPE OS) (IDOC CMP)) 2940 "cmp $src1,$src2" 2941 (+ OP1_4 OP2_0 src1 src2) 2942 (set condbit (lt HI src1 src2)) 2943 () 2944) 2945 2946;Compare byte register 2947;CMPB Rbn,Rbm 2948(dni cmpbr "compare two byte registers" 2949 ((PIPE OS) (IDOC CMP)) 2950 "cmpb $drb,$srb" 2951 (+ OP1_4 OP2_1 drb srb) 2952 (set condbit (lt QI drb srb)) 2953 () 2954) 2955 2956(define-pmacro (cmp1 name insn opc1 opc2 op1 op2 mode) 2957 (dni name 2958 (.str name "compare" ) 2959 ((PIPE OS) (IDOC CMP)) 2960 (.str insn " $"op1 ",$hash$"op2) 2961 (+ opc1 opc2 op1 (f-op-bit1 0) op2) 2962 (set condbit (lt mode op1 op2)) 2963 () 2964 ) 2965) 2966(cmp1 cmpri cmp OP1_4 OP2_8 src1 uimm3 HI) 2967(cmp1 cmpbri cmpb OP1_4 OP2_9 drb uimm3 QI) 2968 2969; CMP Rwn,#data16 2970(dni cmpi "compare" 2971 ((PIPE OS) (IDOC CMP)) 2972 "cmp $reg8,$hash$uimm16" 2973 (+ OP1_4 OP2_6 reg8 uimm16) 2974 (set condbit (lt HI reg8 uimm16)) 2975 () 2976) 2977 2978; CMPB reg,#data8 2979(dni cmpbi "compare" 2980 ((PIPE OS) (IDOC CMP)) 2981 "cmpb $regb8,$hash$uimm8" 2982 (+ OP1_4 OP2_7 regb8 uimm8 (f-op-bit8 0)) 2983 (set condbit (lt QI regb8 uimm8)) 2984 () 2985) 2986 2987;compare reg and indirect memory 2988(define-pmacro (cmp2 name insn opc1 opc2 op1 op2 mode) 2989 (dni name 2990 (.str name "compare" ) 2991 ((PIPE OS) (IDOC CMP)) 2992 (.str insn " $"op1 ",[$"op2"]") 2993 (+ opc1 opc2 op1 (f-op-bit2 2) op2) 2994 (set condbit (lt mode op1 op2)) 2995 () 2996 ) 2997) 2998(cmp2 cmpr2 cmp OP1_4 OP2_8 dr sr2 HI) 2999(cmp2 cmpbr2 cmpb OP1_4 OP2_9 drb sr2 QI) 3000 3001;compare register and indirect memory post increment 3002(define-pmacro (cmp3 name insn opc1 opc2 op1 op2 mode) 3003 (dni name 3004 (.str name "compare" ) 3005 ((PIPE OS) (IDOC CMP)) 3006 (.str insn " $"op1 ",[$"op2"+]") 3007 (+ opc1 opc2 op1 (f-op-bit2 3) op2) 3008 (sequence () 3009 (set condbit (lt mode op1 op2)) 3010 (set HI op2 (add HI op2 (const 2))) 3011 ) 3012 () 3013 ) 3014) 3015(cmp3 cmp2i cmp OP1_4 OP2_8 dr sr2 HI) 3016(cmp3 cmpb2i cmpb OP1_4 OP2_9 drb sr2 QI) 3017 3018;compare register and direct memory 3019(define-pmacro (cmp4 name insn opc1 opc2 op1 op2 mode) 3020 (dni name 3021 (.str name "compare" ) 3022 ((PIPE OS) (IDOC CMP)) 3023 (.str insn " $"op1 ",$pof$"op2) 3024 (+ opc1 opc2 op1 op2) 3025 (set condbit (lt HI op1 (mem HI op2))) 3026 () 3027 ) 3028) 3029(cmp4 cmp04 cmp OP1_4 OP2_2 reg8 upof16 HI) 3030(cmp4 cmpb4 cmpb OP1_4 OP2_3 regb8 upof16 QI) 3031 3032;compare register and direct memory 3033(define-pmacro (cmp4 name insn opc1 opc2 op1 op2 mode) 3034 (dni name 3035 (.str name "compare" ) 3036 ((PIPE OS) (IDOC CMP)) 3037 (.str insn " $"op1 ",$"op2) 3038 (+ opc1 opc2 op1 op2) 3039 (set condbit (lt HI op1 (mem HI op2))) 3040 () 3041 ) 3042) 3043(cmp4 cmp004 cmp OP1_4 OP2_2 regmem8 memgr8 HI) 3044(cmp4 cmp0004 cmp OP1_4 OP2_2 reg8 memory HI) 3045(cmp4 cmpb04 cmpb OP1_4 OP2_3 regbmem8 memgr8 QI) 3046(cmp4 cmpb004 cmpb OP1_4 OP2_3 regb8 memory QI) 3047 3048;compare register and immediate 3049(define-pmacro (cmp5 name insn opc1 opc2 op1 op2 mode) 3050 (dni name 3051 (.str name "compare" ) 3052 ((PIPE OS) (IDOC CMP)) 3053 (.str insn " $"op1 ",$hash$"op2) 3054 (+ opc1 opc2 op2 op1) 3055 (sequence () 3056 (set condbit (lt HI op1 op2)) 3057 (set mode op1 (sub HI op1 (const 1))) 3058 ) 3059 () 3060 ) 3061) 3062(cmp5 cmpd1ri cmpd1 OP1_10 OP2_0 sr uimm4 HI) 3063(cmp5 cmpd2ri cmpd2 OP1_11 OP2_0 sr uimm4 HI) 3064(cmp5 cmpi1ri cmpi1 OP1_8 OP2_0 sr uimm4 HI) 3065(cmp5 cmpi2ri cmpi2 OP1_9 OP2_0 sr uimm4 HI) 3066(cmp5 cmpd1rim cmpd1 OP1_10 OP2_6 reg8 uimm16 HI) 3067(cmp5 cmpd2rim cmpd2 OP1_11 OP2_6 reg8 uimm16 HI) 3068(cmp5 cmpi1rim cmpi1 OP1_8 OP2_6 reg8 uimm16 HI) 3069(cmp5 cmpi2rim cmpi2 OP1_9 OP2_6 reg8 uimm16 HI) 3070 3071;compare register and direct memory 3072(define-pmacro (cmp6 name insn opc1 opc2 op1 op2 mode ) 3073 (dni name 3074 (.str name "compare" ) 3075 ((PIPE OS) (IDOC CMP)) 3076 (.str insn " $"op1 ",$pof$"op2) 3077 (+ opc1 opc2 op1 op2) 3078 (sequence () 3079 (set condbit (lt HI op1 (mem HI op2))) 3080 (set mode op1 (sub HI op1 (const 1))) 3081 ) 3082 () 3083 ) 3084) 3085(cmp6 cmpd1rp cmpd1 OP1_10 OP2_2 reg8 upof16 HI ) 3086(cmp6 cmpd2rp cmpd2 OP1_11 OP2_2 reg8 upof16 HI ) 3087(cmp6 cmpi1rp cmpi1 OP1_8 OP2_2 reg8 upof16 HI ) 3088(cmp6 cmpi2rp cmpi2 OP1_9 OP2_2 reg8 upof16 HI ) 3089 3090;compare register and direct memory 3091(define-pmacro (cmp7 name insn opc1 opc2 op1 op2 mode) 3092 (dni name 3093 (.str name "compare" ) 3094 ((PIPE OS) (IDOC CMP)) 3095 (.str insn " $"op1 ",$"op2) 3096 (+ opc1 opc2 op1 op2) 3097 (sequence () 3098 (set condbit (lt HI op1 (mem HI op2))) 3099 (set mode op1 (sub HI op1 (const 1))) 3100 ) 3101 () 3102 ) 3103) 3104(cmp7 cmpd1rm cmpd1 OP1_10 OP2_2 regmem8 memgr8 HI) 3105(cmp7 cmpd2rm cmpd2 OP1_11 OP2_2 regmem8 memgr8 HI) 3106(cmp7 cmpi1rm cmpi1 OP1_8 OP2_2 regmem8 memgr8 HI) 3107(cmp7 cmpi2rm cmpi2 OP1_9 OP2_2 regmem8 memgr8 HI) 3108(cmp7 cmpd1rmi cmpd1 OP1_10 OP2_2 reg8 memory HI) 3109(cmp7 cmpd2rmi cmpd2 OP1_11 OP2_2 reg8 memory HI) 3110(cmp7 cmpi1rmi cmpi1 OP1_8 OP2_2 reg8 memory HI) 3111(cmp7 cmpi2rmi cmpi2 OP1_9 OP2_2 reg8 memory HI) 3112 3113 3114;Shift and rotate insns 3115;**************************************************************** 3116(define-pmacro (shift name insn insn1 opc1 opc2 op1 op2 mode) 3117 (dni name 3118 (.str name "shift" ) 3119 ((PIPE OS) (IDOC ALU)) 3120 (.str insn " $"op1 ",$"op2) 3121 (+ opc1 opc2 op1 op2) 3122 (set mode op1 (insn1 mode op1 op2)) 3123 () 3124 ) 3125) 3126(shift shlr shl sll OP1_4 OP2_12 dr sr HI) 3127(shift shrr shr srl OP1_6 OP2_12 dr sr HI) 3128(shift rolr rol rol OP1_0 OP2_12 dr sr HI) 3129(shift rorr ror ror OP1_2 OP2_12 dr sr HI) 3130(shift ashrr ashr sra OP1_10 OP2_12 dr sr HI) 3131 3132(define-pmacro (shift1 name insn insn1 opc1 opc2 op1 op2 mode) 3133 (dni name 3134 (.str name "shift" ) 3135 ((PIPE OS) (IDOC ALU)) 3136 (.str insn " $"op1 ",$hash$"op2) 3137 (+ opc1 opc2 op2 op1) 3138 (set mode op1 (insn1 mode op1 op2)) 3139 () 3140 ) 3141) 3142(shift1 shlri shl sll OP1_5 OP2_12 sr uimm4 HI) 3143(shift1 shrri shr srl OP1_7 OP2_12 sr uimm4 HI) 3144(shift1 rolri rol rol OP1_1 OP2_12 sr uimm4 HI) 3145(shift1 rorri ror ror OP1_3 OP2_12 sr uimm4 HI) 3146(shift1 ashrri ashr sra OP1_11 OP2_12 sr uimm4 HI) 3147