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/toolchain/binutils/binutils-2.25/include/opcode/
Dtic6x-opcode-table.h135 ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
136 ENC(dst, reg, 1)))
140 ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
145 ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
146 ENC(dst, reg, 1)))
152 ENC(dst, reg, 1)))
157 ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
158 ENC(dst, reg, 1)))
163 ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
164 ENC(src2, reg, 1), ENC(dst, reg, 2)))
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/
Dfp_cvt_int.s24 .macro do_cvtf fbits, reg argument
27 SCVTF \reg\()7, W7
28 SCVTF \reg\()7, X7
29 UCVTF \reg\()7, W7
30 UCVTF \reg\()7, X7
34 SCVTF \reg\()7, W7, #\fbits
36 SCVTF \reg\()7, X7, #\fbits
38 UCVTF \reg\()7, W7, #\fbits
40 UCVTF \reg\()7, X7, #\fbits
61 .macro do_fcvt suffix, fbits, reg argument
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Daddsub.s55 .macro do_addsub_ext type, op, Rn, reg, extend, amount
59 \op \reg\()16, \Rn, \reg\()1
62 adjust_rm \op, \reg\()16, \Rn, \reg, 1, \extend
64 adjust_rm \op, \reg\()16, \Rn, \reg, 1, \extend, \amount
71 \op \reg\()ZR, \Rn, \reg\()1
74 adjust_rm \op, \reg\()ZR, \Rn, \reg, 1, \extend
76 adjust_rm \op, \reg\()ZR, \Rn, \reg, 1, \extend, \amount
82 \op \Rn, \reg\()1
85 \op \Rn, \reg\()1, \extend
87 \op \Rn, \reg\()1, \extend #\amount
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Dldst-reg-uns-imm.s33 .macro op2_no_imm op, reg argument
34 \op \reg\()7, [sp]
37 .macro op2 op, reg, simm
38 \op \reg\()7, [sp, #\simm]
43 .macro ld_or_st op, suffix, reg, size
45 op2 \op\suffix, \reg, \simm
47 op2_no_imm \op\suffix, \reg
49 op2 \op\suffix, \reg, \simm
51 op2 \op\suffix, \reg, "(4095*\size)"
56 .irp reg, b, h, s, d, q
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Dneon-ins.s3 .macro iterate_regs_types macro_name reg argument
6 \macro_name \regs b \index \reg
12 \macro_name \regs h \index \reg
18 \macro_name \regs s \index \reg
34 iterate_regs_types macro_name=ins_mov_main reg=w
37 .irp reg, 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
38 ins v\reg\().d[0], x\reg
39 mov v\reg\().d[0], x\reg
40 ins v\reg\().d[1], x\reg
41 mov v\reg\().d[1], x\reg
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Dneon-fp-cvt-int.s24 .macro do_cvt op, fbits, reg, reg_shape
27 .ifc \reg, V
30 \op \reg\()7, \reg\()7
34 .ifc \reg, V
47 .ifc \reg, S
52 .ifc \reg, D
78 .irp reg, S, D
79 do_cvt FCVTNS, \fbits, \reg
80 do_cvt FCVTNU, \fbits, \reg
81 do_cvt FCVTPS, \fbits, \reg
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Dbitfield-bfm.s50 .macro op_bfm signed, reg, immr, imms
51 \signed\()bfm \reg\()zr, \reg\()7, #\immr, #\imms // e.g. sbfm xzr, x7, #0, #15
54 .macro ext2bfm signed, reg, imms
55 op_bfm signed=\signed, reg=\reg, immr=0, imms=\imms
59 .macro sr2bfm signed, reg, shift, imms
60 op_bfm signed=\signed, reg=\reg, immr=\shift, imms=\imms
64 .macro sl2bfm signed, reg, shift
65 .ifc \reg, w
66 op_bfm signed=\signed, reg=\reg, immr="((32-\shift)&31)", imms="(31-\shift)"
68 op_bfm signed=\signed, reg=\reg, immr="((64-\shift)&63)", imms="(63-\shift)"
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Dldst-reg-pair.s30 .macro op3_offset op, reg, imm
31 \op \reg\()7, \reg\()15, [sp, #\imm]
35 .macro op3_post_ind op, reg, imm
36 \op \reg\()7, \reg\()15, [sp], #\imm
40 .macro op3_pre_ind op, reg, imm
41 \op \reg\()7, \reg\()15, [sp, #\imm]!
44 .macro op3 op, reg, size, type
49 op3_offset \op, \reg, "(\imm7*\size)"
53 op3_post_ind \op, \reg, "(\imm7*\size)"
57 op3_pre_ind \op, \reg, "(\imm7*\size)"
Dldst-reg-unscaled-imm.s31 .macro op2_no_imm op, reg argument
32 \op \reg\()7, [sp]
35 .macro op2 op, reg, simm
36 \op \reg\()7, [sp, #\simm]
40 .macro ld_or_st op, suffix, reg argument
42 op2 \op\suffix, \reg, \simm
44 op2_no_imm \op\suffix, \reg
46 op2 \op\suffix, \reg, \simm
52 .irp reg, b, h, s, d, q
54 op2 \op, \reg, \simm
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Dldst-reg-reg-offset.s26 .macro op3_32 op, reg, ext, imm
28 \op \reg\()7, [sp, w7, \ext]
30 \op \reg\()7, [sp, w7, \ext #\imm]
34 .macro op3_64 op, reg, ext, imm
36 \op \reg\()7, [sp, x7, \ext]
38 \op \reg\()7, [sp, x7, \ext #\imm]
42 .macro op3 op, reg, ext, imm=-1
44 op3_32 \op, \reg, \ext, \imm
47 op3_32 \op, \reg, \ext, \imm
52 op3_64 \op, \reg, \ext, \imm
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/toolchain/binutils/binutils-2.25/opcodes/
Dscore-dis.c567 long reg; in print_insn_score48() local
569 reg = given >> bitstart; in print_insn_score48()
570 reg &= (2 << (bitend - bitstart)) - 1; in print_insn_score48()
572 func (stream, "%s", score_regnames[reg]); in print_insn_score48()
577 long reg; in print_insn_score48() local
579 reg = given >> bitstart; in print_insn_score48()
580 reg &= (2 << (bitend - bitstart)) - 1; in print_insn_score48()
582 func (stream, "%ld", reg); in print_insn_score48()
587 long reg; in print_insn_score48() local
588 reg = given >> bitstart; in print_insn_score48()
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Dscore7-dis.c615 long reg; in print_insn_score32() local
617 reg = given >> bitstart; in print_insn_score32()
618 reg &= (2 << (bitend - bitstart)) - 1; in print_insn_score32()
620 func (stream, "%s", score_regnames[reg]); in print_insn_score32()
625 long reg; in print_insn_score32() local
627 reg = given >> bitstart; in print_insn_score32()
628 reg &= (2 << (bitend - bitstart)) - 1; in print_insn_score32()
630 func (stream, "%ld", reg); in print_insn_score32()
635 long reg; in print_insn_score32() local
637 reg = given >> bitstart; in print_insn_score32()
[all …]
/toolchain/binutils/binutils-2.25/gas/config/
Dtc-mcore.c492 parse_reg (char * s, unsigned * reg) in parse_reg() argument
502 *reg = 10 + s[2] - '0'; in parse_reg()
508 *reg = s[1] - '0'; in parse_reg()
516 * reg = 0; in parse_reg()
548 parse_creg (char * s, unsigned * reg) in parse_creg() argument
560 *reg = 30 + s[3] - '0'; in parse_creg()
566 *reg = 20 + s[3] - '0'; in parse_creg()
572 *reg = 10 + s[3] - '0'; in parse_creg()
578 *reg = s[2] - '0'; in parse_creg()
597 *reg = cregs[i].crnum; in parse_creg()
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Dm68k-parse.y97 enum m68k_register reg; member
104 %token <reg> DR AR FPR FPCR LPC ZAR ZDR LZPC CREG
109 %type <reg> zadr zdr apc zapc zpc optzapc optczapc
155 op->reg = $1;
160 op->reg = $1;
165 op->reg = $1;
170 op->reg = $1;
175 op->reg = $1;
208 op->reg = $2;
213 op->reg = $2;
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/rx/
Dmov.sm3 mov.L #{uimm4},{reg}
7 mov.L #{uimm8},{reg}
8 mov.L #{imm},{reg}
9 mov{bwl} {reg1},{reg}
16 mov{bwl} {mem},{reg}
17 mov{bwl} [{reg},{reg}],{reg}
20 mov{bwl} {reg},[{reg},{reg}]
24 mov{bwl} {reg},[{reg}+]
25 mov{bwl} [{reg}+],{reg}
26 mov{bwl} {reg},[-{reg}]
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Dadd.sm1 add #{uimm4},{reg}
2 add #{imm},{reg}
4 add {reg},{reg}
5 add {memx},{reg}
7 add #{imm},{reg},{reg}
8 add {reg},{reg},{reg}
Dmovu.sm3 movu{bw} {reg},{reg}
5 movu{bw} {mem},{reg}
6 movu{bw} [{reg},{reg}],{reg}
8 movu{bw} [{reg}+],{reg}
9 movu{bw} [-{reg}],{reg}
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/
Dx86-64-opcode.s6 CALLq *(%r8) # -- -- -- 41 FF 10 ; REX to access upper reg.
8 CALLq *(%r8) # -- -- -- 41 FF 10 ; REX to access upper reg.
23 MOVw %cs,(%r8) # -- -- -- 41 8C 08 ; REX to access upper reg.
25 MOVw %ss,(%r8) # -- -- -- 41 8C 10 ; REX to access upper reg.
27 MOVw %fs,(%r8) # -- -- -- 41 8C 20 ; REX to access upper reg.
29 MOVw (%r8),%ss # -- -- -- 41 8E 10 ; REX to access upper reg.
31 MOVw (%r8),%fs # -- -- -- 41 8E 20 ; REX to access upper reg.
33 MOVb $0,(%r8) # -- -- -- 41 C6 00 00 ; REX to access upper reg.
35 …MOVw $0x7000,(%r8) # 66 -- -- 41 C7 00 00 70 ; REX to access upper reg. O16 for 16-bi…
37 MOVl $0x70000000,(%r8) # -- -- -- 41 C7 00 00 00 00 70 ; REX to access upper reg.
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/
Dmips16.s5 .macro ldst op, reg, base
6 \op \reg,0(\base)
7 \op \reg,1(\base)
8 \op \reg,2(\base)
9 \op \reg,3(\base)
10 \op \reg,4(\base)
11 \op \reg,8(\base)
12 \op \reg,16(\base)
13 \op \reg,32(\base)
14 \op \reg,64(\base)
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/toolchain/binutils/binutils-2.25/cpu/
Dfr30.cpu598 (binary-int-op add add "reg/reg" OP1_A OP2_6 add Rj Ri)
599 (binary-int-op addi add "immed/reg" OP1_A OP2_4 add u4 Ri)
600 (binary-int-op add2 add2 "immed/reg" OP1_A OP2_5 add m4 Ri)
601 (binary-int-op-c addc addc "reg/reg" OP1_A OP2_7 add Rj Ri)
602 (binary-int-op-n addn addn "reg/reg" OP1_A OP2_2 add Rj Ri)
603 (binary-int-op-n addni addn "immed/reg" OP1_A OP2_0 add u4 Ri)
604 (binary-int-op-n addn2 addn2 "immed/reg" OP1_A OP2_1 add m4 Ri)
606 (binary-int-op sub sub "reg/reg" OP1_A OP2_C sub Rj Ri)
607 (binary-int-op-c subc subc "reg/reg" OP1_A OP2_D sub Rj Ri)
608 (binary-int-op-n subn subn "reg/reg" OP1_A OP2_E sub Rj Ri)
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Dor1korfpx.cpu26 "floating point reg/reg insn opcode enums" ()
72 (.str "lf." mnemonic ".s reg/reg/reg")
80 (.str "lf." mnemonic ".d reg/reg/reg")
96 "lf.rem.s reg/reg/reg"
104 "lf.rem.d reg/reg/reg"
122 "lf.itof.s reg/reg"
130 "lf.itof.d reg/reg"
139 "lf.ftoi.s reg/reg"
148 "lf.ftoi.d reg/reg"
159 (.str "lf.sf" mnemonic ".s reg/reg")
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/
Dgroup-reloc-ldc.s97 .macro vfp_test load store reg argument
99 \load \reg, [r0, #:pc_g0:(f + 0x214)]
100 \load \reg, [r0, #:pc_g1:(f + 0x214)]
101 \load \reg, [r0, #:pc_g2:(f + 0x214)]
103 \load \reg, [r0, #:sb_g0:(f + 0x214)]
104 \load \reg, [r0, #:sb_g1:(f + 0x214)]
105 \load \reg, [r0, #:sb_g2:(f + 0x214)]
107 \store \reg, [r0, #:pc_g0:(f + 0x214)]
108 \store \reg, [r0, #:pc_g1:(f + 0x214)]
109 \store \reg, [r0, #:pc_g2:(f + 0x214)]
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Dgroup-reloc-ldc-encoding-bad.s107 .macro vfp_test load store reg cst
109 \load \reg, [r0, #:pc_g0:(f + \cst)]
110 \load \reg, [r0, #:pc_g1:(f + \cst)]
111 \load \reg, [r0, #:pc_g2:(f + \cst)]
113 \load \reg, [r0, #:sb_g0:(f + \cst)]
114 \load \reg, [r0, #:sb_g1:(f + \cst)]
115 \load \reg, [r0, #:sb_g2:(f + \cst)]
117 \store \reg, [r0, #:pc_g0:(f + \cst)]
118 \store \reg, [r0, #:pc_g1:(f + \cst)]
119 \store \reg, [r0, #:pc_g2:(f + \cst)]
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Dgroup-reloc-ldc-parsing-bad.s3 .macro ldctest insn reg argument
5 \insn 0, \reg, [r0, #:pc_g0_nc:(sym)]
6 \insn 0, \reg, [r0, #:pc_g1_nc:(sym)]
7 \insn 0, \reg, [r0, #:sb_g0_nc:(sym)]
8 \insn 0, \reg, [r0, #:sb_g1_nc:(sym)]
10 \insn 0, \reg, [r0, #:foo:(sym)]
14 .macro ldctest2 insn reg argument
16 \insn \reg, [r0, #:pc_g0_nc:(sym)]
17 \insn \reg, [r0, #:pc_g1_nc:(sym)]
18 \insn \reg, [r0, #:sb_g0_nc:(sym)]
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/
Dunwind-ok.d14 [[:space:]]*P3:rp_br\(reg=b7\)
17 [[:space:]]*X2:spill_reg\(t=0,reg=r4,treg=r2\)
18 [[:space:]]*X4:spill_reg_p\(qp=p1,t=1,reg=r7,treg=r31\)
19 [[:space:]]*X1:spill_sprel\(reg=b1,t=2,spoff=0x8\)
20 [[:space:]]*X3:spill_sprel_p\(qp=p2,t=3,reg=b5,spoff=0x10\)
21 [[:space:]]*X1:spill_psprel\(reg=f2,t=4,pspoff=0x10-0x28\)
22 [[:space:]]*X3:spill_psprel_p\(qp=p4,t=5,reg=f5,pspoff=0x10-0x30\)
23 [[:space:]]*X2:restore\(t=6,reg=f16\)
24 [[:space:]]*X4:restore_p\(qp=p8,t=7,reg=f31\)
25 [[:space:]]*X2:spill_reg\(t=8,reg=ar\.bsp,treg=r16\)
[all …]

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