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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/
Dmips16-hilo.s21 sll $4,16
24 sll $4,16
27 sll $4,16
30 sll $4,16
33 sll $4,16
36 sll $4,16
39 sll $4,16
42 sll $4,16
45 sll $4,16
48 sll $4,16
[all …]
Dmips16-hilo-n32.d12 2: f400 3480 sll a0,16
16 c: f400 3480 sll a0,16
21 18: f400 3480 sll a0,16
26 24: f400 3480 sll a0,16
31 30: f400 3480 sll a0,16
36 3c: f400 3480 sll a0,16
41 48: f400 3480 sll a0,16
46 54: f400 3480 sll a0,16
51 60: f400 3480 sll a0,16
55 6a: f400 3480 sll a0,16
[all …]
Dmips16-hilo.d12 2: f400 3480 sll a0,16
16 c: f400 3480 sll a0,16
21 18: f400 3480 sll a0,16
26 24: f400 3480 sll a0,16
31 30: f400 3480 sll a0,16
36 3c: f400 3480 sll a0,16
41 48: f400 3480 sll a0,16
46 54: f400 3480 sll a0,16
51 60: f400 3480 sll a0,16
55 6a: f400 3480 sll a0,16
[all …]
Dhilo-diff.s8 sll $4, 16
11 sll $5, 16
15 sll $4, 16
18 sll $5, 16
28 sll $4, 16
31 sll $5, 16
35 sll $4, 16
38 sll $5, 16
42 sll $4, 16
45 sll $5, 16
[all …]
Dulh-reloc.d10 [0-9a-f]+ <[^>]*> sll \$1,\$1,0x8
14 [0-9a-f]+ <[^>]*> sll \$1,\$1,0x8
19 [0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
25 [0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
30 [0-9a-f]+ <[^>]*> sll \$1,\$1,0x8
34 [0-9a-f]+ <[^>]*> sll \$1,\$1,0x8
39 [0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
45 [0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
53 [0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
61 [0-9a-f]+ <[^>]*> sll \$4,\$4,0x8
[all …]
Dhilo-diff-eb.d10 [0-9a-f]+ <[^>]*> 00042400 sll a0,a0,0x10
13 [0-9a-f]+ <[^>]*> 00052c00 sll a1,a1,0x10
16 [0-9a-f]+ <[^>]*> 00042400 sll a0,a0,0x10
19 [0-9a-f]+ <[^>]*> 00052c00 sll a1,a1,0x10
23 [0-9a-f]+ <[^>]*> 00042400 sll a0,a0,0x10
26 [0-9a-f]+ <[^>]*> 00052c00 sll a1,a1,0x10
29 [0-9a-f]+ <[^>]*> 00042400 sll a0,a0,0x10
32 [0-9a-f]+ <[^>]*> 00052c00 sll a1,a1,0x10
35 [0-9a-f]+ <[^>]*> 00042400 sll a0,a0,0x10
38 [0-9a-f]+ <[^>]*> 00052c00 sll a1,a1,0x10
[all …]
Dmicromips@hilo-diff-eb.d10 [0-9a-f]+ <[^>]*> 0084 8000 sll a0,a0,0x10
13 [0-9a-f]+ <[^>]*> 00a5 8000 sll a1,a1,0x10
16 [0-9a-f]+ <[^>]*> 0084 8000 sll a0,a0,0x10
19 [0-9a-f]+ <[^>]*> 00a5 8000 sll a1,a1,0x10
23 [0-9a-f]+ <[^>]*> 0084 8000 sll a0,a0,0x10
26 [0-9a-f]+ <[^>]*> 00a5 8000 sll a1,a1,0x10
29 [0-9a-f]+ <[^>]*> 0084 8000 sll a0,a0,0x10
32 [0-9a-f]+ <[^>]*> 00a5 8000 sll a1,a1,0x10
35 [0-9a-f]+ <[^>]*> 0084 8000 sll a0,a0,0x10
38 [0-9a-f]+ <[^>]*> 00a5 8000 sll a1,a1,0x10
[all …]
Dulh.d12 0+0008 <[^>]*> sll at,at,0x8
16 0+0018 <[^>]*> sll at,at,0x8
21 0+002c <[^>]*> sll a0,a0,0x8
25 0+003c <[^>]*> sll at,at,0x8
30 0+0050 <[^>]*> sll a0,a0,0x8
36 0+0068 <[^>]*> sll a0,a0,0x8
40 0+0078 <[^>]*> sll at,at,0x8
44 0+0088 <[^>]*> sll at,at,0x8
52 0+00a0 <[^>]*> sll a0,a0,0x8
60 0+00b8 <[^>]*> sll a0,a0,0x8
[all …]
Dulh2-el.d13 0+0008 <[^>]*> 00010a00 sll \$1,\$1,0x8
17 0+0018 <[^>]*> 00010a00 sll \$1,\$1,0x8
21 0+0028 <[^>]*> 00010a00 sll \$1,\$1,0x8
25 0+0038 <[^>]*> 00010a00 sll \$1,\$1,0x8
29 0+0048 <[^>]*> 00010a00 sll \$1,\$1,0x8
33 0+0058 <[^>]*> 00010a00 sll \$1,\$1,0x8
37 0+0068 <[^>]*> 00010a00 sll \$1,\$1,0x8
41 0+0078 <[^>]*> 00010a00 sll \$1,\$1,0x8
Dulh2-eb.d13 0+0008 <[^>]*> 00010a00 sll \$1,\$1,0x8
17 0+0018 <[^>]*> 00010a00 sll \$1,\$1,0x8
21 0+0028 <[^>]*> 00010a00 sll \$1,\$1,0x8
25 0+0038 <[^>]*> 00010a00 sll \$1,\$1,0x8
29 0+0048 <[^>]*> 00010a00 sll \$1,\$1,0x8
33 0+0058 <[^>]*> 00010a00 sll \$1,\$1,0x8
37 0+0068 <[^>]*> 00010a00 sll \$1,\$1,0x8
41 0+0078 <[^>]*> 00010a00 sll \$1,\$1,0x8
Dush.d21 0+002c <[^>]*> sll a0,a0,0x8
31 0+0054 <[^>]*> sll a0,a0,0x8
39 0+0074 <[^>]*> sll a0,a0,0x8
55 0+00ac <[^>]*> sll a0,a0,0x8
65 0+00cc <[^>]*> sll a0,a0,0x8
73 0+00e8 <[^>]*> sll a0,a0,0x8
83 0+0108 <[^>]*> sll a0,a0,0x8
91 0+0124 <[^>]*> sll a0,a0,0x8
101 0+0144 <[^>]*> sll a0,a0,0x8
109 0+0160 <[^>]*> sll a0,a0,0x8
[all …]
Dmicromips@ulh2-el.d13 [0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
17 [0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
21 [0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
25 [0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
29 [0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
33 [0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
37 [0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
41 [0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
Dmicromips@ulh2-eb.d13 [0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
17 [0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
21 [0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
25 [0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
29 [0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
33 [0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
37 [0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
41 [0-9a-f]+ <[^>]*> 0021 4000 sll \$1,\$1,0x8
Drol.d18 0+0020 <[^>]*> sll at,a0,0x1
21 0+002c <[^>]*> sll at,a1,0x1
34 0+0060 <[^>]*> sll a0,a0,0x1f
37 0+006c <[^>]*> sll a0,a1,0x1f
41 0+007c <[^>]*> sll at,a1,0x1
44 0+0088 <[^>]*> sll at,a1,0x1f
49 0+009c <[^>]*> sll a0,a1,0x1f
52 0+00a8 <[^>]*> sll a0,a1,0x1
Dulh-svr4pic.d18 0+0014 <[^>]*> sll a0,a0,0x8
25 0+002c <[^>]*> sll a0,a0,0x8
39 0+005c <[^>]*> sll a0,a0,0x8
53 0+0088 <[^>]*> sll a0,a0,0x8
62 0+00a4 <[^>]*> sll a0,a0,0x8
80 0+00e0 <[^>]*> sll a0,a0,0x8
94 0+0110 <[^>]*> sll a0,a0,0x8
102 0+012c <[^>]*> sll a0,a0,0x8
122 0+016c <[^>]*> sll a0,a0,0x8
Dulh-xgot.d19 0+0018 <[^>]*> sll a0,a0,0x8
29 0+0038 <[^>]*> sll a0,a0,0x8
49 0+0078 <[^>]*> sll a0,a0,0x8
67 0+00b0 <[^>]*> sll a0,a0,0x8
77 0+00d0 <[^>]*> sll a0,a0,0x8
99 0+0118 <[^>]*> sll a0,a0,0x8
119 0+0158 <[^>]*> sll a0,a0,0x8
130 0+017c <[^>]*> sll a0,a0,0x8
152 0+01c4 <[^>]*> sll a0,a0,0x8
Dmips16.s184 sll $2,$3,0
185 sll $2,$3,1
186 sll $2,$3,8
187 sll $2,$3,9
188 sll $2,$3,31
189 sll $2,$3
/toolchain/binutils/binutils-2.25/ld/testsuite/ld-mips-elf/
Dmips16-hilo-n32.d14 0+500002 <[^>]*> f400 3480 sll a0,16
17 0+50000c <[^>]*> f400 3480 sll a0,16
20 0+500018 <[^>]*> f400 3480 sll a0,16
23 0+500024 <[^>]*> f400 3480 sll a0,16
26 0+500030 <[^>]*> f400 3480 sll a0,16
29 0+50003c <[^>]*> f400 3480 sll a0,16
32 0+500048 <[^>]*> f400 3480 sll a0,16
35 0+500054 <[^>]*> f400 3480 sll a0,16
38 0+500060 <[^>]*> f400 3480 sll a0,16
41 0+50006a <[^>]*> f400 3480 sll a0,16
[all …]
Dmips16-hilo.d13 0+500002 <[^>]*> f400 3480 sll a0,16
16 0+50000c <[^>]*> f400 3480 sll a0,16
19 0+500018 <[^>]*> f400 3480 sll a0,16
22 0+500024 <[^>]*> f400 3480 sll a0,16
25 0+500030 <[^>]*> f400 3480 sll a0,16
28 0+50003c <[^>]*> f400 3480 sll a0,16
31 0+500048 <[^>]*> f400 3480 sll a0,16
34 0+500054 <[^>]*> f400 3480 sll a0,16
37 0+500060 <[^>]*> f400 3480 sll a0,16
40 0+50006a <[^>]*> f400 3480 sll a0,16
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/score/
DrD_rA_rB.d122 100: 0028 sll! r0, r2
123 102: 0028 sll! r0, r2
124 104: 0548 sll! r5, r4
125 106: 0548 sll! r5, r4
126 108: 0f48 sll! r15, r4
127 10a: 0f48 sll! r15, r4
128 10c: 0f38 sll! r15, r3
129 10e: 0f38 sll! r15, r3
130 110: 0838 sll! r8, r3
131 112: 0838 sll! r8, r3
[all …]
/toolchain/binutils/binutils-2.25/cpu/
Dsh.cpu187 (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 14))) (sll SI newvalue 14))))
196 (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 13))) (sll SI newvalue 13))))
205 (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 12))) (sll SI newvalue 12))))
214 (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv 2)) (sll SI newvalue 1))))
223 (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 9))) (sll SI newvalue 9))))
232 (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 8))) (sll SI newvalue 8))))
291 (sll DI (zext DI (subword SI (reg h-fr index) 0)) 32)
340 (or (sll (zext DI s1) 32)
345 (or (sll (zext DI h3) 48)
346 (or (sll (zext DI h2) 32)
[all …]
Dmep-avc2.cpu106 (or (sll (ifield f-avc2-v3Imm16s4x24e32-hi) 8) (ifield f-avc2-v3Imm16s4x24e32-lo))))
130 (or (sll (ifield f-avc2-c3Imm16s4x24e32-hi) 8) (ifield f-avc2-c3Imm16s4x24e32-lo))))
291 (if (lt (ext SI avc2c3CRq) (ext SI 0)) (set avc2copCCR1 (or (sll (srl avc2copCCR1 1) 1) (srl (sll (…
292 (set avc2copCCR1 (or (sll (srl avc2copCCR1 1) 1) (srl (sll (zext SI 0) 31) 31)))
431 (sequence() (set tmp0 (sll 1 (sub avc2c3Imm5u24 1)))
447 (sequence() (set tmp0 (sub (sll 1 avc2c3Imm5u24) 1))
503 (set avc2c3CRq (sll avc2c3CRq (and QI (srl avc2c3CRp 0) #x1f)))
524 (set avc2c3CRq (sll avc2c3CRq avc2c3Imm5u24))
531 (set avc2c3CRq (subword SI (sll (or (sll (zext DI avc2c3CRq) 32) (zext DI avc2c3CRp)) (and QI (srl …
538 (set avc2c3CRq (subword SI (sll (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3))…
[all …]
Dxstormy16.cpu150 (sll HI newval 12)))))
158 (set (newval) (set psw (or (and psw (inv (sll HI 1 index)))
159 (sll HI newval index)))))
396 (decode (value pc) (add SI (sll value 1) (add SI pc 2)))
411 (extract (set (ifield f-abs24) (or (sll (ifield f-abs24-2) 8) f-abs24-1)))
429 (sll HI (zflag HI value) 1))
430 (or (sll HI (c-call BI "parity" value) 5)
431 (sll HI (nflag QI (srl value (mul ws 8))) 6))))
440 (or (sll index 12)
448 (or (sll index 12)
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/m32r/
Dm32r2.s74 .global sll symbol
75 sll: label
76 sll r0,r1 || sll r2,r3
77 mul r0,r1 || sll r2,r3
78 sll r0,r1 || mul r2,r3
79 ldi r0,#1 || sll r2,r3
80 sll r0,r1 || ldi r2,#1
Dm32r2.d52 0+004c <sll>:
53 4c: 10 41 92 43 sll r0,r1 \|\| sll r2,r3
54 50: 12 43 90 61 sll r2,r3 \|\| mul r0,r1
55 54: 10 41 92 63 sll r0,r1 \|\| mul r2,r3
56 58: 60 01 92 43 ldi r0,#1 \|\| sll r2,r3
57 5c: 10 41 e2 01 sll r0,r1 \|\| ldi r2,#1

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