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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/
Dgroup-reloc-ldc.s7 .macro ldctest load store argument
17 \store 0, c0, [r0, #:pc_g0:(f + 0x214)]
18 \store 0, c0, [r0, #:pc_g1:(f + 0x214)]
19 \store 0, c0, [r0, #:pc_g2:(f + 0x214)]
21 \store 0, c0, [r0, #:sb_g0:(f + 0x214)]
22 \store 0, c0, [r0, #:sb_g1:(f + 0x214)]
23 \store 0, c0, [r0, #:sb_g2:(f + 0x214)]
33 \store 0, c0, [r0, #:pc_g0:(f - 0x214)]
34 \store 0, c0, [r0, #:pc_g1:(f - 0x214)]
35 \store 0, c0, [r0, #:pc_g2:(f - 0x214)]
[all …]
Dgroup-reloc-ldc-encoding-bad.s7 .macro ldctest load store cst
17 \store 0, c0, [r0, #:pc_g0:(f + \cst)]
18 \store 0, c0, [r0, #:pc_g1:(f + \cst)]
19 \store 0, c0, [r0, #:pc_g2:(f + \cst)]
21 \store 0, c0, [r0, #:sb_g0:(f + \cst)]
22 \store 0, c0, [r0, #:sb_g1:(f + \cst)]
23 \store 0, c0, [r0, #:sb_g2:(f + \cst)]
33 \store 0, c0, [r0, #:pc_g0:(f - \cst)]
34 \store 0, c0, [r0, #:pc_g1:(f - \cst)]
35 \store 0, c0, [r0, #:pc_g2:(f - \cst)]
[all …]
Dgroup-reloc-ldr-encoding-bad.s6 .macro ldrtest load store sym offset
15 \store r0, [r0, #:pc_g0:(\sym \offset)]
16 \store r0, [r0, #:pc_g1:(\sym \offset)]
17 \store r0, [r0, #:pc_g2:(\sym \offset)]
18 \store r0, [r0, #:sb_g0:(\sym \offset)]
19 \store r0, [r0, #:sb_g1:(\sym \offset)]
20 \store r0, [r0, #:sb_g2:(\sym \offset)]
Dgroup-reloc-ldr.s5 .macro ldrtest load store sym offset
14 \store r0, [r0, #:pc_g0:(\sym \offset)]
15 \store r0, [r0, #:pc_g1:(\sym \offset)]
16 \store r0, [r0, #:pc_g2:(\sym \offset)]
17 \store r0, [r0, #:sb_g0:(\sym \offset)]
18 \store r0, [r0, #:sb_g1:(\sym \offset)]
19 \store r0, [r0, #:sb_g2:(\sym \offset)]
Dgroup-reloc-ldrs-encoding-bad.s15 .macro ldrtest load store sym offset
19 \store r0, [r0, #:pc_g1:(\sym \offset)]
20 \store r0, [r0, #:pc_g2:(\sym \offset)]
21 \store r0, [r0, #:sb_g0:(\sym \offset)]
22 \store r0, [r0, #:sb_g1:(\sym \offset)]
23 \store r0, [r0, #:sb_g2:(\sym \offset)]
Dgroup-reloc-ldrs.s15 .macro ldrtest load store sym offset
19 \store r0, [r0, #:pc_g1:(\sym \offset)]
20 \store r0, [r0, #:pc_g2:(\sym \offset)]
21 \store r0, [r0, #:sb_g0:(\sym \offset)]
22 \store r0, [r0, #:sb_g1:(\sym \offset)]
23 \store r0, [r0, #:sb_g2:(\sym \offset)]
Dvfp1.s35 @ Load/store operations
40 @ Load/store multiple operations
162 @ Load/store operations
174 @ Load/store multiple operations
236 @ Load/store operations
241 @ Load/store multiple operations
Dvfp1_t2.s38 @ Load/store operations
43 @ Load/store multiple operations
165 @ Load/store operations
177 @ Load/store multiple operations
244 @ Load/store operations
249 @ Load/store multiple operations
Dvfp1xD_t2.s40 @ Load/store operations
45 @ Load/store multiple operations
183 @ Load/store operations
195 @ Load/store multiple operations
294 @ Load/store operations
299 @ Load/store multiple operations
Dvfpv3xd.d2 #name: VFP Double-precision load/store
5 # Test the ARM VFP Double Precision load/store on single precision FPU
Dvfp1xD.s37 @ Load/store operations
42 @ Load/store multiple operations
180 @ Load/store operations
192 @ Load/store multiple operations
286 @ Load/store operations
291 @ Load/store multiple operations
Dneon-ldst-es-bad.d1 # name: Bad element size combinations in Neon load/store instructions
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mt/
Dldst.s1 ; load/store tests
24 ldb @[r9+r3], r5 ; store
26 ldb @[r8+7], r3 ; store
28 ldw @[r14+10], r9 ; store
/toolchain/binutils/binutils-2.25/opcodes/
Ds390-opc.txt203 50 st RX_RRRD "store" g5 esa,zarch
204 9b stam RS_AARD "store access multiple" g5 esa,zarch
205 b212 stap S_RD "store CPU address" g5 esa,zarch
206 42 stc RX_RRRD "store character" g5 esa,zarch
207 b205 stck S_RD "store clock" g5 esa,zarch
208 b207 stckc S_RD "store clock comparator" g5 esa,zarch
209 be stcm RS_RURD "store characters under mask" g5 esa,zarch
210 b23a stcps S_RD "store channel path status" g5 esa,zarch
211 b239 stcrw S_RD "store channel report word" g5 esa,zarch
212 b6 stctl RS_CCRD "store control" g5 esa,zarch
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/toolchain/binutils/binutils-2.25/cpu/
Dfrv.cpu267 ; GR store unit
268 (unit u-gr-store "GR Store Unit" ()
283 ; FR store unit
284 (unit u-fr-store "FR Store Unit" ()
616 ; GR store unit -- TODO doesn't handle quad
617 (unit u-gr-store "GR Store Unit" ()
624 ; GR recovering store unit -- TODO doesn't handle quad
625 (unit u-gr-r-store "GR Recovering Store Unit" ()
640 ; FR store unit -- TODO doesn't handle quad
641 (unit u-fr-store "FR Store Unit" ()
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Depiphany.cpu145 (dnf f-wordsize "load/store size" () 6 2)
146 (dnf f-store "load/store flag" () 4 1) ;; 0==load,1==store
214 (dnmf f-disp11 "Unsigned offset for load/store" () UINT (f-disp3 f-disp8)
225 (dnmf f-sdisp11 "Signed offset for load/store" () INT (f-disp3 f-disp8)
302 ; specifies the size of a memory load/store operation
306 (define-normal-insn-enum insn-memory-access "memory access direction" () OP_ f-store
307 ; load=0, store=1
691 ;; [17:16]=exception cause 00=no exception 01=load-store exception 10=fpu exception 11=unimplemente…
1361 ;; common store to effective address, handling 8/16/32/64 bit data
1362 (define-pmacro (store-double-to-ea eff-addr regnum mode sel)
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Dor1korbis.cpu588 (define-pmacro (load-store-addr base offset size)
595 (set UWI rD (zext UWI (mem USI (load-store-addr rA simm16 4))))
604 (set WI rD (ext WI (mem SI (load-store-addr rA simm16 4))))
613 (set UWI rD (zext UWI (mem USI (load-store-addr rA simm16 4))))
615 (set atomic-address (load-store-addr rA simm16 4))
624 (set UWI rD (zext UWI (mem UQI (load-store-addr rA simm16 1))))
632 (set WI rD (ext WI (mem QI (load-store-addr rA simm16 1))))
640 (set UWI rD (zext UWI (mem UHI (load-store-addr rA simm16 2))))
648 (set WI rD (ext WI (mem HI (load-store-addr rA simm16 2))))
655 (define-pmacro (store-insn mnemonic opc-op mode size)
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Dfr30.opc76 int load_store) /* 0 == load, 1 == store. */
98 if (load_store) /* Mask is reversed for store. */
164 int load_store) /* 0 == load, 1 == store. */
Dlm32.cpu591 (dni sb "store byte" ()
612 (dni sh "store halfword" ()
668 (dni sw "store word" ()
838 (dni sbgprel "store byte gp relative" (ALIAS)
845 (dni shgprel "store halfword gp relative" (ALIAS)
852 (dni swgprel "store word gp relative" (ALIAS)
880 (dni swgotoff "store word got offset" (ALIAS)
894 (dni shgotoff "store half word got offset" (ALIAS)
915 (dni sbgotoff "store byte got offset" (ALIAS)
/toolchain/binutils/binutils-2.25/binutils/
Dnm.c416 asymbol *store; in filter_symbols() local
418 store = bfd_make_empty_symbol (abfd); in filter_symbols()
419 if (store == NULL) in filter_symbols()
433 sym = bfd_minisymbol_to_symbol (abfd, is_dynamic, (const void *) from, store); in filter_symbols()
948 asymbol *store; in print_size_symbols() local
951 store = bfd_make_empty_symbol (abfd); in print_size_symbols()
952 if (store == NULL) in print_size_symbols()
961 sym = bfd_minisymbol_to_symbol (abfd, is_dynamic, from->minisym, store); in print_size_symbols()
977 asymbol *store; in print_symbols() local
980 store = bfd_make_empty_symbol (abfd); in print_symbols()
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/
Dulh-pic.s1 # Test unaligned load and store macros with PIC code. We don't bother
D24k-triple-stores-9.d3 #name: 24K: Triple store (Intervening data #1)
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/
Dx86-64-gidt.s1 # Instructions to load/store global/interrupt description table
/toolchain/binutils/binutils-2.25/ld/emultempl/
Dspuelf.em429 einfo ("%X%P: %A exceeds local store range\n", s);
432 einfo ("%P: --auto-overlay ignored with zero local store range\n");
627 { "local-store", required_argument, NULL, OPTION_SPU_LOCAL_STORE },
649 --local-store=lo:hi Valid address range.\n\
653 executable does not fit in local store.\n\
659 --fixed-space=bytes Local store for non-overlay code and data.\n\
660 --reserved-space=bytes Local store for stack and heap. If not specified\n\
703 einfo (_("%P%F: invalid --local-store address range `%s'\''\n"), optarg);
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/nds32/
Dji-jr.d2 #name: nds32 load-store instructions

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