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Searched refs:CurOp (Results 1 – 8 of 8) sorted by relevance

/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp712 unsigned CurOp = X86II::getOperandBias(Desc); in EmitVEXOpcodePrefix() local
734 CurOp += X86::AddrNumOperands; in EmitVEXOpcodePrefix()
737 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); in EmitVEXOpcodePrefix()
740 VEX_4V = getVEXRegisterEncoding(MI, CurOp); in EmitVEXOpcodePrefix()
741 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) in EmitVEXOpcodePrefix()
743 CurOp++; in EmitVEXOpcodePrefix()
746 const MCOperand &MO = MI.getOperand(CurOp); in EmitVEXOpcodePrefix()
765 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) in EmitVEXOpcodePrefix()
767 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) in EmitVEXOpcodePrefix()
769 CurOp++; in EmitVEXOpcodePrefix()
[all …]
DX86BaseInfo.h633 unsigned CurOp = 0; in getOperandBias() local
635 ++CurOp; in getOperandBias()
640 CurOp += 2; in getOperandBias()
645 CurOp += 2; in getOperandBias()
648 ++CurOp; in getOperandBias()
649 return CurOp; in getOperandBias()
/external/llvm/utils/TableGen/
DDAGISelMatcherGen.cpp537 unsigned CurOp = NextRecordedOperandNo; in EmitMatcherCode() local
539 NamedComplexPatternOperands[N->getChild(i)->getName()] = CurOp + 1; in EmitMatcherCode()
540 CurOp += N->getChild(i)->getNumMIResults(CGP); in EmitMatcherCode()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGISel.cpp1792 unsigned CurOp = InlineAsm::Op_FirstOperand; in SelectInlineAsmMemoryOperands() local
1793 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue(); in SelectInlineAsmMemoryOperands()
1795 CurOp += InlineAsm::getNumOperandRegisters(Flags)+1; in SelectInlineAsmMemoryOperands()
1796 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue(); in SelectInlineAsmMemoryOperands()
DSelectionDAGBuilder.cpp6418 unsigned CurOp = InlineAsm::Op_FirstOperand; in visitInlineAsm() local
6422 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); in visitInlineAsm()
6426 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; in visitInlineAsm()
6430 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); in visitInlineAsm()
6445 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType(); in visitInlineAsm()
6480 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); in visitInlineAsm()
/external/llvm/docs/
DWritingAnLLVMBackend.rst1852 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
1854 if (CurOp != NumOps) {
1855 const MachineOperand &MO1 = MI.getOperand(CurOp++);
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp8813 SDValue CurOp = PreOp.getOperand(0); in tryMatchAcrossLaneShuffleForReduction() local
8818 CurOp = PreOp.getOperand(1); in tryMatchAcrossLaneShuffleForReduction()
8827 if (CurOp.getOpcode() != Op && (CurStep != (NumExpectedSteps - 1))) in tryMatchAcrossLaneShuffleForReduction()
8835 if (Shuffle.getOperand(0) != CurOp) in tryMatchAcrossLaneShuffleForReduction()
8855 PreOp = CurOp; in tryMatchAcrossLaneShuffleForReduction()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp21997 unsigned CurOp = 0; in emitEHSjLjSetJmp() local
21999 DstReg = MI->getOperand(CurOp++).getReg(); in emitEHSjLjSetJmp()
22005 MemOpndSlot = CurOp; in emitEHSjLjSetJmp()