Searched refs:DIV_OP (Results 1 – 8 of 8) sorted by relevance
/external/v8/src/mips64/ |
D | disasm-mips64.cc | 1297 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL() 1308 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL() 1319 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL() 1330 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
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D | constants-mips64.h | 470 DIV_OP = ((0U << 3) + 2), enumerator
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D | assembler-mips64.cc | 1659 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD); in div() 1676 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U); in divu() 1713 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD); in ddiv() 1730 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD_U); in ddivu()
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D | simulator-mips64.cc | 3619 case DIV_OP: in DecodeTypeRegisterSPECIAL() 3649 case DIV_OP: in DecodeTypeRegisterSPECIAL() 3678 case DIV_OP: in DecodeTypeRegisterSPECIAL()
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/external/v8/src/mips/ |
D | disasm-mips.cc | 1119 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL() 1130 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
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D | constants-mips.h | 451 DIV_OP = ((0U << 3) + 2), enumerator
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D | assembler-mips.cc | 1597 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD); in div() 1608 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U); in divu()
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D | simulator-mips.cc | 3588 case DIV_OP: in DecodeTypeRegisterSPECIAL() 3623 case DIV_OP: in DecodeTypeRegisterSPECIAL()
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