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Searched refs:DIV_OP (Results 1 – 8 of 8) sorted by relevance

/external/v8/src/mips64/
Ddisasm-mips64.cc1297 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
1308 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
1319 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
1330 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
Dconstants-mips64.h470 DIV_OP = ((0U << 3) + 2), enumerator
Dassembler-mips64.cc1659 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD); in div()
1676 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U); in divu()
1713 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD); in ddiv()
1730 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD_U); in ddivu()
Dsimulator-mips64.cc3619 case DIV_OP: in DecodeTypeRegisterSPECIAL()
3649 case DIV_OP: in DecodeTypeRegisterSPECIAL()
3678 case DIV_OP: in DecodeTypeRegisterSPECIAL()
/external/v8/src/mips/
Ddisasm-mips.cc1119 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
1130 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
Dconstants-mips.h451 DIV_OP = ((0U << 3) + 2), enumerator
Dassembler-mips.cc1597 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD); in div()
1608 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U); in divu()
Dsimulator-mips.cc3588 case DIV_OP: in DecodeTypeRegisterSPECIAL()
3623 case DIV_OP: in DecodeTypeRegisterSPECIAL()