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Searched refs:LW (Results 1 – 25 of 45) sorted by relevance

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/external/llvm/test/Linker/
Dsubprogram-linkonce-weak.ll2 ; RUN: FileCheck %s -check-prefix=LW -check-prefix=CHECK <%t1
16 ; The LW prefix means linkonce (this file) first, then weak (the other file).
20 ; LW: define i32 @bar({{.*}} !dbg ![[BARSP:[0-9]+]]
21 ; LW: %sum = add i32 %a, %b, !dbg ![[FOOINBAR:[0-9]+]]
22 ; LW: ret i32 %sum, !dbg ![[BARRET:[0-9]+]]
23 ; LW: define weak i32 @foo({{.*}} !dbg ![[WEAKFOOSP:[0-9]+]]
24 ; LW: %sum = call i32 @fastadd(i32 %a, i32 %b), !dbg ![[FOOCALL:[0-9]+]]
25 ; LW: ret i32 %sum, !dbg ![[FOORET:[0-9]+]]
52 ; LW-SAME: !{![[LCU:[0-9]+]], ![[WCU:[0-9]+]]}
56 ; LW: ![[LCU]] = distinct !DICompileUnit({{.*}} subprograms: ![[LSPs:[0-9]+]]
[all …]
/external/clang/utils/ABITest/
DEnumeration.py150 LW,RW = W//2, W - (W//2)
151 L,R = getNthPairBounded(N, H**LW, H**RW)
152 return (getNthNTuple(L,LW,H=H,useLeftToRight=useLeftToRight) +
/external/libvpx/libvpx/vpx_dsp/mips/
Dintrapred_msa.c23 src_data = LW(src); in intra_predict_vert_4x4_msa()
33 src_data1 = LW(src); in intra_predict_vert_8x8_msa()
34 src_data2 = LW(src + 4); in intra_predict_vert_8x8_msa()
161 val0 = LW(src_top); in intra_predict_dc_4x4_msa()
162 val1 = LW(src_left); in intra_predict_dc_4x4_msa()
181 val0 = LW(src); in intra_predict_dc_tl_4x4_msa()
393 val = LW(src_top_ptr); in intra_predict_tm_4x4_msa()
Dmacros_msa.h55 #define LW(psrc) ({ \ macro
89 val0_m = LW(psrc_m); \
90 val1_m = LW(psrc_m + 4); \
150 #define LW(psrc) ({ \ macro
184 val0_m = LW(psrc_m1); \
185 val1_m = LW(psrc_m1 + 4); \
240 out0 = LW((psrc)); \
241 out1 = LW((psrc) + stride); \
242 out2 = LW((psrc) + 2 * stride); \
243 out3 = LW((psrc) + 3 * stride); \
Dvpx_convolve_copy_msa.c214 tmp = LW(src); in vpx_convolve_copy_msa()
/external/libvpx/libvpx/vp8/common/mips/msa/
Dvp8_macros_msa.h43 #define LW(psrc) \ macro
80 val0_m = LW(psrc_m); \
81 val1_m = LW(psrc_m + 4); \
130 #define LW(psrc) \ macro
167 val0_m = LW(psrc_m1); \
168 val1_m = LW(psrc_m1 + 4); \
226 out0 = LW((psrc)); \
227 out1 = LW((psrc) + stride); \
228 out2 = LW((psrc) + 2 * stride); \
229 out3 = LW((psrc) + 3 * stride); \
/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp45 if ((Opc == Mips::LW) || (Opc == Mips::LD) || in isLoadFromStackSlot()
263 Opc = Mips::LW; in loadRegFromStack()
289 Opc = Mips::LW; in loadRegFromStack()
293 Opc = Mips::LW; in loadRegFromStack()
DMipsLongBranch.cpp329 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA) in expandToLongBranch()
DMipsFastISel.cpp361 emitInst(Mips::LW, DestReg) in materializeGV()
378 emitInst(Mips::LW, DestReg) in materializeExternalCallSym()
713 Opc = Mips::LW; in emitLoad()
DMipsDSPInstrInfo.td1318 (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1320 (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
DMipsInstrInfo.td1410 def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
2242 def : LoadRegImmPat<LW, i32, load>;
2249 def : MipsPat<(atomic_load_32 addr:$a), (LW addr:$a)>;
DMips16InstrInfo.td842 // Format: LW ry, offset(rx) MIPS16e
850 // Format: LW rx, offset(sp) MIPS16e
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsNaClELFStreamer.cpp216 case Mips::LW: in isBasePlusOffsetMemoryAccess()
/external/v8/src/mips/
Dassembler-mips.cc243 LW | (Register::kCode_sp << kRsShift) | (0 & kImm16Mask); // NOLINT
246 LW | (Register::kCode_fp << kRsShift) | (0 & kImm16Mask); // NOLINT
251 const Instr kLwRegFpNegOffsetPattern = LW | (Register::kCode_fp << kRsShift) |
629 return (static_cast<uint32_t>(instr & kOpcodeMask) == LW); in IsLw()
643 Instr temp_instr = LW | (instr & kRsFieldMask) | (instr & kRtFieldMask) in SetLwOffset()
1774 GenInstrImmediate(LW, rs.rm(), rd, rs.offset_); in lw()
1777 GenInstrImmediate(LW, at, rd, 0); // Equiv to lw(rd, MemOperand(at, 0)); in lw()
2099 GenInstrImmediate(LW, src.rm(), at, in ldc1()
2105 GenInstrImmediate(LW, at, at, Register::kExponentOffset); in ldc1()
Dconstants-mips.h362 LW = ((4U << 3) + 3) << kOpcodeShift, enumerator
901 OpcodeToBitNumber(LW) | OpcodeToBitNumber(LBU) | OpcodeToBitNumber(LHU) |
Ddisasm-mips.cc1566 case LW: in DecodeTypeImmediate()
/external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/fr-FR/
Dfr-FR_kdt_g2p.pkb33 �LW�ҤB�� �����G����c��&`"@(�H���xSP��V�#+g�� ��l`r���f���[Շ�#T�F�����2O�]��
/external/v8/src/mips64/
Dconstants-mips64.h350 LW = ((4U << 3) + 3) << kOpcodeShift, enumerator
947 OpcodeToBitNumber(LWL) | OpcodeToBitNumber(LW) | OpcodeToBitNumber(LWU) |
Dassembler-mips64.cc225 LW | (Register::kCode_fp << kRsShift) | (0 & kImm16Mask); // NOLINT
230 const Instr kLwRegFpNegOffsetPattern = LW | (Register::kCode_fp << kRsShift) |
597 return (static_cast<uint32_t>(instr & kOpcodeMask) == LW); in IsLw()
611 Instr temp_instr = LW | (instr & kRsFieldMask) | (instr & kRtFieldMask) in SetLwOffset()
1975 GenInstrImmediate(LW, rs.rm(), rd, rs.offset_); in lw()
1978 GenInstrImmediate(LW, at, rd, 0); // Equiv to lw(rd, MemOperand(at, 0)); in lw()
Ddisasm-mips64.cc1792 case LW: in DecodeTypeImmediate()
/external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/en-US/
Den-US_lh0_kpdf_phs.pkb1703 …)')/9CMRQJ@5+#!%*./0,'G����̙rcXV`r����gG3'!)?9oxr`L9,$ $+4@LW^_XL>0%2&.4896�…
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp1672 emitRRX(Mips::LW, Mips::T9, Mips::GP, in processInstruction()
1684 emitRRX(ABI.ArePtrs64bit() ? Mips::LD : Mips::LW, Mips::T9, Mips::GP, in processInstruction()
1694 emitRRX(ABI.ArePtrs64bit() ? Mips::LD : Mips::LW, Mips::T9, Mips::GP, in processInstruction()
3545 MemInst.setOpcode(IsLoad ? Mips::LW : Mips::SW); in createCpRestoreMemOp()
3553 emitRRI(IsLoad ? Mips::LW : Mips::SW, Mips::GP, Mips::SP, StackOffset, IDLoc, in createCpRestoreMemOp()
/external/v8/test/cctest/interpreter/
Dtest-bytecode-generator.cc2928 #define LW(c) B(LdaConstantWide), U16I(c), B(Star), R(0) in TEST() macro
2929 REPEAT_32(COMMA, LW(constant_count)), in TEST()
2930 REPEAT_16(COMMA, LW(constant_count)), in TEST()
2931 REPEAT_8(COMMA, LW(constant_count)), in TEST()
2932 #undef LW in TEST()
/external/llvm/test/MC/Mips/
Dmips-expansions.s16 # LW/SW and LDC1/SDC1 of symbol address, done by MipsAsmParser::expandMemInst():
/external/pcre/dist/sljit/
DsljitNativeMIPS_common.c146 #define LW (HI(35)) macro
529 #define STACK_LOAD LW

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