| /external/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.h | 31 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS()
74 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS()
75 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64AssignAAPCS()
76 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 }; in f64AssignAAPCS()
77 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS()
126 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64RetAssign()
127 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64RetAssign()
163 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
165 static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
169 static const MCPhysReg DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
[all …]
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| D | ARMBaseRegisterInfo.h | 72 const MCPhysReg *CSRegs) { in isCalleeSavedRegister()
94 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
126 ArrayRef<MCPhysReg> Order,
127 SmallVectorImpl<MCPhysReg> &Hints,
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 27 typedef uint16_t MCPhysReg; typedef
32 typedef const MCPhysReg* iterator;
33 typedef const MCPhysReg* const_iterator;
162 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
163 const MCPhysReg *DiffLists; // Pointer to the difflists array
193 const MCPhysReg *List;
202 void init(MCPhysReg InitVal, const MCPhysReg *DiffList) { in init()
212 MCPhysReg D = *List++; in advance()
247 const MCPhysReg (*RURoots)[2], in InitMCRegisterInfo()
249 const MCPhysReg *DL, in InitMCRegisterInfo()
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| D | MCInstrDesc.h | 147 const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr
148 const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
475 const MCPhysReg *getImplicitUses() const { return ImplicitUses; } in getImplicitUses()
497 const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; } in getImplicitDefs()
512 if (const MCPhysReg *ImpUses = ImplicitUses) in hasImplicitUseOfPhysReg()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.h | 28 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
31 static const MCPhysReg HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
34 static const MCPhysReg SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
37 static const MCPhysReg DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2,
40 static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
89 ArrayRef<MCPhysReg> RegList; in CC_AArch64_Custom_Block()
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| D | AArch64RegisterInfo.h | 37 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
38 const MCPhysReg *
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| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 166 ForwardedRegister(unsigned VReg, MCPhysReg PReg, MVT VT) in ForwardedRegister()
169 MCPhysReg PReg;
331 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
358 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
372 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
399 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
432 ArrayRef<MCPhysReg> ShadowRegs) { in AllocateStack()
501 void getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, MVT VT,
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| D | RegisterClassInfo.h | 33 std::unique_ptr<MCPhysReg[]> Order;
39 operator ArrayRef<MCPhysReg>() const {
56 const MCPhysReg *CalleeSaved;
93 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
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| D | MachineBasicBlock.h | 76 MCPhysReg PhysReg;
79 RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)
345 void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask = ~0u) {
360 unsigned addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC);
363 void removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask = ~0u);
366 bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask = ~0u) const;
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| /external/llvm/lib/CodeGen/ |
| D | AllocationOrder.h | 30 SmallVector<MCPhysReg, 16> Hints;
31 ArrayRef<MCPhysReg> Order;
45 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder()
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| D | RegisterClassInfo.cpp | 51 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); in runOnMachineFunction()
87 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
90 SmallVector<MCPhysReg, 16> CSRAlias; in compute()
97 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF); in compute()
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| D | CallingConvLower.cpp | 193 void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, in getRemainingRegParmsForType()
222 Regs.push_back(MCPhysReg(Locs[I].getLocReg())); in getRemainingRegParmsForType()
241 SmallVector<MCPhysReg, 8> RemainingRegs; in analyzeMustTailForwardedRegisters()
245 for (MCPhysReg PReg : RemainingRegs) { in analyzeMustTailForwardedRegisters()
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| D | LivePhysRegs.cpp | 143 for (const MCPhysReg *CSR = TRI.getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR) in addPristines()
157 for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) in addLiveOuts()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430RegisterInfo.cpp | 38 const MCPhysReg*
42 static const MCPhysReg CalleeSavedRegs[] = { in getCalleeSavedRegs()
47 static const MCPhysReg CalleeSavedRegsFP[] = { in getCalleeSavedRegs()
52 static const MCPhysReg CalleeSavedRegsIntr[] = { in getCalleeSavedRegs()
58 static const MCPhysReg CalleeSavedRegsIntrFP[] = { in getCalleeSavedRegs()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 58 typedef const MCPhysReg* iterator;
59 typedef const MCPhysReg* const_iterator;
75 ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
209 ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const { in getRawAllocationOrder()
426 virtual const MCPhysReg*
429 virtual const MCPhysReg*
722 ArrayRef<MCPhysReg> Order,
723 SmallVectorImpl<MCPhysReg> &Hints,
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsABIInfo.cpp | 19 static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
21 static const MCPhysReg Mips64IntRegs[8] = {
26 ArrayRef<MCPhysReg> MipsABIInfo::GetByValArgRegs() const { in GetByValArgRegs()
34 ArrayRef<MCPhysReg> MipsABIInfo::GetVarArgRegs() const { in GetVarArgRegs()
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| D | MipsABIInfo.h | 50 ArrayRef<MCPhysReg> GetByValArgRegs() const;
53 ArrayRef<MCPhysReg> GetVarArgRegs() const;
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 56 const MCPhysReg *
58 static const MCPhysReg CallerSavedRegsV4[] = { in getCallerSavedRegs()
78 const MCPhysReg *
80 static const MCPhysReg CalleeSavedRegsV3[] = { in getCalleeSavedRegs()
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| D | HexagonRegisterInfo.h | 45 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF)
79 const MCPhysReg *getCallerSavedRegs(const MachineFunction *MF) const;
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterInfo.h | 32 static const MCPhysReg CalleeSavedReg;
48 const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF) const override;
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| D | AMDGPURegisterInfo.cpp | 27 const MCPhysReg AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
29 const MCPhysReg*
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| D | SIFrameLowering.cpp | 39 static ArrayRef<MCPhysReg> getAllSGPR128() { in getAllSGPR128()
44 static ArrayRef<MCPhysReg> getAllSGPRs() { in getAllSGPRs()
124 for (MCPhysReg Reg : getAllSGPR128().drop_back(2).slice(NumPreloaded)) { in emitPrologue()
142 for (MCPhysReg Reg : getAllSGPRs().drop_back(6).slice(NumPreloaded)) { in emitPrologue()
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| D | SIMachineFunctionInfo.h | 96 MCPhysReg getNextUserSGPR() const { in getNextUserSGPR()
101 MCPhysReg getNextSystemSGPR() const { in getNextSystemSGPR()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXRegisterInfo.cpp | 80 const MCPhysReg *
82 static const MCPhysReg CalleeSavedRegs[] = { 0 }; in getCalleeSavedRegs()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegisterInfo.cpp | 39 const MCPhysReg *
41 static const MCPhysReg CalleeSavedRegs[] = {0}; in getCalleeSavedRegs()
|