1 //===- NVPTXRegisterInfo.cpp - NVPTX Register Information -----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the NVPTX implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "NVPTXRegisterInfo.h"
15 #include "NVPTX.h"
16 #include "NVPTXSubtarget.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/MC/MachineLocation.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "nvptx-reg-info"
27 
28 namespace llvm {
getNVPTXRegClassName(TargetRegisterClass const * RC)29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) {
30   if (RC == &NVPTX::Float32RegsRegClass) {
31     return ".f32";
32   }
33   if (RC == &NVPTX::Float64RegsRegClass) {
34     return ".f64";
35   } else if (RC == &NVPTX::Int64RegsRegClass) {
36     return ".s64";
37   } else if (RC == &NVPTX::Int32RegsRegClass) {
38     return ".s32";
39   } else if (RC == &NVPTX::Int16RegsRegClass) {
40     return ".s16";
41   } else if (RC == &NVPTX::Int1RegsRegClass) {
42     return ".pred";
43   } else if (RC == &NVPTX::SpecialRegsRegClass) {
44     return "!Special!";
45   } else {
46     return "INTERNAL";
47   }
48   return "";
49 }
50 
getNVPTXRegClassStr(TargetRegisterClass const * RC)51 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) {
52   if (RC == &NVPTX::Float32RegsRegClass) {
53     return "%f";
54   }
55   if (RC == &NVPTX::Float64RegsRegClass) {
56     return "%fd";
57   } else if (RC == &NVPTX::Int64RegsRegClass) {
58     return "%rd";
59   } else if (RC == &NVPTX::Int32RegsRegClass) {
60     return "%r";
61   } else if (RC == &NVPTX::Int16RegsRegClass) {
62     return "%rs";
63   } else if (RC == &NVPTX::Int1RegsRegClass) {
64     return "%p";
65   } else if (RC == &NVPTX::SpecialRegsRegClass) {
66     return "!Special!";
67   } else {
68     return "INTERNAL";
69   }
70   return "";
71 }
72 }
73 
NVPTXRegisterInfo()74 NVPTXRegisterInfo::NVPTXRegisterInfo() : NVPTXGenRegisterInfo(0) {}
75 
76 #define GET_REGINFO_TARGET_DESC
77 #include "NVPTXGenRegisterInfo.inc"
78 
79 /// NVPTX Callee Saved Registers
80 const MCPhysReg *
getCalleeSavedRegs(const MachineFunction *) const81 NVPTXRegisterInfo::getCalleeSavedRegs(const MachineFunction *) const {
82   static const MCPhysReg CalleeSavedRegs[] = { 0 };
83   return CalleeSavedRegs;
84 }
85 
getReservedRegs(const MachineFunction & MF) const86 BitVector NVPTXRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
87   BitVector Reserved(getNumRegs());
88   return Reserved;
89 }
90 
eliminateFrameIndex(MachineBasicBlock::iterator II,int SPAdj,unsigned FIOperandNum,RegScavenger * RS) const91 void NVPTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
92                                             int SPAdj, unsigned FIOperandNum,
93                                             RegScavenger *RS) const {
94   assert(SPAdj == 0 && "Unexpected");
95 
96   MachineInstr &MI = *II;
97   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
98 
99   MachineFunction &MF = *MI.getParent()->getParent();
100   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
101                MI.getOperand(FIOperandNum + 1).getImm();
102 
103   // Using I0 as the frame pointer
104   MI.getOperand(FIOperandNum).ChangeToRegister(NVPTX::VRFrame, false);
105   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
106 }
107 
getFrameRegister(const MachineFunction & MF) const108 unsigned NVPTXRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
109   return NVPTX::VRFrame;
110 }
111