| /external/boringssl/src/ssl/test/runner/poly1305/ |
| D | poly1305_arm.s | 29 ORR R3<<6, R9, R9
30 ORR R4<<12, g, g
31 ORR R5<<18, R11, R11
97 ORR R1<<6, g, g
98 ORR R2<<12, R11, R11
99 ORR R3<<18, R12, R12
107 ORR R3, R4, R4
153 ORR R11<<6, R12, R12
154 ORR R5<<6, R14, R14
163 ORR R1<<6, R12, R12
[all …]
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| /external/aac/libSBRdec/src/arm/ |
| D | env_calc_arm.cpp | 128 ORR r0, r0, r4 in FDK_get_maxval()
129 ORR r0, r0, r5 in FDK_get_maxval()
136 ORR r0, r0, r4 in FDK_get_maxval()
137 ORR r0, r0, r5 in FDK_get_maxval()
|
| /external/libhevc/common/arm64/ |
| D | ihevc_sao_band_offset_chroma.s | 176 … ORR v4.8b, v4.8b , v13.8b //band_table.val[3] = vorr_u8(band_table.val[3], au1_cmp)
184 … ORR v3.8b, v3.8b , v14.8b //band_table.val[2] = vorr_u8(band_table.val[2], au1_cmp)
194 … ORR v2.8b, v2.8b , v15.8b //band_table.val[1] = vorr_u8(band_table.val[1], au1_cmp)
203 … ORR v1.8b, v1.8b , v16.8b //band_table.val[0] = vorr_u8(band_table.val[0], au1_cmp)
250 … ORR v12.8b, v12.8b , v17.8b //band_table.val[3] = vorr_u8(band_table.val[3], au1_cmp)
258 … ORR v11.8b, v11.8b , v18.8b //band_table.val[2] = vorr_u8(band_table.val[2], au1_cmp)
268 … ORR v10.8b, v10.8b , v19.8b //band_table.val[1] = vorr_u8(band_table.val[1], au1_cmp)
278 … ORR v9.8b, v9.8b , v20.8b //band_table.val[0] = vorr_u8(band_table.val[0], au1_cmp)
|
| D | ihevc_sao_band_offset_luma.s | 152 … ORR v4.8b, v4.8b , v25.8b //band_table.val[3] = vorr_u8(band_table.val[3], au1_cmp)
160 … ORR v3.8b, v3.8b , v24.8b //band_table.val[2] = vorr_u8(band_table.val[2], au1_cmp)
170 … ORR v2.8b, v2.8b , v23.8b //band_table.val[1] = vorr_u8(band_table.val[1], au1_cmp)
180 … ORR v1.8b, v1.8b , v22.8b //band_table.val[0] = vorr_u8(band_table.val[0], au1_cmp)
|
| /external/v8/src/arm64/ |
| D | constants-arm64.h | 499 ORR = 0x20000000, enumerator
500 ORN = ORR | NOT,
514 ORR_w_imm = LogicalImmediateFixed | ORR,
515 ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits,
533 ORR_w = LogicalShiftedFixed | ORR,
534 ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits,
|
| D | macro-assembler-arm64.cc | 92 case ORR: // Fall through. in LogicalMacro()
108 case ORR: in LogicalMacro()
431 LogicalImmediate(dst, AppropriateZeroRegFor(dst), n, imm_s, imm_r, ORR); in TryOneInstrMoveImmediate()
|
| D | macro-assembler-arm64-inl.h | 94 LogicalMacro(rd, rn, operand, ORR); in Orr()
|
| D | assembler-arm64.cc | 1222 Logical(rd, rn, operand, ORR); in orr()
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-movi.ll | 4 ; Tests for MOV-immediate implemented with ORR-immediate.
93 ; Tests for ORR with MOVK.
|
| /external/pcre/dist/sljit/ |
| D | sljitNativeARM_64.c | 103 #define ORR 0xaa000000 macro
669 return push_inst(compiler, ORR | RD(dst) | RN(TMP_ZERO) | RM(arg2)); in emit_op_imm()
695 return push_inst(compiler, (ORR ^ (1 << 31)) | RD(dst) | RN(TMP_ZERO) | RM(arg2)); in emit_op_imm()
742 FAIL_IF(push_inst(compiler, (ORR ^ inv_bits) | RD(dst) | RN(arg1) | RM(arg2))); in emit_op_imm()
980 return push_inst(compiler, ORR | RD(arg) | RN(TMP_ZERO) | RM(TMP_LR)); in getput_arg()
1142 FAIL_IF(push_inst(compiler, ORR | RD(SLJIT_S0) | RN(TMP_ZERO) | RM(SLJIT_R0))); in sljit_emit_enter()
1144 FAIL_IF(push_inst(compiler, ORR | RD(SLJIT_S1) | RN(TMP_ZERO) | RM(SLJIT_R1))); in sljit_emit_enter()
1146 FAIL_IF(push_inst(compiler, ORR | RD(SLJIT_S2) | RN(TMP_ZERO) | RM(SLJIT_R2))); in sljit_emit_enter()
1261 FAIL_IF(push_inst(compiler, ORR | RD(TMP_REG1) | RN(TMP_ZERO) | RM(SLJIT_R0))); in sljit_emit_op0()
1266 FAIL_IF(push_inst(compiler, (ORR ^ inv_bits) | RD(TMP_REG1) | RN(TMP_ZERO) | RM(SLJIT_R0))); in sljit_emit_op0()
[all …]
|
| /external/vixl/src/vixl/a64/ |
| D | constants-a64.h | 526 ORR = 0x20000000, enumerator
527 ORN = ORR | NOT,
541 ORR_w_imm = LogicalImmediateFixed | ORR,
542 ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits,
560 ORR_w = LogicalShiftedFixed | ORR,
561 ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits,
|
| D | macro-assembler-a64.cc | 479 dst, AppropriateZeroRegFor(dst), n, imm_s, imm_r, ORR); in OneInstrMoveImmediateHelper()
676 LogicalMacro(rd, rn, operand, ORR); in Orr()
741 case ORR: in LogicalMacro()
759 case ORR: in LogicalMacro()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 117 // ORR Xd, XZR, Xm
329 // ORR.16b Vd,Vn,Vn
369 // BIC,ORR V,#imm are WriteV
409 // AND,BIC,CMTST,EOR,ORN,ORR
|
| /external/v8/src/arm/ |
| D | constants-arm.h | 153 ORR = 12 << 21, // Logical (inclusive) OR. enumerator
|
| D | disasm-arm.cc | 924 case ORR: { in DecodeType01()
|
| /external/tremolo/Tremolo/ |
| D | bitwiseARM.s | 108 ORR r10,r10,r12,LSL r5 @ r10= first r5+8 bits
304 ORR r10,r10,r12,LSL r5 @ r10= first r5+8 bits
|
| D | dpen.s | 146 ORR r0, r14,r10,LSL #8 @ r7 = chase = (next<<8) | r14
206 ORR r0, r14,r10,LSL #16 @ r7 = chase = (next<<16) | r14
|
| D | mdctLARM.s | 998 ORR r7, r7, r8, LSL #6 @ r7 = bitrev[bit]
|
| D | mdctARM.s | 1011 ORR r7, r7, r8, LSL #6 @ r7 = bitrev[bit]
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 319 # ORR
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 448 @ ORR
|
| D | thumb2-narrow-dp.ll | 728 // ORR (commutative)
734 ORR r2, r1, r2 // Must use wide encoding as not flag-setting
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-aliases.s | 25 ; ORR Rd, Rn, Rn is a MOV
|
| /external/vixl/doc/ |
| D | supported-instructions.md | 903 ### ORR ### subsection
2811 ### ORR ### subsection
2820 ### ORR ### subsection
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 128 // AND,BIC,EOR,ORN,ORR
|