Searched refs:Op1Reg (Results 1 – 5 of 5) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 219 unsigned Op1Reg, bool Op1IsKill);
223 unsigned Op1Reg, bool Op1IsKill);
227 unsigned Op1Reg, bool Op1IsKill);
3876 unsigned Op1Reg, bool Op1IsKill) { in emitLSL_rr() argument
3891 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask); in emitLSL_rr()
3894 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitLSL_rr()
3982 unsigned Op1Reg, bool Op1IsKill) { in emitLSR_rr() argument
3998 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask); in emitLSR_rr()
4001 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitLSR_rr()
4103 unsigned Op1Reg, bool Op1IsKill) { in emitASR_rr() argument
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1629 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in SelectSelect() local
1630 if (Op1Reg == 0) return false; in SelectSelect()
1675 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2); in SelectSelect()
1679 .addReg(Op1Reg) in SelectSelect()
1683 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1); in SelectSelect()
1686 .addReg(Op1Reg) in SelectSelect()
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1229 unsigned Op1Reg = getRegForValue(Op1); in X86FastEmitCompare() local
1230 if (Op1Reg == 0) return false; in X86FastEmitCompare()
1233 .addReg(Op1Reg); in X86FastEmitCompare()
1578 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in X86SelectShift() local
1579 if (Op1Reg == 0) return false; in X86SelectShift()
1581 CReg).addReg(Op1Reg); in X86SelectShift()
1687 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in X86SelectDivRem() local
1688 if (Op1Reg == 0) in X86SelectDivRem()
1724 TII.get(OpEntry.OpDivRem)).addReg(Op1Reg); in X86SelectDivRem()
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| D | X86ISelLowering.cpp | 21641 unsigned Op1Reg = MIIt->getOperand(1).getReg(); in EmitLoweredSelect() local
21648 std::swap(Op1Reg, Op2Reg); in EmitLoweredSelect()
21650 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end()) in EmitLoweredSelect()
21651 Op1Reg = RegRewriteTable[Op1Reg].first; in EmitLoweredSelect()
21658 .addReg(Op1Reg).addMBB(copy0MBB) in EmitLoweredSelect()
21662 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg); in EmitLoweredSelect()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1744 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in selectShift() local
1745 if (!Op1Reg) in selectShift()
1762 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg); in selectShift()
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