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Searched refs:VLIW (Results 1 – 12 of 12) sorted by relevance

/external/mesa3d/src/gallium/drivers/radeon/
DR600Schedule.td10 // R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction
DR600ISelLowering.cpp50 setSchedulingPreference(Sched::VLIW); in R600TargetLowering()
/external/llvm/lib/Target/AMDGPU/
DR600Schedule.td10 // R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction
/external/llvm/docs/CommandGuide/
Dtblgen.rst102 Generate DFA Packetizer for VLIW targets.
/external/llvm/
DCREDITS.TXT100 D: Deterministic finite automaton based infrastructure for VLIW packetization
239 D: Implemented DFA-based target independent VLIW packetizer
285 D: Backend for Qualcomm's Hexagon VLIW processor.
DCODE_OWNERS.TXT106 D: VLIW Instruction Scheduling, Packetization
/external/llvm/docs/TableGen/
DBackEnds.rst180 on a VLIW architecture. The class internally generates a deterministic finite
/external/llvm/docs/
DCodeGenerator.rst527 bundles. A MI bundle can model a VLIW group / pack which contains an arbitrary
1586 VLIW Packetizer
1589 In a Very Long Instruction Word (VLIW) architecture, the compiler is responsible
1592 *bundles*. The VLIW packetizer in LLVM is a target-independent mechanism to
1598 Instructions in a VLIW target can typically be mapped to multiple functional
1603 VLIW packetizer parses the instruction classes of a target and generates tables
1622 To generate tables for a VLIW target, add *Target*\ GenDFAPacketizer.inc as a
/external/llvm/include/llvm/Target/
DTargetLowering.h73 VLIW // Scheduling for VLIW targets. enumerator
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGISel.cpp314 if (TLI->getSchedulingPreference() == Sched::VLIW) in createDefaultScheduler()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1531 setSchedulingPreference(Sched::VLIW); in HexagonTargetLowering()
/external/clang/include/clang/Basic/
DAttrDocs.td897 - Ignored on older VLIW subtargets which did not have separate scalar