1//===-- R600Schedule.td - R600 Scheduling definitions ------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// R600 has a VLIW architecture.  On pre-cayman cards there are 5 instruction
11// slots ALU.X, ALU.Y, ALU.Z, ALU.W, and TRANS.  For cayman cards, the TRANS
12// slot has been removed.
13//
14//===----------------------------------------------------------------------===//
15
16
17def ALU_X : FuncUnit;
18def ALU_Y : FuncUnit;
19def ALU_Z : FuncUnit;
20def ALU_W : FuncUnit;
21def TRANS : FuncUnit;
22
23def AnyALU : InstrItinClass;
24def VecALU : InstrItinClass;
25def TransALU : InstrItinClass;
26
27def R600_EG_Itin : ProcessorItineraries <
28  [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS, ALU_NULL],
29  [],
30  [
31    InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS]>]>,
32    InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_X, ALU_W]>]>,
33    InstrItinData<TransALU, [InstrStage<1, [TRANS]>]>,
34    InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]>
35  ]
36>;
37