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Searched refs:X01 (Results 1 – 3 of 3) sorted by relevance

/external/clang/test/CXX/temp/temp.param/
Dp7.cpp14 template<VOID a> class X01; // expected-error{{cannot have type}}
/external/valgrind/VEX/priv/
Dguest_arm64_toIR.c229 #define X01 BITS2(0,1) macro
7529 case X01: in math_WIDEN_LO_OR_HI_LANES()
7570 case X01: amt = 16; break; in math_WIDEN_EVEN_OR_ODD_LANES()
7700 case X01: in math_VEC_DUP_IMM()
7918 vassert(size == X01 || size == X10); /* s or h only */ in math_SQDMULH()
7930 Int rcShift = size == X01 ? 15 : 31; in math_SQDMULH()
9107 if (bitU == 1 && sz <= X01 && opcode == BITS5(0,1,1,0,1)) { in dis_AdvSIMD_scalar_pairwise()
9110 Bool isD = sz == X01; in dis_AdvSIMD_scalar_pairwise()
9756 if (bitU == 0 && size <= X01 && opcode == BITS5(1,1,0,1,1)) { in dis_AdvSIMD_scalar_three_same()
9759 IRType ity = size == X01 ? Ity_F64 : Ity_F32; in dis_AdvSIMD_scalar_three_same()
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Dhost_arm64_defs.c2625 #define X01 BITS4(0,0, 0,1) macro
3073 UInt instr = X_2_6_2_12_5_5(X00, X111001, isLoad ? X01 : X00, in do_load_or_store8()
3107 UInt instr = X_2_6_3_9_2_5_5(X01, X111000, isLoad ? X010 : X000, in do_load_or_store16()
3122 UInt instr = X_2_6_2_12_5_5(X01, X111001, isLoad ? X01 : X00, in do_load_or_store16()
3171 UInt instr = X_2_6_2_12_5_5(X10, X111001, isLoad ? X01 : X00, in do_load_or_store32()
3222 UInt instr = X_2_6_2_12_5_5(X11, X111001, isLoad ? X01 : X00, in do_load_or_store64()
3273 argR->ARM64riA.I12.shift == 12 ? X01 : X00, in emit_ARM64Instr()
3300 is64 ? X11 : X01, X110001, in emit_ARM64Instr()
3301 argR->ARM64riA.I12.shift == 12 ? X01 : X00, in emit_ARM64Instr()
3819 *p++ = X_2_6_2_12_5_5(X01, X111101, isLD ? X01 : X00, in emit_ARM64Instr()
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