Searched refs:XIndir (Results 1 – 15 of 15) sorted by relevance
| /external/valgrind/VEX/priv/ |
| D | host_tilegx_defs.c | 304 showTILEGXCondCode(instr->GXin.XIndir.cond)); in ppTILEGXInstr()
305 ppHRegTILEGX(instr->GXin.XIndir.dstGA); in ppTILEGXInstr()
307 ppTILEGXAMode(instr->GXin.XIndir.amPC); in ppTILEGXInstr()
849 i->GXin.XIndir.dstGA = dstGA; in TILEGXInstr_XIndir()
850 i->GXin.XIndir.amPC = amPC; in TILEGXInstr_XIndir()
851 i->GXin.XIndir.cond = cond; in TILEGXInstr_XIndir()
1037 addHRegUse(u, HRmRead, i->GXin.XIndir.dstGA); in getRegUsage_TILEGXInstr()
1038 addRegUsage_TILEGXAMode(u, i->GXin.XIndir.amPC); in getRegUsage_TILEGXInstr()
1138 mapReg(m, &i->GXin.XIndir.dstGA); in mapRegs_TILEGXInstr()
1139 mapRegs_TILEGXAMode(m, i->GXin.XIndir.amPC); in mapRegs_TILEGXInstr()
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| D | host_x86_defs.c | 666 i->Xin.XIndir.dstGA = dstGA; in X86Instr_XIndir()
667 i->Xin.XIndir.amEIP = amEIP; in X86Instr_XIndir()
668 i->Xin.XIndir.cond = cond; in X86Instr_XIndir()
1006 showX86CondCode(i->Xin.XIndir.cond)); in ppX86Instr()
1007 ppHRegX86(i->Xin.XIndir.dstGA); in ppX86Instr()
1009 ppX86AMode(i->Xin.XIndir.amEIP); in ppX86Instr()
1329 addHRegUse(u, HRmRead, i->Xin.XIndir.dstGA); in getRegUsage_X86Instr()
1330 addRegUsage_X86AMode(u, i->Xin.XIndir.amEIP); in getRegUsage_X86Instr()
1542 mapReg(m, &i->Xin.XIndir.dstGA); in mapRegs_X86Instr()
1543 mapRegs_X86AMode(m, i->Xin.XIndir.amEIP); in mapRegs_X86Instr()
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| D | host_mips_defs.c | 921 i->Min.XIndir.dstGA = dstGA; in MIPSInstr_XIndir()
922 i->Min.XIndir.amPC = amPC; in MIPSInstr_XIndir()
923 i->Min.XIndir.cond = cond; in MIPSInstr_XIndir()
1330 showMIPSCondCode(i->Min.XIndir.cond)); in ppMIPSInstr()
1331 ppHRegMIPS(i->Min.XIndir.dstGA, mode64); in ppMIPSInstr()
1333 ppMIPSAMode(i->Min.XIndir.amPC, mode64); in ppMIPSInstr()
1690 addHRegUse(u, HRmRead, i->Min.XIndir.dstGA); in getRegUsage_MIPSInstr()
1691 addRegUsage_MIPSAMode(u, i->Min.XIndir.amPC); in getRegUsage_MIPSInstr()
1848 mapReg(m, &i->Min.XIndir.dstGA); in mapRegs_MIPSInstr()
1849 mapRegs_MIPSAMode(m, i->Min.XIndir.amPC); in mapRegs_MIPSInstr()
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| D | host_amd64_defs.c | 704 i->Ain.XIndir.dstGA = dstGA; in AMD64Instr_XIndir()
705 i->Ain.XIndir.amRIP = amRIP; in AMD64Instr_XIndir()
706 i->Ain.XIndir.cond = cond; in AMD64Instr_XIndir()
1123 showAMD64CondCode(i->Ain.XIndir.cond)); in ppAMD64Instr()
1125 ppHRegAMD64(i->Ain.XIndir.dstGA); in ppAMD64Instr()
1127 ppAMD64AMode(i->Ain.XIndir.amRIP); in ppAMD64Instr()
1518 addHRegUse(u, HRmRead, i->Ain.XIndir.dstGA); in getRegUsage_AMD64Instr()
1519 addRegUsage_AMD64AMode(u, i->Ain.XIndir.amRIP); in getRegUsage_AMD64Instr()
1767 mapReg(m, &i->Ain.XIndir.dstGA); in mapRegs_AMD64Instr()
1768 mapRegs_AMD64AMode(m, i->Ain.XIndir.amRIP); in mapRegs_AMD64Instr()
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| D | host_arm_defs.c | 1194 i->ARMin.XIndir.dstGA = dstGA; in ARMInstr_XIndir()
1195 i->ARMin.XIndir.amR15T = amR15T; in ARMInstr_XIndir()
1196 i->ARMin.XIndir.cond = cond; in ARMInstr_XIndir()
1656 showARMCondCode(i->ARMin.XIndir.cond)); in ppARMInstr()
1658 ppHRegARM(i->ARMin.XIndir.dstGA); in ppARMInstr()
1660 ppARMAMode1(i->ARMin.XIndir.amR15T); in ppARMInstr()
2082 addHRegUse(u, HRmRead, i->ARMin.XIndir.dstGA); in getRegUsage_ARMInstr()
2083 addRegUsage_ARMAMode1(u, i->ARMin.XIndir.amR15T); in getRegUsage_ARMInstr()
2362 i->ARMin.XIndir.dstGA in mapRegs_ARMInstr()
2363 = lookupHRegRemap(m, i->ARMin.XIndir.dstGA); in mapRegs_ARMInstr()
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| D | host_ppc_defs.c | 820 i->Pin.XIndir.dstGA = dstGA; in PPCInstr_XIndir()
821 i->Pin.XIndir.amCIA = amCIA; in PPCInstr_XIndir()
822 i->Pin.XIndir.cond = cond; in PPCInstr_XIndir()
1597 showPPCCondCode(i->Pin.XIndir.cond)); in ppPPCInstr()
1599 ppHRegPPC(i->Pin.XIndir.dstGA); in ppPPCInstr()
1601 ppPPCAMode(i->Pin.XIndir.amCIA); in ppPPCInstr()
2325 addHRegUse(u, HRmRead, i->Pin.XIndir.dstGA); in getRegUsage_PPCInstr()
2326 addRegUsage_PPCAMode(u, i->Pin.XIndir.amCIA); in getRegUsage_PPCInstr()
2678 mapReg(m, &i->Pin.XIndir.dstGA); in mapRegs_PPCInstr()
2679 mapRegs_PPCAMode(m, i->Pin.XIndir.amCIA); in mapRegs_PPCInstr()
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| D | host_arm64_defs.c | 934 i->ARM64in.XIndir.dstGA = dstGA; in ARM64Instr_XIndir()
935 i->ARM64in.XIndir.amPC = amPC; in ARM64Instr_XIndir()
936 i->ARM64in.XIndir.cond = cond; in ARM64Instr_XIndir()
1484 showARM64CondCode(i->ARM64in.XIndir.cond)); in ppARM64Instr()
1486 ppHRegARM64(i->ARM64in.XIndir.dstGA); in ppARM64Instr()
1488 ppARM64AMode(i->ARM64in.XIndir.amPC); in ppARM64Instr()
1984 addHRegUse(u, HRmRead, i->ARM64in.XIndir.dstGA); in getRegUsage_ARM64Instr()
1985 addRegUsage_ARM64AMode(u, i->ARM64in.XIndir.amPC); in getRegUsage_ARM64Instr()
2289 i->ARM64in.XIndir.dstGA in mapRegs_ARM64Instr()
2290 = lookupHRegRemap(m, i->ARM64in.XIndir.dstGA); in mapRegs_ARM64Instr()
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| D | host_tilegx_defs.h | 427 } XIndir; member
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| D | host_x86_defs.h | 473 } XIndir; member
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| D | host_amd64_defs.h | 494 } XIndir; member
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| D | host_mips_defs.h | 469 } XIndir; member
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| D | host_arm_defs.h | 710 } XIndir; member
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| D | host_arm64_defs.h | 618 } XIndir; member
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| D | host_ppc_defs.h | 634 } XIndir; member
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| /external/valgrind/docs/internals/ |
| D | t-chaining-notes.txt | 75 control-transfer instructions: XDirect, XIndir and XAssisted.
112 * new instructions in backends: XDirect, XIndir and XAssisted.
117 XIndir is used for indirect jumps. It is compiled into a jump
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