| /external/v8/src/x64/ |
| D | codegen-x64.h | 54 Register base_reg,
59 : base_reg_(base_reg), in base_reg_() argument
67 Register base_reg,
72 : base_reg_(base_reg), in base_reg_() argument
80 Register base_reg,
85 : base_reg_(base_reg), in base_reg_() argument
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| D | disasm-x64.cc | 346 int base_reg(int low_bits) { return low_bits | ((rex_ & 0x01) << 3); } in base_reg() function in disasm::DisassemblerX64
2006 NameOfCPURegister(base_reg(current & 0x07))); in InstructionDecode()
2011 NameOfCPURegister(base_reg(current & 0x07))); in InstructionDecode()
2036 NameOfCPURegister(base_reg(current & 0x07)), in InstructionDecode()
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| D | code-stubs-x64.cc | 5075 Register base_reg = r15; in CallApiFunctionAndReturn() local
5076 __ Move(base_reg, next_address); in CallApiFunctionAndReturn()
5077 __ movp(prev_next_address_reg, Operand(base_reg, kNextOffset)); in CallApiFunctionAndReturn()
5078 __ movp(prev_limit_reg, Operand(base_reg, kLimitOffset)); in CallApiFunctionAndReturn()
5079 __ addl(Operand(base_reg, kLevelOffset), Immediate(1)); in CallApiFunctionAndReturn()
5127 __ subl(Operand(base_reg, kLevelOffset), Immediate(1)); in CallApiFunctionAndReturn()
5128 __ movp(Operand(base_reg, kNextOffset), prev_next_address_reg); in CallApiFunctionAndReturn()
5129 __ cmpp(prev_limit_reg, Operand(base_reg, kLimitOffset)); in CallApiFunctionAndReturn()
5198 __ movp(Operand(base_reg, kLimitOffset), prev_limit_reg); in CallApiFunctionAndReturn()
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| D | assembler-x64.cc | 187 int base_reg = (has_sib ? operand.buf_[1] : modrm) & 0x07; in Operand() local
190 bool is_baseless = (mode == 0) && (base_reg == 0x05); // No base or RIP base. in Operand()
210 } else if (disp_value != 0 || (base_reg == 0x05)) { in Operand()
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_vec4_reg_allocate.cpp | 131 for (int base_reg = j; in brw_alloc_reg_set_for_classes() local
132 base_reg < j + class_sizes[i]; in brw_alloc_reg_set_for_classes()
133 base_reg++) { in brw_alloc_reg_set_for_classes()
134 ra_add_transitive_reg_conflict(brw->vs.regs, base_reg, reg); in brw_alloc_reg_set_for_classes()
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| D | brw_fs_reg_allocate.cpp | 119 for (int base_reg = j; in brw_alloc_reg_set_for_classes() local
120 base_reg < j + class_sizes[i]; in brw_alloc_reg_set_for_classes()
121 base_reg++) { in brw_alloc_reg_set_for_classes()
122 ra_add_transitive_reg_conflict(brw->wm.regs, base_reg, reg); in brw_alloc_reg_set_for_classes()
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| D | brw_blorp_blit.cpp | 493 void alloc_push_const_regs(int base_reg);
743 brw_blorp_blit_program::alloc_push_const_regs(int base_reg) in alloc_push_const_regs() argument
748 brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, base_reg, CONST_LOC(name) / 2) in alloc_push_const_regs()
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| D | brw_wm_emit.c | 1323 GLuint base_reg, in fire_fb_write() argument
1343 brw_message_reg(base_reg + 1), in fire_fb_write()
1357 base_reg, in fire_fb_write()
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| /external/mesa3d/src/mesa/program/ |
| D | register_allocate.c | 219 unsigned int base_reg, unsigned int reg) in ra_add_transitive_reg_conflict() argument
223 ra_add_reg_conflict(regs, reg, base_reg); in ra_add_transitive_reg_conflict()
225 for (i = 0; i < regs->regs[base_reg].num_conflicts; i++) { in ra_add_transitive_reg_conflict()
226 ra_add_reg_conflict(regs, reg, regs->regs[base_reg].conflict_list[i]); in ra_add_transitive_reg_conflict()
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| D | register_allocate.h | 44 unsigned int base_reg, unsigned int reg);
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| /external/v8/test/unittests/compiler/ia32/ |
| D | instruction-selector-ia32-unittest.cc | 344 Node* base_reg; // opaque value to generate base as register member in v8::internal::compiler::AddressingModeUnitTest
356 base_reg = m->Parameter(0); in Reset()
368 Node* base = base_reg; in TEST_F()
375 Node* base = base_reg; in TEST_F()
382 Node* base = base_reg; in TEST_F()
392 Node* base = base_reg; in TEST_F()
401 Node* base = base_reg; in TEST_F()
412 Node* base = base_reg; in TEST_F()
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| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_state_init.c | 423 uint32_t base_reg; in cube_emit_cs() local
435 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break; in cube_emit_cs()
436 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break; in cube_emit_cs()
438 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break; in cube_emit_cs()
444 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0)); in cube_emit_cs()
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