| /external/llvm/lib/Target/AMDGPU/ |
| D | R600MachineScheduler.cpp | 377 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_XRegClass); in AssignSlot()
380 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_YRegClass); in AssignSlot()
383 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass); in AssignSlot()
386 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_WRegClass); in AssignSlot()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 442 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass); in insertSelect()
448 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass); in insertSelect()
488 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) { in insertSelect()
492 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) { in insertSelect()
496 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) { in insertSelect()
499 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) { in insertSelect()
527 MRI.constrainRegClass(TrueReg, RC); in insertSelect()
528 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
737 !MRI->constrainRegClass(Reg, OpRegCstraints)) in UpdateOperandRegClass()
1860 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass); in storeRegToStackSlot()
[all …]
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| D | AArch64ConditionalCompares.cpp | 604 MRI->constrainRegClass(HeadCond[2].getReg(), in convert()
651 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(), in convert()
654 MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(), in convert()
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| D | AArch64RegisterInfo.cpp | 329 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
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| /external/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 706 MRI.constrainRegClass(RegA, RC); in reassociateOps()
708 MRI.constrainRegClass(RegB, RC); in reassociateOps()
710 MRI.constrainRegClass(RegX, RC); in reassociateOps()
712 MRI.constrainRegClass(RegY, RC); in reassociateOps()
714 MRI.constrainRegClass(RegC, RC); in reassociateOps()
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| D | OptimizePHIs.cpp | 171 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg))) in OptimizeBB()
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| D | UnreachableBlockElim.cpp | 194 MRI.constrainRegClass(Input, MRI.getRegClass(Output)); in runOnMachineFunction()
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| D | MachineCSE.cpp | 156 if (!MRI->constrainRegClass(SrcReg, RC)) in INITIALIZE_PASS_DEPENDENCY()
571 if (!MRI->constrainRegClass(NewReg, OldRC)) { in ProcessBlock()
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| D | TailDuplication.cpp | 300 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) { in TailDuplicateAndUpdate()
453 MRI->constrainRegClass(VI->second, MRI->getRegClass(Reg)); in DuplicateInstruction()
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| D | MachineRegisterInfo.cpp | 46 MachineRegisterInfo::constrainRegClass(unsigned Reg, in constrainRegClass() function in MachineRegisterInfo
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| D | TwoAddressInstructionPass.cpp | 1434 MRI->constrainRegClass(DstReg, RC); in collectTiedOperands()
1549 MRI->constrainRegClass(RegA, RC); in processTiedPairs()
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| D | MachineLICM.cpp | 1281 if (!MRI->constrainRegClass(DupReg, MRI->getRegClass(Reg))) { in EliminateCSE()
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| D | MachineBasicBlock.cpp | 392 if (!MRI.constrainRegClass(VirtReg, RC)) in addLiveIn()
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| D | PeepholeOptimizer.cpp | 537 MRI->constrainRegClass(DstReg, DstRC); in INITIALIZE_PASS_DEPENDENCY()
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| D | RegisterCoalescer.cpp | 716 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg))) in removeCopyByCommutingDef()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 227 if (!MRI.constrainRegClass(KilledProdReg, in processBlock()
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| D | PPCRegisterInfo.cpp | 994 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
1020 MRI.constrainRegClass(BaseReg, in resolveFrameIndex()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2InstrInfo.cpp | 152 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); in storeRegToStackSlot()
191 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); in loadRegFromStackSlot()
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| D | A15SDOptimizer.cpp | 669 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg())); in runOnInstruction()
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| D | ARMBaseRegisterInfo.cpp | 573 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
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| D | ARMLoadStoreOptimizer.cpp | 2184 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2185 MRI->constrainRegClass(SecondReg, TRC); in RescheduleOps()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 336 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { in AddRegisterOperand()
450 RC = MRI->constrainRegClass(VReg, RC, MinRCSize); in ConstrainForSubReg()
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| D | FastISel.cpp | 1771 if (!MRI.constrainRegClass(Op, RegClass)) { in constrainOperandRegClass()
1979 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx)); in fastEmitInst_extractsubreg()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 571 const TargetRegisterClass *constrainRegClass(unsigned Reg,
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.cpp | 702 MRI.constrainRegClass(DestReg, &SystemZ::GR32BitRegClass); in convertToThreeAddress()
703 MRI.constrainRegClass(SrcReg, &SystemZ::GR32BitRegClass); in convertToThreeAddress()
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