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Searched refs:fcvtns (Results 1 – 25 of 27) sorted by relevance

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/external/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s143 fcvtns h22, h13
144 fcvtns s22, s13
145 fcvtns d21, d14
Darm64-fp-encoding.s326 fcvtns w1, h2
327 fcvtns w1, s2
328 fcvtns w1, d2
329 fcvtns x1, h2
330 fcvtns x1, s2
331 fcvtns x1, d2
333 ; FP16: fcvtns w1, h2 ; encoding: [0x41,0x00,0xe0,0x1e]
335 ; NO-FP16-NEXT: fcvtns w1, h2
336 ; CHECK: fcvtns w1, s2 ; encoding: [0x41,0x00,0x20,0x1e]
337 ; CHECK: fcvtns w1, d2 ; encoding: [0x41,0x00,0x60,0x1e]
[all …]
Dneon-simd-misc.s549 fcvtns v4.4h, v0.4h
550 fcvtns v6.8h, v8.8h
551 fcvtns v6.4s, v8.4s
552 fcvtns v6.2d, v8.2d
553 fcvtns v4.2s, v0.2s
Dfullfp16-neon-neg.s238 fcvtns h22, h13
330 fcvtns v4.4h, v0.4h
332 fcvtns v6.8h, v8.8h
Darm64-advsimd.s838 fcvtns.2s v0, v0
839 fcvtns.4s v0, v0
840 fcvtns.2d v0, v0
841 fcvtns s0, s0
842 fcvtns d0, d0 define
844 ; CHECK: fcvtns.2s v0, v0 ; encoding: [0x00,0xa8,0x21,0x0e]
845 ; CHECK: fcvtns.4s v0, v0 ; encoding: [0x00,0xa8,0x21,0x4e]
846 ; CHECK: fcvtns.2d v0, v0 ; encoding: [0x00,0xa8,0x61,0x4e]
847 ; CHECK: fcvtns s0, s0 ; encoding: [0x00,0xa8,0x21,0x5e]
848 ; CHECK: fcvtns d0, d0 ; encoding: [0x00,0xa8,0x61,0x5e]
Dneon-diagnostics.s5891 fcvtns v0.16b, v31.16b
5892 fcvtns v2.8h, v4.8h
5893 fcvtns v1.8b, v9.8b
5894 fcvtns v13.4h, v21.4h
7237 fcvtns s0, d0
7238 fcvtns d0, s0 define
Dbasic-a64-instructions.s2068 fcvtns w3, s31
2069 fcvtns xzr, s12
2122 fcvtns w3, d31
2123 fcvtns xzr, d12
Dbasic-a64-diagnostics.s1809 fcvtns sp, s5
/external/llvm/test/CodeGen/AArch64/
Darm64-cvt.ll168 ;CHECK: fcvtns w0, s0
170 %tmp3 = call i32 @llvm.aarch64.neon.fcvtns.i32.f32(float %A)
176 ;CHECK: fcvtns x0, s0
178 %tmp3 = call i64 @llvm.aarch64.neon.fcvtns.i64.f32(float %A)
184 ;CHECK: fcvtns w0, d0
186 %tmp3 = call i32 @llvm.aarch64.neon.fcvtns.i32.f64(double %A)
192 ;CHECK: fcvtns x0, d0
194 %tmp3 = call i64 @llvm.aarch64.neon.fcvtns.i64.f64(double %A)
198 declare i32 @llvm.aarch64.neon.fcvtns.i32.f32(float) nounwind readnone
199 declare i64 @llvm.aarch64.neon.fcvtns.i64.f32(float) nounwind readnone
[all …]
Darm64-vcvt.ll192 ;CHECK: fcvtns.2s v0, v0
194 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtns.v2i32.v2f32(<2 x float> %A)
201 ;CHECK: fcvtns.4s v0, v0
203 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtns.v4i32.v4f32(<4 x float> %A)
210 ;CHECK: fcvtns.2d v0, v0
212 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtns.v2i64.v2f64(<2 x double> %A)
216 declare <2 x i32> @llvm.aarch64.neon.fcvtns.v2i32.v2f32(<2 x float>) nounwind readnone
217 declare <4 x i32> @llvm.aarch64.neon.fcvtns.v4i32.v4f32(<4 x float>) nounwind readnone
218 declare <2 x i64> @llvm.aarch64.neon.fcvtns.v2i64.v2f64(<2 x double>) nounwind readnone
/external/v8/test/cctest/
Dtest-disasm-arm64.cc1517 COMPARE(fcvtns(w0, s1), "fcvtns w0, s1"); in TEST_()
1518 COMPARE(fcvtns(x2, s3), "fcvtns x2, s3"); in TEST_()
1519 COMPARE(fcvtns(w4, d5), "fcvtns w4, d5"); in TEST_()
1520 COMPARE(fcvtns(x6, d7), "fcvtns x6, d7"); in TEST_()
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt1692 # FP16: fcvtns w3, h31
1693 # FP16: fcvtns xzr, h12
1746 # CHECK: fcvtns w3, s31
1747 # CHECK: fcvtns xzr, s12
1800 # CHECK: fcvtns w3, d31
1801 # CHECK: fcvtns xzr, d12
Darm64-advsimd.txt474 # CHECK: fcvtns.2s v0, v0
631 # 'orr.4h' should be selected over "fcvtns.2s v0, v1, #0"
Dneon-instructions.txt2580 # CHECK: fcvtns s22, s13
2581 # CHECK: fcvtns d21, d14
/external/vixl/test/
Dtest-simulator-a64.cc2554 DEFINE_TEST_FP_TO_INT(fcvtns, FPToS, Conversions) in DEFINE_TEST_FP_TO_INT()
3951 DEFINE_TEST_NEON_2SAME_FP(fcvtns, Conversions) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
4005 DEFINE_TEST_NEON_2SAME_FP_SCALAR(fcvtns, Conversions) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
Dtest-disasm-a64.cc2441 COMPARE(fcvtns(w0, s1), "fcvtns w0, s1"); in TEST()
2442 COMPARE(fcvtns(x2, s3), "fcvtns x2, s3"); in TEST()
2443 COMPARE(fcvtns(w4, d5), "fcvtns w4, d5"); in TEST()
2444 COMPARE(fcvtns(x6, d7), "fcvtns x6, d7"); in TEST()
/external/v8/src/arm64/
Dmacro-assembler-arm64-inl.h632 fcvtns(rd, fn); in Fcvtns()
Dassembler-arm64.h1597 void fcvtns(const Register& rd, const FPRegister& fn);
Dassembler-arm64.cc2005 void Assembler::fcvtns(const Register& rd, const FPRegister& fn) { in fcvtns() function in v8::internal::Assembler
/external/vixl/src/vixl/a64/
Dmacro-assembler-a64.h1249 fcvtns(rd, vn); in Fcvtns()
2264 V(fcvtns, Fcvtns) \
Dassembler-a64.h2216 void fcvtns(const Register& rd, const VRegister& vn);
2222 void fcvtns(const VRegister& rd, const VRegister& vn);
Dassembler-a64.cc2861 V(fcvtns, NEON_FCVTNS, FCVTNS) \
/external/vixl/doc/
Dsupported-instructions.md1976 void fcvtns(const Register& rd, const VRegister& vn)
1983 void fcvtns(const VRegister& rd, const VRegister& vn)
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp26728 fcvtns d10, d21 b558eaae3b599cb32c5743185b6d9fab 3005dfd6cbd7c72a1db21d20e84d4b4c 0000000000000…
26730 fcvtns s10, s21 50940fed544388650be1629a3ed03000 da02c064595a0d1b872062c31a4bfe93 0000000000000…
26732 fcvtns v10.2d, v21.2d b964e5b463880e2688108234e69faaf4 b272b25a3c184cfded10095e7196fb59 0000000…
26735 fcvtns v10.4s, v21.4s efc86c0367292df7a3e1a4e554da0d87 b856b6b7751284ce528411f0ee2c429e 0000000…
26737 fcvtns v10.2s, v21.2s f2bfa6d86025e6d85b56c8ae887f5aba ebadcb7c0348b78eb37c7b7a910dd263 0000000…
26739 fcvtns w21, s10 c34990364f7c39c8b16fed8e8191908d 4c78f2a8e6b9e23e13f746fb583aaca7 c34990364f7c3…
26741 fcvtns x21, s10 62672c1b333025c7a42b1386400eb0ff dab62b3c1f6607dd70f6727446b2cf6b 62672c1b33302…
26743 fcvtns w21, d10 96687437ae4e266cca7801e458763baf bb5ef3592ca24df6f39660c70e83aabf 96687437ae4e2…
26745 fcvtns x21, d10 a05f17c7b1bb0bb1411b018c410a4ff0 02e3eba53b9ef5b2a905062f6f7f5cb8 a05f17c7b1bb0…
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2439 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2727 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>;
3271 defm FCVTNS : SIMDFPTwoScalar< 0, 0, 0b11010, "fcvtns">;

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