| /external/llvm/lib/Target/AArch64/ |
| D | AArch64TargetMachine.cpp | 186 if (TM->getOptLevel() != CodeGenOpt::None) in AArch64PassConfig()
223 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy) in addIRPasses()
229 if (TM->getOptLevel() != CodeGenOpt::None) in addIRPasses()
232 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) { in addIRPasses()
250 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant) in addPreISel()
255 if ((TM->getOptLevel() != CodeGenOpt::None && in addPreISel()
258 bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) && in addPreISel()
263 if (TM->getOptLevel() != CodeGenOpt::None) in addPreISel()
270 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel())); in addInstSelector()
275 getOptLevel() != CodeGenOpt::None) in addInstSelector()
[all …]
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZTargetMachine.cpp | 119 addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel())); in addInstSelector()
121 if (getOptLevel() != CodeGenOpt::None) in addInstSelector()
128 if (getOptLevel() != CodeGenOpt::None && in addPreSched2()
138 if (getOptLevel() != CodeGenOpt::None) in addPreEmitPass()
164 if (getOptLevel() != CodeGenOpt::None) in addPreEmitPass()
171 if (getOptLevel() != CodeGenOpt::None) { in addPreEmitPass()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonTargetMachine.cpp | 177 bool NoOpt = (TM->getOptLevel() == CodeGenOpt::None); in HexagonPassConfig()
210 bool NoOpt = (getOptLevel() == CodeGenOpt::None); in addIRPasses()
224 bool NoOpt = (getOptLevel() == CodeGenOpt::None); in addInstSelector()
229 addPass(createHexagonISelDag(TM, getOptLevel())); in addInstSelector()
256 if (getOptLevel() != CodeGenOpt::None) { in addPreRegAlloc()
265 if (getOptLevel() != CodeGenOpt::None) in addPostRegAlloc()
272 if (getOptLevel() != CodeGenOpt::None) in addPreSched2()
278 bool NoOpt = (getOptLevel() == CodeGenOpt::None); in addPreEmitPass()
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| D | HexagonFrameLowering.cpp | 726 if (MF.getTarget().getOptLevel() == CodeGenOpt::None) in hasFP()
837 bool NoOpt = MF.getTarget().getOptLevel() == CodeGenOpt::None; in getFrameIndexReference()
1431 if (MF.getTarget().getOptLevel() > CodeGenOpt::Default) in shouldInlineCSR()
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| D | HexagonCopyToCombine.cpp | 410 MF.getTarget().getOptLevel() <= CodeGenOpt::Default; in runOnMachineFunction()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCTargetMachine.cpp | 269 computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this); in getSubtargetImpl()
305 if (TM->getOptLevel() != CodeGenOpt::None) in addIRPasses()
312 getOptLevel() != CodeGenOpt::None; in addIRPasses()
318 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) { in addIRPasses()
335 if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None) in addPreISel()
338 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None) in addPreISel()
358 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None) in addInstSelector()
392 if (getOptLevel() != CodeGenOpt::None) in addPreSched2()
397 if (getOptLevel() != CodeGenOpt::None) in addPreEmitPass()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetMachine.cpp | 340 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy) in addIRPasses()
349 if (TM->getOptLevel() != CodeGenOpt::None) in addIRPasses()
354 if ((TM->getOptLevel() != CodeGenOpt::None && in addPreISel()
362 bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) && in addPreISel()
377 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel())); in addInstSelector()
382 if (getOptLevel() != CodeGenOpt::None) { in addPreRegAlloc()
394 if (getOptLevel() != CodeGenOpt::None) { in addPreSched2()
405 if (getOptLevel() != CodeGenOpt::None) { in addPreSched2()
427 if (getOptLevel() != CodeGenOpt::None) in addPreEmitPass()
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| D | ARMAsmPrinter.cpp | 123 else if (TM.getOptLevel() == CodeGenOpt::Aggressive) in runOnMachineFunction()
126 else if (TM.getOptLevel() > CodeGenOpt::None) in runOnMachineFunction()
|
| /external/llvm/lib/CodeGen/ |
| D | Passes.cpp | 411 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) { in addIRPasses()
426 if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting) in addIRPasses()
429 if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining) in addIRPasses()
469 if (getOptLevel() != CodeGenOpt::None && !DisableCGP) in addCodeGenPrepare()
537 if (getOptLevel() != CodeGenOpt::None) { in addMachinePasses()
559 if (getOptLevel() != CodeGenOpt::None) in addMachinePasses()
565 if (getOptLevel() != CodeGenOpt::None) in addMachinePasses()
580 if (getOptLevel() != CodeGenOpt::None && in addMachinePasses()
595 if (getOptLevel() != CodeGenOpt::None) in addMachinePasses()
652 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None; in getOptimizeRegAlloc()
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| D | LLVMTargetMachine.cpp | 134 (TM->getOptLevel() == CodeGenOpt::None && in addPassesToGenerateCode()
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| D | PostRASchedulerList.cpp | 285 if (!enablePostRAScheduler(Fn.getSubtarget(), PassConfig->getOptLevel(), in runOnMachineFunction()
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| /external/llvm/lib/Target/X86/ |
| D | X86TargetMachine.cpp | 229 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel())); in addInstSelector()
233 getOptLevel() != CodeGenOpt::None) in addInstSelector()
257 if (getOptLevel() != CodeGenOpt::None) in addPreRegAlloc()
270 if (getOptLevel() != CodeGenOpt::None) in addPreEmitPass()
276 if (getOptLevel() != CodeGenOpt::None) { in addPreEmitPass()
|
| /external/llvm/lib/Target/ |
| D | TargetMachine.cpp | 141 CodeGenOpt::Level TargetMachine::getOptLevel() const { in getOptLevel() function in TargetMachine
144 return CodeGenInfo->getOptLevel(); in getOptLevel()
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| /external/llvm/tools/lli/ |
| D | OrcLazyJIT.cpp | 125 CodeGenOpt::Level getOptLevel();
143 EB.setOptLevel(getOptLevel()); in runOrcLazyJIT()
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| D | lli.cpp | 367 CodeGenOpt::Level getOptLevel() { in getOptLevel() function
466 builder.setOptLevel(getOptLevel()); in main()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXTargetMachine.cpp | 163 if (getOptLevel() == CodeGenOpt::Aggressive) in addEarlyCSEOrGVNPass()
234 addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel())); in addInstSelector()
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| /external/llvm/include/llvm/MC/ |
| D | MCCodeGenInfo.h | 44 CodeGenOpt::Level getOptLevel() const { return OptLevel; } in getOptLevel() function
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430TargetMachine.cpp | 65 addPass(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel())); in addInstSelector()
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| /external/llvm/include/llvm/CodeGen/ |
| D | Passes.h | 140 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUTargetMachine.cpp | 302 if (getOptLevel() > CodeGenOpt::None) { in addPreRegAlloc()
306 if (getOptLevel() > CodeGenOpt::None && ST.loadStoreOptEnabled()) { in addPreRegAlloc()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreTargetMachine.cpp | 74 addPass(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel())); in addInstSelector()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyTargetMachine.cpp | 150 createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel())); in addInstSelector()
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| /external/llvm/include/llvm/Target/ |
| D | TargetMachine.h | 188 CodeGenOpt::Level getOptLevel() const;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsTargetMachine.cpp | 231 if (getOptLevel() == CodeGenOpt::None) in addPreRegAlloc()
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| D | MipsDelaySlotFiller.cpp | 583 if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) { in runOnMachineBasicBlock()
|