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Searched refs:getSimpleVT (Results 1 – 25 of 44) sorted by relevance

12

/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.cpp689 MVT SimpleVT = LoadedVT.getSimpleVT(); in SelectLoad()
927 MVT SimpleVT = LoadedVT.getSimpleVT(); in SelectLoadVector()
969 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
993 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
1022 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
1046 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
1076 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
1100 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
1123 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
1147 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp177 MVT VT = RealVT.getSimpleVT(); in getRegForValue()
181 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); in getRegForValue()
244 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg, in materializeConstant()
327 IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN, in getRegForGEPIndex()
332 fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN, IdxNIsKill); in getRegForGEPIndex()
412 fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, Op1IsKill, in selectBinaryOp()
413 CI->getZExtValue(), VT.getSimpleVT()); in selectBinaryOp()
445 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, in selectBinaryOp()
446 Op0IsKill, Imm, VT.getSimpleVT()); in selectBinaryOp()
457 unsigned ResultReg = fastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), in selectBinaryOp()
[all …]
DSelectionDAG.cpp784 Erased = ValueTypeNodes[VT.getSimpleVT().SimpleTy] != nullptr; in RemoveNodeFromCSEMaps()
785 ValueTypeNodes[VT.getSimpleVT().SimpleTy] = nullptr; in RemoveNodeFromCSEMaps()
1434 if (VT.isSimple() && (unsigned)VT.getSimpleVT().SimpleTy >= in getValueType()
1436 ValueTypeNodes.resize(VT.getSimpleVT().SimpleTy+1); in getValueType()
1439 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT().SimpleTy]; in getValueType()
2014 MVT CompVT = N1.getValueType().getSimpleVT(); in FoldSetCC()
3722 assert(VT.getSimpleVT() <= N1.getSimpleValueType() && in getNode()
3732 if (VT.getSimpleVT() == N1.getSimpleValueType()) in getNode()
3967 if (VT.getSimpleVT() == N2.getSimpleValueType()) in getNode()
4213 TLI.isSafeMemOpType(NewVT.getSimpleVT())) in FindOptimalMemOpLowering()
[all …]
DLegalizeDAG.cpp268 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); in ExpandConstantFP()
1092 SrcVT.getSimpleVT())) { in LegalizeLoadOps()
1124 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT()); in LegalizeLoadOps()
1148 EVT LoadVT = TLI.getRegisterType(IDestVT.getSimpleVT()); in LegalizeLoadOps()
2741 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); in PromoteLegalINT_TO_FP()
2783 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); in PromoteLegalFP_TO_INT()
2841 switch (VT.getSimpleVT().SimpleTy) { in ExpandBSWAP()
3997 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT(); in ConvertNodeToLibcall()
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp155 DstTy.getSimpleVT(), in getCastInstrCost()
156 SrcTy.getSimpleVT())) in getCastInstrCost()
185 DstTy.getSimpleVT(), in getCastInstrCost()
186 SrcTy.getSimpleVT())) in getCastInstrCost()
216 ISD, DstTy.getSimpleVT(), in getCastInstrCost()
217 SrcTy.getSimpleVT())) in getCastInstrCost()
235 DstTy.getSimpleVT(), in getCastInstrCost()
236 SrcTy.getSimpleVT())) in getCastInstrCost()
286 SelCondTy.getSimpleVT(), in getCmpSelInstrCost()
287 SelValTy.getSimpleVT())) in getCmpSelInstrCost()
DARMFastISel.cpp690 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant()
737 VT = evt.getSimpleVT(); in isTypeLegal()
1363 MVT SrcVT = SrcEVT.getSimpleVT(); in ARMEmitCmp()
1556 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIToFP()
1788 MVT VT = FPVT.getSimpleVT(); in SelectBinaryFPOp()
2121 MVT RVVT = RVEVT.getSimpleVT(); in SelectRet()
2177 return ARMMaterializeGV(GV, LCREVT.getSimpleVT()); in getLibcallReg()
2744 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIntExt()
2745 MVT DestVT = DestEVT.getSimpleVT(); in SelectIntExt()
3028 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
DARMISelDAGToDAG.cpp1556 switch (LoadedVT.getSimpleVT().SimpleTy) { in SelectT2IndexedLoad()
1822 switch (VT.getSimpleVT().SimpleTy) { in SelectVLD()
1959 switch (VT.getSimpleVT().SimpleTy) { in SelectVST()
2122 switch (VT.getSimpleVT().SimpleTy) { in SelectVLDSTLane()
2235 switch (VT.getSimpleVT().SimpleTy) { in SelectVLDDup()
2773 switch (VT.getSimpleVT().SimpleTy) { in Select()
2793 switch (VT.getSimpleVT().SimpleTy) { in Select()
2813 switch (VT.getSimpleVT().SimpleTy) { in Select()
/external/llvm/include/llvm/Target/
DTargetLowering.h409 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); in isTypeLegal()
410 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr; in isTypeLegal()
553 return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op]; in getOperationAction()
593 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy; in getLoadExtAction()
594 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy; in getLoadExtAction()
619 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy; in getTruncStoreAction()
620 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy; in getTruncStoreAction()
630 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal; in isTruncStoreLegal()
647 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal || in isIndexedLoadLegal()
648 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom); in isIndexedLoadLegal()
[all …]
DTargetCallingConv.h150 VT = vt.getSimpleVT(); in InputArg()
189 VT = vt.getSimpleVT(); in OutputArg()
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp812 DstTy.getSimpleVT(), in getCastInstrCost()
813 SrcTy.getSimpleVT())) in getCastInstrCost()
818 DstTy.getSimpleVT(), in getCastInstrCost()
819 SrcTy.getSimpleVT())) in getCastInstrCost()
824 DstTy.getSimpleVT(), in getCastInstrCost()
825 SrcTy.getSimpleVT())) in getCastInstrCost()
831 DstTy.getSimpleVT(), in getCastInstrCost()
832 SrcTy.getSimpleVT())) in getCastInstrCost()
838 DstTy.getSimpleVT(), in getCastInstrCost()
839 SrcTy.getSimpleVT())) in getCastInstrCost()
[all …]
DX86FastISel.cpp325 VT = evt.getSimpleVT(); in isTypeLegal()
353 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitLoad()
443 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
534 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
572 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, in X86FastEmitExtend()
1084 SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, in X86SelectRet()
1163 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpOpcode()
1180 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpImmediateOpcode()
1372 ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND, in X86SelectZExt()
2752 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
[all …]
/external/llvm/include/llvm/CodeGen/
DValueTypes.h83 MVT EltTy = getSimpleVT().getVectorElementType(); in changeVectorElementTypeToInteger()
221 MVT getSimpleVT() const { in getSimpleVT() function
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp287 DstTy.getSimpleVT(), in getCastInstrCost()
288 SrcTy.getSimpleVT())) in getCastInstrCost()
403 SelCondTy.getSimpleVT(), in getCmpSelInstrCost()
404 SelValTy.getSimpleVT())) in getCmpSelInstrCost()
DAArch64ISelLowering.cpp633 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); in addTypeForNEON()
634 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32); in addTypeForNEON()
636 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote); in addTypeForNEON()
637 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32); in addTypeForNEON()
639 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); in addTypeForNEON()
640 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64); in addTypeForNEON()
642 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote); in addTypeForNEON()
643 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64); in addTypeForNEON()
648 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand); in addTypeForNEON()
649 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand); in addTypeForNEON()
[all …]
DAArch64FastISel.cpp467 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant()
915 VT = evt.getSimpleVT(); in isTypeLegal()
1411 MVT VT = EVT.getSimpleVT(); in emitCmp()
2769 emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed); in selectIntToFP()
2827 MVT VT = ArgVT.getSimpleVT().SimpleTy; in fastLowerArguments()
3702 MVT RVVT = RVEVT.getSimpleVT(); in selectRet()
3748 MVT SrcVT = SrcEVT.getSimpleVT(); in selectTrunc()
3749 MVT DestVT = DestEVT.getSimpleVT(); in selectTrunc()
4432 MVT DestVT = DestEVT.getSimpleVT(); in selectRem()
4797 IdxN = emitIntExt(IdxVT.getSimpleVT(), IdxN, PtrVT, /*IsZExt=*/false); in getRegForGEPIndex()
/external/llvm/lib/Target/MSP430/
DMSP430ISelDAGToDAG.cpp307 switch (VT.getSimpleVT().SimpleTy) { in isValidIndexedLoad()
332 MVT VT = LD->getMemoryVT().getSimpleVT(); in SelectIndexedLoad()
361 MVT VT = LD->getMemoryVT().getSimpleVT(); in SelectIndexedBinOp()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp510 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); in promoteLdStType()
511 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), in promoteLdStType()
512 PromotedLdStVT.getSimpleVT()); in promoteLdStType()
514 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote); in promoteLdStType()
515 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), in promoteLdStType()
516 PromotedLdStVT.getSimpleVT()); in promoteLdStType()
1184 if (VT.getSimpleVT() == MVT::v4i8) in createSplat()
1187 if (VT.getSimpleVT() == MVT::v4i16) in createSplat()
2065 return (MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32); in isTruncateFree()
2071 return (VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32); in isTruncateFree()
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp252 if (VT.getScalarType().getSimpleVT().SimpleTy == MVT::f32 in isFPImmLegal()
253 || VT.getScalarType().getSimpleVT().SimpleTy == MVT::f64) { in isFPImmLegal()
263 if (VT.getScalarType().getSimpleVT().SimpleTy == MVT::f32 in ShouldShrinkFPConstant()
264 || VT.getScalarType().getSimpleVT().SimpleTy == MVT::f64) { in ShouldShrinkFPConstant()
/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp395 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant()
545 VT = evt.getSimpleVT(); in isTypeLegal()
1481 MVT RVVT = RVEVT.getSimpleVT(); in selectRet()
1553 MVT SrcVT = SrcEVT.getSimpleVT(); in selectIntExt()
1554 MVT DestVT = DestEVT.getSimpleVT(); in selectIntExt()
1653 MVT DestVT = DestEVT.getSimpleVT(); in selectDivRem()
1714 MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT(); in selectShift()
1832 MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT(); in getRegEnsuringSimpleIntegerWidening()
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp270 VT = Evt.getSimpleVT(); in isTypeLegal()
806 MVT SrcVT = SrcEVT.getSimpleVT(); in PPCEmitCmp()
1000 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIToFP()
1645 MVT RVVT = RVEVT.getSimpleVT(); in SelectRet()
1814 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIntExt()
1815 MVT DestVT = DestEVT.getSimpleVT(); in SelectIntExt()
2131 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant()
DPPCISelLowering.cpp2853 switch (ValVT.getSimpleVT().SimpleTy) { in LowerFormalArguments_32SVR4()
3247 switch (ObjectVT.getSimpleVT().SimpleTy) { in LowerFormalArguments_64SVR4()
3368 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 && in LowerFormalArguments_64SVR4()
3376 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32; in LowerFormalArguments_64SVR4()
3379 switch (ObjectVT.getSimpleVT().SimpleTy) { in LowerFormalArguments_64SVR4()
3527 switch(ObjectVT.getSimpleVT().SimpleTy) { in LowerFormalArguments_Darwin()
3654 switch (ObjectVT.getSimpleVT().SimpleTy) { in LowerFormalArguments_Darwin()
4821 switch (ArgVT.getSimpleVT().SimpleTy) { in LowerCall_64SVR4()
5271 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 && in LowerCall_64SVR4()
5277 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32; in LowerCall_64SVR4()
[all …]
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp904 MVT SVT = VT.getSimpleVT(); in getTypeConversion()
990 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); in getTypeConversion()
1013 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); in getTypeConversion()
1401 RegisterVT = RegisterEVT.getSimpleVT(); in getVectorTypeBreakdown()
1625 return std::make_pair(Cost, MTy.getSimpleVT()); in getTypeLegalizationCost()
1632 return std::make_pair(Cost, MTy.getSimpleVT()); in getTypeLegalizationCost()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp380 CCInfo.addLoc(CCValAssign::getMem(ArgLocs.size(), VT.getSimpleVT(), in LowerCall()
381 Offset, VT.getSimpleVT(), in LowerCall()
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp212 switch (RegVT.getSimpleVT().SimpleTy) { in LowerFormalArguments()
215 << RegVT.getSimpleVT().SimpleTy << '\n'; in LowerFormalArguments()
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp1153 if (isCondCodeLegal(InverseCC, CompareVT.getSimpleVT())) { in LowerSELECT_CC()
1158 if (isCondCodeLegal(SwapInvCC, CompareVT.getSimpleVT())) { in LowerSELECT_CC()
1187 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) { in LowerSELECT_CC()
1194 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) { in LowerSELECT_CC()

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