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Searched refs:simm11 (Results 1 – 9 of 9) sorted by relevance

/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td25 // mov<cond> (%icc|%xcc), simm11, rd
27 ", $simm11, $rd"),
28 (movri IntRegs:$rd, i32imm:$simm11, condVal)>;
50 // mov<cond> %fcc[0-3], simm11, rd
51 def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $simm11, $rd"),
52 (movri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, condVal)>;
DSparcInstr64Bit.td323 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
324 "mov$cond %xcc, $simm11, $rd",
326 (SPselectxcc simm11:$simm11, i32:$f, imm:$cond))]>;
464 def : Pat<(SPselectxcc (i64 simm11:$t), i64:$f, imm:$cond),
469 def : Pat<(SPselecticc (i64 simm11:$t), i64:$f, imm:$cond),
474 def : Pat<(SPselectfcc (i64 simm11:$t), i64:$f, imm:$cond),
DSparcInstrInfo.td62 def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
1151 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1152 "mov$cond %icc, $simm11, $rd",
1154 (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
1165 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1166 "mov$cond %fcc0, $simm11, $rd",
1168 (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
1274 (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1275 "mov$cond $cc, $simm11, $rd", []>;
DSparcInstrFormats.td255 bits<11> simm11;
257 let Inst{10-0} = simm11;
/external/valgrind/VEX/priv/
Dhost_arm_defs.c339 ARMAModeV* mkARMAModeV ( HReg reg, Int simm11 ) { in mkARMAModeV() argument
341 vassert(simm11 >= -1020 && simm11 <= 1020); in mkARMAModeV()
342 vassert(0 == (simm11 & 3)); in mkARMAModeV()
344 am->simm11 = simm11; in mkARMAModeV()
349 vex_printf("%d(", am->simm11); in ppARMAModeV()
3506 Int simm11 = i->ARMin.VLdStD.amode->simm11; in emit_ARMInstr() local
3507 UInt off8 = simm11 >= 0 ? simm11 : ((UInt)(-simm11)); in emit_ARMInstr()
3508 UInt bU = simm11 >= 0 ? 1 : 0; in emit_ARMInstr()
3522 Int simm11 = i->ARMin.VLdStS.amode->simm11; in emit_ARMInstr() local
3523 UInt off8 = simm11 >= 0 ? simm11 : ((UInt)(-simm11)); in emit_ARMInstr()
[all …]
Dhost_arm_defs.h193 Int simm11; /* -1020, -1016 .. 1016, 1020 */ member
197 extern ARMAModeV* mkARMAModeV ( HReg reg, Int simm11 );
Dhost_arm_isel.c874 && am->simm11 >= -1020 && am->simm11 <= 1020 in sane_AModeV()
875 && 0 == (am->simm11 & 3) ); in sane_AModeV()
Dguest_arm_toIR.c19145 Int simm11 = INSN0(10,0); in disInstr_THUMB_WRK() local
19146 simm11 = (simm11 << 21) >> 20; in disInstr_THUMB_WRK()
19147 UInt dst = simm11 + guest_R15_curr_instr_notENC + 4; in disInstr_THUMB_WRK()
/external/llvm/lib/Target/Mips/
DMipsInstrInfo.td494 def simm11 : Operand<i32>;
680 let MIOperandInfo = (ops ptr_rc, simm11);