1//===-- SparcInstrAliases.td - Instruction Aliases for Sparc Target -------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains instruction aliases for Sparc.
11//===----------------------------------------------------------------------===//
12
13// Instruction aliases for conditional moves.
14
15// mov<cond> <ccreg> rs2, rd
16multiclass intcond_mov_alias<string cond, int condVal, string ccreg,
17                          Instruction movrr, Instruction movri,
18                          Instruction fmovs, Instruction fmovd> {
19
20  // mov<cond> (%icc|%xcc), rs2, rd
21  def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
22                             ", $rs2, $rd"),
23                  (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
24
25  // mov<cond> (%icc|%xcc), simm11, rd
26  def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
27                             ", $simm11, $rd"),
28                  (movri IntRegs:$rd, i32imm:$simm11, condVal)>;
29
30  // fmovs<cond> (%icc|%xcc), $rs2, $rd
31  def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg),
32                             ", $rs2, $rd"),
33                  (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
34
35  // fmovd<cond> (%icc|%xcc), $rs2, $rd
36  def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg),
37                             ", $rs2, $rd"),
38                  (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;
39}
40
41// mov<cond> <ccreg> rs2, rd
42multiclass fpcond_mov_alias<string cond, int condVal,
43                           Instruction movrr, Instruction movri,
44                           Instruction fmovs, Instruction fmovd> {
45
46  // mov<cond> %fcc[0-3], rs2, rd
47  def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $rs2, $rd"),
48                  (movrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, condVal)>;
49
50  // mov<cond> %fcc[0-3], simm11, rd
51  def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $simm11, $rd"),
52                  (movri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, condVal)>;
53
54  // fmovs<cond> %fcc[0-3], $rs2, $rd
55  def : InstAlias<!strconcat(!strconcat("fmovs", cond), " $cc, $rs2, $rd"),
56                  (fmovs FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, condVal)>;
57
58  // fmovd<cond> %fcc[0-3], $rs2, $rd
59  def : InstAlias<!strconcat(!strconcat("fmovd", cond), " $cc, $rs2, $rd"),
60                  (fmovd DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, condVal)>;
61}
62
63// Instruction aliases for integer conditional branches and moves.
64multiclass int_cond_alias<string cond, int condVal> {
65
66  // b<cond> $imm
67  def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
68                  (BCOND brtarget:$imm, condVal)>;
69
70  // b<cond>,a $imm
71  def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
72                  (BCONDA brtarget:$imm, condVal)>;
73
74  // b<cond> %icc, $imm
75  def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),
76                  (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
77
78  // b<cond>,pt %icc, $imm
79  def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %icc, $imm"),
80                  (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
81
82  // b<cond>,a %icc, $imm
83  def : InstAlias<!strconcat(!strconcat("b", cond), ",a %icc, $imm"),
84                  (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
85
86  // b<cond>,a,pt %icc, $imm
87  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %icc, $imm"),
88                  (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
89
90  // b<cond>,pn %icc, $imm
91  def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %icc, $imm"),
92                  (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
93
94  // b<cond>,a,pn %icc, $imm
95  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %icc, $imm"),
96                  (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
97
98  // b<cond> %xcc, $imm
99  def : InstAlias<!strconcat(!strconcat("b", cond), " %xcc, $imm"),
100                  (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
101
102  // b<cond>,pt %xcc, $imm
103  def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %xcc, $imm"),
104                  (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
105
106  // b<cond>,a %xcc, $imm
107  def : InstAlias<!strconcat(!strconcat("b", cond), ",a %xcc, $imm"),
108                  (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
109
110  // b<cond>,a,pt %xcc, $imm
111  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %xcc, $imm"),
112                  (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
113
114  // b<cond>,pn %xcc, $imm
115  def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %xcc, $imm"),
116                  (BPXCCNT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
117
118  // b<cond>,a,pn %xcc, $imm
119  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %xcc, $imm"),
120                  (BPXCCANT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
121
122
123  defm : intcond_mov_alias<cond, condVal, " %icc",
124                            MOVICCrr, MOVICCri,
125                            FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>;
126
127  defm : intcond_mov_alias<cond, condVal, " %xcc",
128                            MOVXCCrr, MOVXCCri,
129                            FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>;
130
131  // fmovq<cond> (%icc|%xcc), $rs2, $rd
132  def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %icc, $rs2, $rd"),
133                  (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
134                  Requires<[HasV9, HasHardQuad]>;
135  def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %xcc, $rs2, $rd"),
136                  (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
137                  Requires<[Is64Bit, HasHardQuad]>;
138
139  // t<cond> %icc, rs1 + rs2
140  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $rs2"),
141                  (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
142                  Requires<[HasV9]>;
143
144  // t<cond> %icc,  rs => t<cond> %icc, G0 + rs
145  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs2"),
146                  (TICCrr G0, IntRegs:$rs2, condVal)>,
147                  Requires<[HasV9]>;
148
149  // t<cond> %xcc, rs1 + rs2
150  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $rs2"),
151                  (TXCCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
152                  Requires<[HasV9]>;
153
154  // t<cond> %xcc, rs => t<cond> %xcc, G0 + rs
155  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs2"),
156                  (TXCCrr G0, IntRegs:$rs2, condVal)>,
157                  Requires<[HasV9]>;
158
159  // t<cond> rs1 + rs2 => t<cond> %icc, rs1 + rs2
160  def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"),
161                  (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>;
162
163  // t<cond> rs=> t<cond> %icc,  G0 + rs2
164  def : InstAlias<!strconcat(!strconcat("t", cond), " $rs2"),
165                  (TICCrr G0, IntRegs:$rs2, condVal)>;
166
167  // t<cond> %icc, rs1 + imm
168  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $imm"),
169                  (TICCri IntRegs:$rs1, i32imm:$imm, condVal)>,
170                  Requires<[HasV9]>;
171  // t<cond> %icc, imm => t<cond> %icc, G0 + imm
172  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $imm"),
173                  (TICCri G0, i32imm:$imm, condVal)>,
174                  Requires<[HasV9]>;
175  // t<cond> %xcc, rs1 + imm
176  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $imm"),
177                  (TXCCri IntRegs:$rs1, i32imm:$imm, condVal)>,
178                  Requires<[HasV9]>;
179  // t<cond> %xcc, imm => t<cond> %xcc, G0 + imm
180  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $imm"),
181                  (TXCCri G0, i32imm:$imm, condVal)>,
182                  Requires<[HasV9]>;
183
184  // t<cond> rs1 + imm => t<cond> %icc, rs1 + imm
185  def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $imm"),
186                  (TICCri IntRegs:$rs1, i32imm:$imm, condVal)>;
187
188  // t<cond> imm => t<cond> %icc, G0 + imm
189  def : InstAlias<!strconcat(!strconcat("t", cond), " $imm"),
190                  (TICCri G0, i32imm:$imm, condVal)>;
191
192}
193
194
195// Instruction aliases for floating point conditional branches and moves.
196multiclass fp_cond_alias<string cond, int condVal> {
197
198  // fb<cond> $imm
199  def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"),
200                  (FBCOND brtarget:$imm, condVal), 0>;
201
202  // fb<cond>,a $imm
203  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $imm"),
204                  (FBCONDA brtarget:$imm, condVal), 0>;
205
206  // fb<cond> %fcc0, $imm
207  def : InstAlias<!strconcat(!strconcat("fb", cond), " $cc, $imm"),
208                  (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
209                  Requires<[HasV9]>;
210
211  // fb<cond>,pt %fcc0, $imm
212  def : InstAlias<!strconcat(!strconcat("fb", cond), ",pt $cc, $imm"),
213                  (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
214                  Requires<[HasV9]>;
215
216  // fb<cond>,a %fcc0, $imm
217  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $cc, $imm"),
218                  (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
219                  Requires<[HasV9]>;
220
221  // fb<cond>,a,pt %fcc0, $imm
222  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pt $cc, $imm"),
223                  (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
224                   Requires<[HasV9]>;
225
226  // fb<cond>,pn %fcc0, $imm
227  def : InstAlias<!strconcat(!strconcat("fb", cond), ",pn $cc, $imm"),
228                  (BPFCCNT brtarget:$imm, condVal, FCCRegs:$cc)>,
229                   Requires<[HasV9]>;
230
231  // fb<cond>,a,pn %fcc0, $imm
232  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pn $cc, $imm"),
233                  (BPFCCANT brtarget:$imm, condVal, FCCRegs:$cc)>,
234                  Requires<[HasV9]>;
235
236  defm : fpcond_mov_alias<cond, condVal,
237                          V9MOVFCCrr, V9MOVFCCri,
238                          V9FMOVS_FCC, V9FMOVD_FCC>, Requires<[HasV9]>;
239
240  // fmovq<cond> %fcc0, $rs2, $rd
241  def : InstAlias<!strconcat(!strconcat("fmovq", cond), " $cc, $rs2, $rd"),
242                  (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2,
243                                                          condVal)>,
244                  Requires<[HasV9, HasHardQuad]>;
245}
246
247defm : int_cond_alias<"a",    0b1000>;
248defm : int_cond_alias<"",     0b1000>; // same as a; gnu asm, not in manual
249defm : int_cond_alias<"n",    0b0000>;
250defm : int_cond_alias<"ne",   0b1001>;
251defm : int_cond_alias<"nz",   0b1001>; // same as ne
252defm : int_cond_alias<"e",    0b0001>;
253defm : int_cond_alias<"eq",    0b0001>; // same as e
254defm : int_cond_alias<"z",    0b0001>; // same as e
255defm : int_cond_alias<"g",    0b1010>;
256defm : int_cond_alias<"le",   0b0010>;
257defm : int_cond_alias<"ge",   0b1011>;
258defm : int_cond_alias<"l",    0b0011>;
259defm : int_cond_alias<"gu",   0b1100>;
260defm : int_cond_alias<"leu",  0b0100>;
261defm : int_cond_alias<"cc",   0b1101>;
262defm : int_cond_alias<"geu",  0b1101>; // same as cc
263defm : int_cond_alias<"cs",   0b0101>;
264defm : int_cond_alias<"lu",   0b0101>; // same as cs
265defm : int_cond_alias<"pos",  0b1110>;
266defm : int_cond_alias<"neg",  0b0110>;
267defm : int_cond_alias<"vc",   0b1111>;
268defm : int_cond_alias<"vs",   0b0111>;
269
270defm : fp_cond_alias<"a",     0b0000>;
271defm : fp_cond_alias<"",      0b0000>; // same as a; gnu asm, not in manual
272defm : fp_cond_alias<"n",     0b1000>;
273defm : fp_cond_alias<"u",     0b0111>;
274defm : fp_cond_alias<"g",     0b0110>;
275defm : fp_cond_alias<"ug",    0b0101>;
276defm : fp_cond_alias<"l",     0b0100>;
277defm : fp_cond_alias<"ul",    0b0011>;
278defm : fp_cond_alias<"lg",    0b0010>;
279defm : fp_cond_alias<"ne",    0b0001>;
280defm : fp_cond_alias<"nz",    0b0001>; // same as ne
281defm : fp_cond_alias<"e",     0b1001>;
282defm : fp_cond_alias<"z",     0b1001>; // same as e
283defm : fp_cond_alias<"ue",    0b1010>;
284defm : fp_cond_alias<"ge",    0b1011>;
285defm : fp_cond_alias<"uge",   0b1100>;
286defm : fp_cond_alias<"le",    0b1101>;
287defm : fp_cond_alias<"ule",   0b1110>;
288defm : fp_cond_alias<"o",     0b1111>;
289
290// Section A.3 Synthetic Instructions
291
292// Most are marked as Emit=0, so that they are not used for disassembly. This is
293// an aesthetic issue, but the chosen policy is to typically prefer using the
294// non-alias form, except for the most obvious and clarifying aliases: cmp, jmp,
295// call, tst, ret, retl.
296
297// Note: cmp is handled in SparcInstrInfo.
298//       jmp/call/ret/retl have special case handling for output in
299//       SparcInstPrinter.cpp
300
301// jmp addr -> jmpl addr, %g0
302def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr), 0>;
303def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr), 0>;
304
305// call addr -> jmpl addr, %o7
306def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr), 0>;
307def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr), 0>;
308
309// tst reg -> orcc %g0, reg, %g0
310def : InstAlias<"tst $rs2", (ORCCrr G0, IntRegs:$rs2, G0)>;
311
312// ret -> jmpl %i7+8, %g0 (aka RET 8)
313def : InstAlias<"ret", (RET 8)>;
314
315// retl -> jmpl %o7+8, %g0 (aka RETL 8)
316def : InstAlias<"retl", (RETL 8)>;
317
318// restore -> restore %g0, %g0, %g0
319def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;
320
321// save -> restore %g0, %g0, %g0
322def : InstAlias<"save", (SAVErr G0, G0, G0)>;
323
324// set value, rd
325// (turns into a sequence of sethi+or, depending on the value)
326// def : InstAlias<"set $val, $rd", (ORri IntRegs:$rd, (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
327def SET : AsmPseudoInst<(outs IntRegs:$rd), (ins i32imm:$val), "set $val, $rd">;
328
329// not rd -> xnor rd, %g0, rd
330def : InstAlias<"not $rd", (XNORrr IntRegs:$rd, IntRegs:$rd, G0), 0>;
331
332// not reg, rd -> xnor reg, %g0, rd
333def : InstAlias<"not $rs1, $rd", (XNORrr IntRegs:$rd, IntRegs:$rs1, G0), 0>;
334
335// neg rd -> sub %g0, rd, rd
336def : InstAlias<"neg $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rd), 0>;
337
338// neg reg, rd -> sub %g0, reg, rd
339def : InstAlias<"neg $rs2, $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rs2), 0>;
340
341// inc rd -> add rd, 1, rd
342def : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>;
343
344// inc simm13, rd -> add rd, simm13, rd
345def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
346
347// inccc rd -> addcc rd, 1, rd
348def : InstAlias<"inccc $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;
349
350// inccc simm13, rd -> addcc rd, simm13, rd
351def : InstAlias<"inccc $simm13, $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
352
353// dec rd -> sub rd, 1, rd
354def : InstAlias<"dec $rd", (SUBri IntRegs:$rd, IntRegs:$rd, 1), 0>;
355
356// dec simm13, rd -> sub rd, simm13, rd
357def : InstAlias<"dec $simm13, $rd", (SUBri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
358
359// deccc rd -> subcc rd, 1, rd
360def : InstAlias<"deccc $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;
361
362// deccc simm13, rd -> subcc rd, simm13, rd
363def : InstAlias<"deccc $simm13, $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
364
365// btst reg_or_imm, reg -> andcc reg,reg_or_imm,%g0
366def : InstAlias<"btst $rs2, $rs1", (ANDCCrr G0, IntRegs:$rs1, IntRegs:$rs2), 0>;
367def : InstAlias<"btst $simm13, $rs1", (ANDCCri G0, IntRegs:$rs1, i32imm:$simm13), 0>;
368
369// bset reg_or_imm, rd -> or rd,reg_or_imm,rd
370def : InstAlias<"bset $rs2, $rd", (ORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
371def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
372
373// bclr reg_or_imm, rd -> andn rd,reg_or_imm,rd
374def : InstAlias<"bclr $rs2, $rd", (ANDNrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
375def : InstAlias<"bclr $simm13, $rd", (ANDNri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
376
377// btog reg_or_imm, rd -> xor rd,reg_or_imm,rd
378def : InstAlias<"btog $rs2, $rd", (XORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
379def : InstAlias<"btog $simm13, $rd", (XORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
380
381
382// clr rd -> or %g0, %g0, rd
383def : InstAlias<"clr $rd", (ORrr IntRegs:$rd, G0, G0), 0>;
384
385// clr{b,h,} [addr] -> st{b,h,} %g0, [addr]
386def : InstAlias<"clrb [$addr]", (STBrr MEMrr:$addr, G0), 0>;
387def : InstAlias<"clrb [$addr]", (STBri MEMri:$addr, G0), 0>;
388def : InstAlias<"clrh [$addr]", (STHrr MEMrr:$addr, G0), 0>;
389def : InstAlias<"clrh [$addr]", (STHri MEMri:$addr, G0), 0>;
390def : InstAlias<"clr [$addr]", (STrr MEMrr:$addr, G0), 0>;
391def : InstAlias<"clr [$addr]", (STri MEMri:$addr, G0), 0>;
392
393
394// mov reg_or_imm, rd -> or %g0, reg_or_imm, rd
395def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
396def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
397
398// mov specialreg, rd -> rd specialreg, rd
399def : InstAlias<"mov $asr, $rd", (RDASR IntRegs:$rd, ASRRegs:$asr), 0>;
400def : InstAlias<"mov %psr, $rd", (RDPSR IntRegs:$rd), 0>;
401def : InstAlias<"mov %wim, $rd", (RDWIM IntRegs:$rd), 0>;
402def : InstAlias<"mov %tbr, $rd", (RDTBR IntRegs:$rd), 0>;
403
404// mov reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
405def : InstAlias<"mov $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
406def : InstAlias<"mov $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
407def : InstAlias<"mov $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
408def : InstAlias<"mov $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>;
409def : InstAlias<"mov $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
410def : InstAlias<"mov $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>;
411def : InstAlias<"mov $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
412def : InstAlias<"mov $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>;
413
414// End of Section A.3
415
416// wr reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
417// (aka: omit the first arg when it's g0. This is not in the manual, but is
418// supported by gnu and solaris as)
419def : InstAlias<"wr $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
420def : InstAlias<"wr $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
421def : InstAlias<"wr $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
422def : InstAlias<"wr $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>;
423def : InstAlias<"wr $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
424def : InstAlias<"wr $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>;
425def : InstAlias<"wr $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
426def : InstAlias<"wr $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>;
427
428
429// flush -> flush %g0
430def : InstAlias<"flush", (FLUSH), 0>;
431
432
433def : MnemonicAlias<"lduw", "ld">, Requires<[HasV9]>;
434def : MnemonicAlias<"lduwa", "lda">, Requires<[HasV9]>;
435
436def : MnemonicAlias<"return", "rett">, Requires<[HasV9]>;
437
438def : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>;
439def : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>;
440
441def : MnemonicAlias<"subc", "subx">, Requires<[HasV9]>;
442def : MnemonicAlias<"subccc", "subxcc">, Requires<[HasV9]>;
443
444
445def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
446def : InstAlias<"fcmpd $rs1, $rs2", (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)>;
447def : InstAlias<"fcmpq $rs1, $rs2", (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>,
448                Requires<[HasHardQuad]>;
449
450def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
451def : InstAlias<"fcmped $rs1, $rs2", (V9FCMPED FCC0, DFPRegs:$rs1,
452                                                     DFPRegs:$rs2)>;
453def : InstAlias<"fcmpeq $rs1, $rs2", (V9FCMPEQ FCC0, QFPRegs:$rs1,
454                                                     QFPRegs:$rs2)>,
455                Requires<[HasHardQuad]>;
456
457// signx rd -> sra rd, %g0, rd
458def : InstAlias<"signx $rd", (SRArr IntRegs:$rd, IntRegs:$rd, G0), 0>, Requires<[HasV9]>;
459
460// signx reg, rd -> sra reg, %g0, rd
461def : InstAlias<"signx $rs1, $rd", (SRArr IntRegs:$rd, IntRegs:$rs1, G0), 0>, Requires<[HasV9]>;
462