| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 74 v64i8 = 27, // 64 x i8 enumerator
258 SimpleTy == MVT::v512i1 || SimpleTy == MVT::v64i8 || in is512BitVector()
324 case v64i8: in getVectorElementType()
374 case v64i8: in getVectorNumElements()
490 case v64i8: in getSizeInBits()
602 if (NumElements == 64) return MVT::v64i8; in getVectorVT()
|
| D | ValueTypes.td | 51 def v64i8 : ValueType<512, 27>; // 64 x i8 vector value
|
| /external/llvm/lib/Target/X86/ |
| D | X86CallingConv.td | 51 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
68 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
149 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
294 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
312 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
415 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
490 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
507 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
526 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
567 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
[all …]
|
| D | X86InstrAVX512.td | 379 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
384 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
388 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
394 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
398 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
402 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
403 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
404 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
405 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
406 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
[all …]
|
| D | X86RegisterInfo.td | 465 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
|
| D | X86ISelLowering.cpp | 1612 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) { in X86TargetLowering()
1620 addRegisterClass(MVT::v64i8, &X86::VR512RegClass); in X86TargetLowering()
1626 setOperationAction(ISD::LOAD, MVT::v64i8, Legal); in X86TargetLowering()
1630 setOperationAction(ISD::ADD, MVT::v64i8, Legal); in X86TargetLowering()
1632 setOperationAction(ISD::SUB, MVT::v64i8, Legal); in X86TargetLowering()
1639 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom); in X86TargetLowering()
1643 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom); in X86TargetLowering()
1645 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom); in X86TargetLowering()
1653 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom); in X86TargetLowering()
1654 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom); in X86TargetLowering()
[all …]
|
| D | X86InstrFragmentsSIMD.td | 630 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
|
| /external/llvm/test/CodeGen/X86/ |
| D | vector-lzcnt-512.ll | 156 %out = call <64 x i8> @llvm.ctlz.v64i8(<64 x i8> %in, i1 0)
212 %out = call <64 x i8> @llvm.ctlz.v64i8(<64 x i8> %in, i1 -1)
219 declare <64 x i8> @llvm.ctlz.v64i8(<64 x i8>, i1)
|
| D | vector-tzcnt-512.ll | 234 %out = call <64 x i8> @llvm.cttz.v64i8(<64 x i8> %in, i1 0)
264 %out = call <64 x i8> @llvm.cttz.v64i8(<64 x i8> %in, i1 -1)
271 declare <64 x i8> @llvm.cttz.v64i8(<64 x i8>, i1)
|
| D | vector-popcnt-512.ll | 154 %out = call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %in)
161 declare <64 x i8> @llvm.ctpop.v64i8(<64 x i8>)
|
| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 154 case MVT::v64i8: return "v64i8"; in getEVTString()
232 case MVT::v64i8: return VectorType::get(Type::getInt8Ty(Context), 64); in getTypeForEVT()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonIntrinsicsV60.td | 92 def : Pat <(v512i1 (bitconvert (v64i8 VectorRegs:$src1))),
93 (v512i1 (V6_vandvrt(v64i8 VectorRegs:$src1),
112 def : Pat <(v64i8 (bitconvert (v512i1 VecPredRegs:$src1))),
113 (v64i8 (V6_vandqrt(v512i1 VecPredRegs:$src1),
|
| D | HexagonISelLowering.cpp | 198 LocVT == MVT::v64i8 || LocVT == MVT::v512i1) { in CC_Hexagon_VarArg()
338 LocVT == MVT::v64i8 || LocVT == MVT::v512i1)) { in CC_HexagonVector()
409 } else if (LocVT == MVT::v64i8 || LocVT == MVT::v32i16 || in RetCC_Hexagon()
545 ty == MVT::v64i8 || in IsHvxVectorType()
889 VT == MVT::v32i16 || VT == MVT::v64i8); in getIndexedAddressParts()
1083 RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) { in LowerFormalArguments()
1566 addRegisterClass(MVT::v64i8, &Hexagon::VectorRegsRegClass); in HexagonTargetLowering()
2672 case MVT::v64i8: in getRegForInlineAsmConstraint()
2682 case MVT::v64i8: in getRegForInlineAsmConstraint()
2826 case MVT::v64i8: in findRepresentativeClass()
|
| D | HexagonISelDAGToDAG.cpp | 406 LoadedVT == MVT::v32i16 || LoadedVT == MVT::v64i8) { in SelectIndexedLoad()
527 StoredVT == MVT::v32i16 || StoredVT == MVT::v64i8) { in SelectIndexedStore()
569 StoredVT == MVT::v32i16 || StoredVT == MVT::v64i8) in SelectIndexedStore()
|
| D | HexagonRegisterInfo.td | 217 def VectorRegs : RegisterClass<"Hexagon", [v64i8, v32i16, v16i32, v8i64], 512,
|
| D | HexagonInstrInfoVector.td | 78 defm : bitconvert_vec<v64i8, v16i32>;
|
| D | HexagonInstrInfoV60.td | 814 defm : vS32b_ai_pats <v64i8, v128i8>;
867 defm : vL32b_ai_pats <v64i8, v128i8>;
|
| D | HexagonInstrInfo.cpp | 2285 VT == MVT::v32i16 || VT == MVT::v64i8) { in isValidAutoIncImm()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 216 def SReg_512 : RegisterClass<"AMDGPU", [v64i8, v16i32], 32, (add SGPR_512)> {
|
| D | SIISelLowering.cpp | 46 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass); in SITargetLowering()
|
| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 87 case MVT::v64i8: return "MVT::v64i8"; in getEnumName()
|
| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 173 def llvm_v64i8_ty : LLVMType<v64i8>; // 64 x i8
|