| /external/llvm/test/MC/ARM/ |
| D | thumb-diagnostics.s | 58 @ Invalid writeback and register lists for LDM
74 @ CHECK-ERRORS: error: writeback operator '!' expected
77 @ CHECK-ERRORS: error: writeback operator '!' not allowed when base register in register list
80 @ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list
83 @ CHECK-ERRORS-V8: error: writeback register not allowed in register list
108 @ Invalid writeback and register lists for PUSH/POP
119 @ Invalid writeback and register lists for STM
134 @ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list
137 @ CHECK-ERRORS-V8: error: writeback register not allowed in register list
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| D | diagnostics.s | 464 @ CHECK-ERRORS: error: writeback register not allowed in register list
465 @ CHECK-ERRORS: error: writeback register not allowed in register list
466 @ CHECK-ERRORS: error: writeback register not allowed in register list
467 @ CHECK-ERRORS: error: writeback register not allowed in register list
488 @ CHECK-ERRORS: error: system STM cannot have writeback register
489 @ CHECK-ERRORS: error: writeback register only allowed on system LDM if PC in register-list
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| D | arm-load-store-multiple-deprecated.s | 204 @ CHECK-V7: error: writeback register not allowed in register list
207 @ CHECK-V7: error: writeback register not allowed in register list
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-diags.s | 155 ; Load pair instructions where Rt==Rt2 and writeback load/store instructions
182 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
185 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
188 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
191 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
224 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
227 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
230 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
233 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
236 ; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
[all …]
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| /external/clang/lib/CodeGen/ |
| D | CGCall.h | 93 Writeback writeback = { srcLV, temporary, toUse }; in addWriteback() local
94 Writebacks.push_back(writeback); in addWriteback()
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| D | CGCall.cpp | 2569 const CallArgList::Writeback &writeback) { in emitWriteback() argument
2570 const LValue &srcLV = writeback.Source; in emitWriteback()
2591 llvm::Value *value = CGF.Builder.CreateLoad(writeback.Temporary); in emitWriteback()
2604 if (writeback.ToUse) { in emitWriteback()
2612 CGF.EmitARCIntrinsicUse(writeback.ToUse); in emitWriteback()
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| /external/autotest/client/tests/wb_kupdate/ |
| D | README | 5 and waiting a maximum of 'max_flush_time' for writeback to flush the dirty
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| /external/autotest/tko/parsers/test/ |
| D | scenario_base.py | 240 def shelve_open(filename, flag='c', protocol=None, writeback=False): argument
244 return shelve.Shelf(dumbdbm.open(filename, flag), protocol, writeback)
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| /external/autotest/client/samples/ |
| D | control.fs_options | 23 ('ext3', '-o data=writeback', 'ext3writeback'),
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| /external/kernel-headers/original/uapi/drm/ |
| D | exynos_drm.h | 183 __u32 writeback; member
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 61 // consumes the pipe for one cycle at issue and another cycle at writeback.
90 // but only consume the pipe for one cycle at issue and a cycle at writeback.
203 // The ID pipe is consumed for 2 cycles: issue and writeback.
210 // The ID pipe is consumed for 2 cycles: issue and writeback.
626 // Only the first WriteVLD and WriteAdr for writeback matches def operands.
767 // Only the WriteAdr for writeback matches a def operands.
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | basic-a64-unpredictable.txt | 84 # Also unpredictable if writeback clashes with either transfer register
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1518 bool writeback = (P == 0) || (W == 1); in DecodeAddrMode2IdxInstruction() local
1520 if (P && writeback) in DecodeAddrMode2IdxInstruction()
1522 else if (!P && writeback) in DecodeAddrMode2IdxInstruction()
1525 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
1625 bool writeback = (W == 1) | (P == 0); in DecodeAddrMode3Instruction() local
1647 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
1661 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
1678 if (!type && writeback && Rn == 15) in DecodeAddrMode3Instruction()
1680 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
1695 if (!type && writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
[all …]
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| /external/autotest/client/profilers/powertop/src/ |
| D | Changelog | 33 * add suggestion to increase VM writeback timeout
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| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleA9.td | 448 // register file writeback!).
2313 // A9WriteAdr consumes AGU regardless address writeback. But it's
2323 // Store either has no def operands, or the one def for address writeback.
2341 // Load multiple with address writeback has an extra def operand in
2345 // resources are identical, For stores only the address writeback
2360 // Note: Unlike VLDM, VLD1 expects the writeback operand after the
2381 // address writeback.
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| D | ARMInstrNEON.td | 693 // ...with address register writeback:
849 // ...with address register writeback:
922 // ...with address register writeback:
981 // ...with address register writeback:
1106 // ...with address register writeback:
1169 // ...with address register writeback:
1240 // ...with address register writeback:
1317 // ...with address register writeback:
1404 // ...with address register writeback:
1479 // ...with address register writeback:
[all …]
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| /external/autotest/client/profilers/powertop/src/po/ |
| D | zh.po | 116 "Suggestion: increase the VM dirty writeback time from %1.2f to 15 seconds with:\n"
120 "建議: 使用下列指令延長 VM dirty writeback 資料回寫時間自 %1.2f 改為 15 秒鐘:\n"
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| D | id.po | 554 "Suggestion: increase the VM dirty writeback time from %1.2f to 15 seconds "
559 "Saran: naikkan waktu VM dirty writeback dari %1.2f ke 15 detik dengan:\n"
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| D | de.po | 526 "Suggestion: increase the VM dirty writeback time from %1.2f to 15 seconds with:\n"
530 "Vorschlag: Erhöhen Sie die \"VM dirty writeback time\" von %1.2f auf\n"
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| D | hu.po | 571 "Suggestion: increase the VM dirty writeback time from %1.2f to 15 seconds "
576 "Tanács: növeld meg a VM dirty writeback időt %1.2f -ről 15 mp-re a következő "
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| D | nl.po | 457 "Suggestion: increase the VM dirty writeback time from %1.2f to 15 seconds "
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| D | ja.po | 540 "Suggestion: increase the VM dirty writeback time from %1.2f to 15 seconds "
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | invalid-thumbv7.txt | 360 # 32-bit Thumb STM instructions cannot have a writeback register which appears
|
| /external/clang/docs/ |
| D | AutomaticReferenceCounting.rst | 957 * the conversion is a well-formed :ref:`pass-by-writeback
1002 Passing to an out parameter by writeback
1007 candidate for :arc-term:`pass-by-writeback`` if:
1013 a pass-by-writeback is always worse than an implicit conversion sequence not
1014 requiring a pass-by-writeback.
1016 The pass-by-writeback is ill-formed if the argument expression does not have a
1033 below, where their store to the writeback temporary is not immediately seen
1036 A pass-by-writeback is evaluated as follows:
1040 and no further work is required for the pass-by-writeback.
1129 caution in the following rules about writeback.
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| /external/clang/test/CodeGenObjCXX/ |
| D | arc.mm | 306 // a non-dependent message send that requires writeback.
|