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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/
Dreloc.d40 [[:xdigit:]]+[048cC][[:space:]]+DIR32[LM]SB[[:space:]]+esym
41 [[:xdigit:]]+[048cC][[:space:]]+GPREL32[LM]SB[[:space:]]+esym
42 [[:xdigit:]]+[048cC][[:space:]]+FPTR32[LM]SB[[:space:]]+esym
43 [[:xdigit:]]+[048cC][[:space:]]+PCREL32[LM]SB[[:space:]]+esym
44 [[:xdigit:]]+[048cC][[:space:]]+LTOFF_FPTR32[LM]SB[[:space:]]+esym
45 [[:xdigit:]]+[048cC][[:space:]]+SEGREL32[LM]SB[[:space:]]+esym
46 [[:xdigit:]]+[048cC][[:space:]]+SECREL32[LM]SB[[:space:]]+esym
47 [[:xdigit:]]+[048cC][[:space:]]+LTV32[LM]SB[[:space:]]+esym
48 [[:xdigit:]]+[048cC][[:space:]]+DTPREL32[LM]SB[[:space:]]+esym
52 [[:xdigit:]]+[08][[:space:]]+DIR64[LM]SB[[:space:]]+esym
[all …]
Dreloc-bad.l4 .*:[[:digit:]]+: (Error|Warning): .* LTOFF32[LM]SB .*
5 .*:[[:digit:]]+: (Error|Warning): .* LTOFF64[LM]SB .*
7 .*:[[:digit:]]+: (Error|Warning): .* PLTOFF32[LM]SB .*
24 .*:[[:digit:]]+: (Error|Warning): .* IPLT32[LM]SB .*
25 .*:[[:digit:]]+: (Error|Warning): .* IPLT64[LM]SB .*
27 .*:[[:digit:]]+: (Error|Warning): .* TPREL32[LM]SB .*
30 .*:[[:digit:]]+: (Error|Warning): .* LTOFF_TPREL32[LM]SB .*
31 .*:[[:digit:]]+: (Error|Warning): .* LTOFF_TPREL64[LM]SB .*
35 .*:[[:digit:]]+: (Error|Warning): .* DTPMOD32[LM]SB .*
38 .*:[[:digit:]]+: (Error|Warning): .* LTOFF_TPREL32[LM]SB .*
[all …]
Dpcrel.d23 0+10[[:space:]]+PCREL64[LM]SB[[:space:]]+esym
24 0+20[[:space:]]+PCREL64[LM]SB[[:space:]]+esym\+0x0+20
25 0+30[[:space:]]+PCREL64[LM]SB[[:space:]]+esym
26 0+40[[:space:]]+PCREL64[LM]SB[[:space:]]+esym-0x0+20
30 0+10[[:space:]]+PCREL32[LM]SB[[:space:]]+esym
31 0+20[[:space:]]+PCREL32[LM]SB[[:space:]]+esym\+0x0+20
32 0+30[[:space:]]+PCREL32[LM]SB[[:space:]]+esym
33 0+40[[:space:]]+PCREL32[LM]SB[[:space:]]+esym-0x0+20
Dreloc-uw.d8 0*00 SEGREL64[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)?
9 0*08 SEGREL64[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)?
10 0*10 SEGREL64[ML]SB[[:space:]]+\.IA_64\.unwind_info(\+0x[[:xdigit:]]*[08])?
11 0*18 SEGREL64[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)?
12 0*20 SEGREL64[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)?
13 0*28 SEGREL64[ML]SB[[:space:]]+\.IA_64\.unwind_info(\+0x[[:xdigit:]]*[08])?
Dreloc-uw-ilp32.d10 0*00 SEGREL32[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)?
11 0*04 SEGREL32[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)?
12 0*08 SEGREL32[ML]SB[[:space:]]+\.IA_64\.unwind_info(\+0x[[:xdigit:]]*[048c])?
13 0*0c SEGREL32[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)?
14 0*10 SEGREL32[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)?
15 0*14 SEGREL32[ML]SB[[:space:]]+\.IA_64\.unwind_info(\+0x[[:xdigit:]]*[048c])?
/toolchain/binutils/binutils-2.25/include/opcode/
Dh8300.h1182 SB = 0, enumerator
1194 {O (O_ADD, SB), AV_H8, 2, "add.b", {{IMM8, RD8, E}}, {{0x8, RD8, IMM8LIST, E}}},
1195 EXPAND_TWOOP_B (O (O_ADD, SB), "add.b", 0x8, 0x0, 0x8, 0x1, 0),
1210 {O (O_ADDX, SB), AV_H8, 2, "addx", {{IMM8, RD8, E}}, {{0x9, RD8, IMM8LIST, E}}},
1211 …{O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNOR…
1212 …{O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 |…
1213 …{O (O_ADDX, SB), AV_H8, 2, "addx", {{RS8, RD8, E}}, {{0x0, 0xe, RS8, RD8, E}}},
1214 …{O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNOR…
1215 …{O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 |…
1216 …{O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNOR…
[all …]
/toolchain/binutils/binutils-2.25/opcodes/
Drl78-decode.opc125 #define SB(b) set_bit (rl78->op+1, b)
126 #define SCY() SR(PSW); SB(0)
316 ID(and); DCY(); SM(HL, 0); SB(bit);
319 ID(and); DCY(); SR(A); SB(bit);
322 ID(and); DCY(); SM(None, SFR); SB(bit);
325 ID(and); DCY(); SM(None, SADDR); SB(bit);
353 ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(F);
356 ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(F);
359 ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(F);
362 ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(F);
[all …]
Drl78-decode.c126 #define SB(b) set_bit (rl78->op+1, b) macro
127 #define SCY() SR(PSW); SB(0)
843 ID(branch_cond_clear); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T); in rl78_decode_opcode()
863 ID(branch_cond_clear); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T); in rl78_decode_opcode()
881 ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T); in rl78_decode_opcode()
901 ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T); in rl78_decode_opcode()
919 ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(F); in rl78_decode_opcode()
939 ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(F); in rl78_decode_opcode()
1129 ID(branch_cond_clear); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T); in rl78_decode_opcode()
1147 ID(branch_cond_clear); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T); in rl78_decode_opcode()
[all …]
/toolchain/binutils/binutils-2.25/ld/testsuite/ld-arm/
Dgroup-relocs.s4 @ specific PC- and SB-relative offsets arise.
29 @ ALU, SB-relative
54 @ LDR, SB-relative
82 @ LDRS, SB-relative
110 @ LDC, SB-relative
Dunresolved-2.d1 #name: SB relocations failure test
Dattr-merge-3.attr12 Tag_ABI_PCS_R9_use: SB
/toolchain/binutils/binutils-2.25/gas/config/
Dtc-h8300.c1629 if ( this_try->opcode->how == O (O_MOV, SB) in build_bytes()
1630 || this_try->opcode->how == O (O_BCLR, SB) in build_bytes()
1631 || this_try->opcode->how == O (O_BAND, SB) in build_bytes()
1632 || this_try->opcode->how == O (O_BIAND, SB) in build_bytes()
1633 || this_try->opcode->how == O (O_BILD, SB) in build_bytes()
1634 || this_try->opcode->how == O (O_BIOR, SB) in build_bytes()
1635 || this_try->opcode->how == O (O_BIST, SB) in build_bytes()
1636 || this_try->opcode->how == O (O_BIXOR, SB) in build_bytes()
1637 || this_try->opcode->how == O (O_BLD, SB) in build_bytes()
1638 || this_try->opcode->how == O (O_BNOT, SB) in build_bytes()
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/rx/
Drx-asm-bad.s19 .SB 80H
20 ldc #80,SB
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/
Dsb1-ext-ps.s1 # source file to test assembly of SB-1 core's paired-single
Dsb1-ext-ps.d2 #name: SB-1 paired single extensions
Dsb1-ext-mdmx.s1 # Source file to test assembly of SB-1 MDMX subset instructions and extensions.
3 # SB-1 implements only the .ob MDMX instructions, and adds three additional
Dsb1-ext-mdmx.d2 #name: SB-1 MDMX subset and extensions
5 # Check SB-1 MDMX subset and extensions assembly and disassembly
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/
Dattr-names.d22 Tag_ABI_PCS_R9_use: SB
/toolchain/binutils/binutils-2.25/ld/testsuite/ld-tic6x/
Dsbr-reloc-global-rel.d1 #name: C6X SB-relative relocations, global symbols, REL
Dsbr-reloc-global.d1 #name: C6X SB-relative relocations, global symbols
Dsbr-reloc-local-rel.d1 #name: C6X SB-relative relocations, local symbols, REL
Dsbr-reloc-local.d1 #name: C6X SB-relative relocations, local symbols
Dsbr-reloc-local-r-rel.d1 #name: C6X SB-relative relocations, local symbols, -r, REL
Dsbr-reloc-local-r.d1 #name: C6X SB-relative relocations, local symbols, -r
/toolchain/binutils/binutils-2.25/cpu/
Dm32c.cpu1274 ; SB Register
1277 (comment "SB register")
1768 (dnop sb "SB register" (all-isas SEM-ONLY) h-sb f-nil)
2416 (name (.sym src16-16-8-SB-relative- xmode))
2429 (name (.sym src16-16-16-SB-relative- xmode))
2502 (name (.sym src32- offset -8-SB-relative- group - xmode))
2517 (name (.sym src32- offset -16-SB-relative- group - xmode))
2719 ; (name (.sym src32-24-8-SB-relative-indirect- xmode))
2732 ; (name (.sym src32-24-16-SB-relative-indirect- xmode))
2862 (name (.sym src mach -2-S-8-SB-relative- xmode))
[all …]

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