Searched refs:instructions (Results 1 – 25 of 904) sorted by relevance
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/d30v/ |
| D | serial2.l | 2 .*:5: Error: Unable to mix instructions as specified
3 .*:6: Error: Unable to mix instructions as specified
4 .*:8: Error: Unable to mix instructions as specified
5 .*:9: Error: Unable to mix instructions as specified
6 .*:11: Error: Unable to mix instructions as specified
7 .*:12: Error: Unable to mix instructions as specified
8 .*:13: Error: Unable to mix instructions as specified
9 .*:14: Error: Unable to mix instructions as specified
10 .*:16: Error: Unable to mix instructions as specified
11 .*:17: Error: Unable to mix instructions as specified
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| D | serial2O.l | 2 .*:5: Error: Unable to mix instructions as specified
3 .*:6: Error: Unable to mix instructions as specified
4 .*:11: Error: Unable to mix instructions as specified
5 .*:12: Error: Unable to mix instructions as specified
6 .*:16: Error: Unable to mix instructions as specified
7 .*:17: Error: Unable to mix instructions as specified
8 .*:21: Error: Unable to mix instructions as specified
9 .*:22: Error: Unable to mix instructions as specified
10 .*:26: Error: Unable to mix instructions as specified
11 .*:27: Error: Unable to mix instructions as specified
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| D | serial.l | 2 .*:6: Error: Unable to mix instructions as specified
3 .*:7: Error: Unable to mix instructions as specified
4 .*:8: Error: Unable to mix instructions as specified
5 .*:9: Error: Unable to mix instructions as specified
15 .* Error: Unable to mix instructions as specified
18 .* Error: Unable to mix instructions as specified
23 .* Error: Unable to mix instructions as specified
28 .* Error: Unable to mix instructions as specified
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| D | x86-64-mpx-inval-2.l | 3 .*:7: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
5 .*:11: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
7 .*:14: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
9 .*:18: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
11 .*:22: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
13 .*:26: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
15 .*:30: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
17 .*:34: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
19 .*:38: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
21 .*:42: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| D | armv8-a-it-bad.l | 2 .*:7: Warning: IT blocks containing 32-bit Thumb instructions are deprecated in ARMv8
5 .*:30: Warning: IT blocks containing 32-bit Thumb instructions are deprecated in ARMv8
7 .*:40: Warning: IT blocks containing 16-bit Thumb instructions of the following class are deprecate…
8 …ocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Miscella…
9 .*:49: Warning: IT blocks containing 16-bit Thumb instructions of the following class are deprecate…
10 .*:52: Warning: IT blocks containing 16-bit Thumb instructions of the following class are deprecate…
11 .*:55: Warning: IT blocks containing 16-bit Thumb instructions of the following class are deprecate…
15 .*:61: Warning: IT blocks containing 16-bit Thumb instructions of the following class are deprecate…
16 .*:65: Warning: IT blocks containing 16-bit Thumb instructions of the following class are deprecate…
17 .*:68: Warning: IT blocks containing 16-bit Thumb instructions of the following class are deprecate…
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| D | macro-warn-1.l | 2 .*:5: Warning: macro instruction expanded into multiple instructions
3 .*:10: Warning: macro instruction expanded into multiple instructions
4 .*:11: Warning: macro instruction expanded into multiple instructions
5 .*:12: Warning: macro instruction expanded into multiple instructions
6 .*:16: Warning: macro instruction expanded into multiple instructions.*slot
7 .*:18: Warning: macro instruction expanded into multiple instructions.*slot
8 .*:20: Warning: macro instruction expanded into multiple instructions.*slot
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| D | macro-warn-1-n32.l | 2 .*:6: Warning: macro instruction expanded into multiple instructions
3 .*:10: Warning: macro instruction expanded into multiple instructions
4 .*:12: Warning: macro instruction expanded into multiple instructions
5 .*:16: Warning: macro instruction expanded into multiple instructions.*slot
6 .*:20: Warning: macro instruction expanded into multiple instructions.*slot
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| D | micromips-branch-delay.l | 9 .*:90: Warning: macro instruction expanded into multiple instructions in a branch delay slot
15 .*:100: Warning: macro instruction expanded into multiple instructions in a branch delay slot
16 .*:110: Warning: macro instruction expanded into multiple instructions in a branch delay slot
17 .*:121: Warning: macro instruction expanded into multiple instructions in a branch delay slot
23 .*:131: Warning: macro instruction expanded into multiple instructions in a branch delay slot
24 .*:141: Warning: macro instruction expanded into multiple instructions in a branch delay slot
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| D | mips64r2.s | 1 # source file to test assembly of mips64r2 instructions
2 # (assumes that mips32r2 instructions will be tested separately for mips64r2.)
10 # unprivileged CPU instructions
30 # non-macro instructions.
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| D | mips-gp64-fp64.l | 2 .*:92: Warning: macro instruction expanded into multiple instructions in a branch delay slot
3 .*:96: Warning: macro instruction expanded into multiple instructions in a branch delay slot
4 .*:100: Warning: macro instruction expanded into multiple instructions in a branch delay slot
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| D | mips32r2-fp32.s | 1 # source file to test assembly of mips32r2 FP instructions
6 # FPU (cp1) instructions
10 # Only the 32-bit FPU instructions are tested here.
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| D | mips32r2.s | 1 # source file to test assembly of mips32r2 *non-fp* instructions
9 # unprivileged CPU instructions
52 # cp0 instructions
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| /toolchain/binutils/binutils-2.25/gas/doc/ |
| D | c-xtensa.texi | 46 @code{L32R} instructions in the text section. These options only affect
47 literals referenced via PC-relative @code{L32R} instructions; literals
48 for absolute mode @code{L32R} instructions are handled separately.
54 Indicate to the assembler whether @code{L32R} instructions use absolute
66 that the assembler will always align instructions like @code{LOOP} that
72 Enable or disable transformation of call instructions to allow calls
83 Enable or disable all assembler transformations of Xtensa instructions,
86 rare cases when the instructions must be exactly as specified in the
98 Enable or disable transformation of jump instructions to allow jumps
131 FLIX instructions, which bundle multiple opcodes together in a single
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| D | c-z80.texi | 36 request warnings and error messages for undocumented instructions.
37 @item -ignore-undocumented-instructions
39 Silently assemble undocumented Z80-instructions that have been adopted
40 as documented R800-instructions.
41 @item -ignore-unportable-instructions
43 Silently assemble all undocumented Z80-instructions.
44 @item -warn-undocumented-instructions
46 Issue warnings for undocumented Z80-instructions that work on R800, do
47 not assemble other undocumented instructions without warning.
48 @item -warn-unportable-instructions
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| D | c-mips.texi | 29 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
35 generation of MIPS ASE instructions
119 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
164 provides a number of new instructions which target smartcard and
172 This tells the assembler to accept MIPS-3D instructions.
178 This tells the assembler to accept MDMX instructions.
184 This tells the assembler to accept DSP Release 1 instructions.
191 This tells the assembler to accept DSP Release 2 instructions.
197 This tells the assembler to accept MT instructions.
203 This tells the assembler to accept MCU instructions.
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| D | c-i386.texi | 75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
213 conjunction with the @option{-march} option, only instructions
223 This option specifies that the assembler should encode SSE instructions
231 These options control if the assembler should check SSE instructions.
233 instructions, which is the default. @option{-msse-check=@var{warning}}
243 instructions. @option{-mavxscalar=@var{128}} will encode scalar
244 AVX instructions with 128bit vector length, which is the default.
245 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
254 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
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| D | c-d10v.texi | 31 The D10V can often execute two sub-instructions in parallel. When this option
33 instructions can be executed in parallel.
36 order of instructions. Normally this generates a warning. When this option
37 is used, no warning will be generated when instructions are swapped.
40 @code{@value{AS}} packs adjacent short instructions into a single packed
79 Objdump and GDB will always append @samp{.s} or @samp{.l} to instructions which
84 @cindex D10V sub-instructions
85 @cindex sub-instructions, D10V
86 The D10V assembler takes as input a series of instructions, either one-per-line,
88 instructions will be short-form or sub-instructions. These sub-instructions can be packed
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| D | c-d30v.texi | 31 The D30V can often execute two sub-instructions in parallel. When this option
33 instructions can be executed in parallel.
77 Objdump and GDB will always append @samp{.s} or @samp{.l} to instructions which
82 @cindex D30V sub-instructions
83 @cindex sub-instructions, D30V
84 The D30V assembler takes as input a series of instructions, either one-per-line,
86 instructions will be short-form or sub-instructions. These sub-instructions can be packed
88 when it should not pack instructions. For example, when a label is defined, the next
111 Sub-instructions may be executed in order, in reverse-order, or in parallel.
128 the execution symbol, or two instructions per line. For example
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| D | c-m32r.texi | 39 to the M32RX microprocessor, which adds some more instructions to the
41 the original instructions.
86 instructions into a single, parallel instruction, where it is legal to
96 instructions provided by the M32R2. If this support needs to be
102 instructions that it produces. This includes filling delay slots and
103 converting sequential instructions into parallel ones. This option
109 questionable parallel instructions are encountered. This option is
111 @code{@value{AS}} directly. Questionable instructions are those whose
126 questionable parallel instructions are encountered.
136 instructions for constraint violations. This ability is provided for
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| D | c-ppc.texi | 30 core instruction set, but including a few additional instructions at
32 instructions each variant supports, please see the chip's architecture
64 Generate code for PowerPC 440. BookE and some 405 instructions.
97 Generate code for Motorola SPE instructions.
115 Generate code for processors with AltiVec instructions.
118 Generate code for Freescale PowerPC VLE instructions.
121 Generate code for processors with Vector-Scalar (VSX) instructions.
124 Generate code for processors with Hardware Transactional Memory instructions.
146 Generate code Power/PowerPC common instructions.
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| D | c-tilepro.texi | 44 There are two ways to write code: either write naked instructions,
55 instructions on a line, whether in a bundle or not, you need to
58 A bundle may contain one or more instructions, up to the limit
59 specified by the ISA (currently three). If fewer instructions are
61 inserts @code{fnop} instructions automatically.
63 The assembler will prefer to preserve the ordering of instructions
66 optional use of explicit @code{fnop} or @code{nop} instructions,
69 If the instructions cannot be bundled in the listed order, the
71 assignment. If there is no way to bundle the instructions together,
75 instructions into one bundle), but it reserves the right to do so in
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| D | c-i860.texi | 60 Select big endian output. Note that the i860 always reads instructions
62 instructions.
66 will be expanded into two instructions. This is a very undesirable feature to
69 where @code{gcc} may emit these pseudo-instructions.
71 Enable support for the i860XP instructions and control registers. By default,
121 All of the Intel i860XR and i860XP machine instructions are supported. Please see
123 @subsection Other instruction support (pseudo-instructions)
125 pseudo-instructions are supported. While these are supported, they are
127 they result in an expansion to multiple actual i860 instructions. Below
128 are the pseudo-instructions that result in expansions.
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| /toolchain/binutils/binutils-2.25/opcodes/ |
| D | arc-ext.c | 49 if (!arc_extension_map.instructions[opcode]) in arcExtMap_instName()
51 *flags = arc_extension_map.instructions[opcode]->flags; in arcExtMap_instName()
52 return arc_extension_map.instructions[opcode]->name; in arcExtMap_instName()
127 insn = arc_extension_map.instructions[i]; in cleanup_ext_map()
193 arc_extension_map.instructions[(int) opcode] = insn; in arcExtMap_add()
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/crx/ |
| D | br_insn.s | 1 # Branch instructions.
7 # conditional branch instructions.
98 # Decrement and Branch instructions.
114 # Branch/Jump and link instructions.
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| D | bit_insn.s | 1 # Bit instructions.
7 # cbit instructions.
43 # sbit instructions.
79 # tbit instructions.
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