1%default {"preinstr":"", "result":"w0", "chkzero":"0"}
2    /*
3     * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
4     * that specifies an instruction that performs "result = w0 op w1".
5     * This could be an ARM instruction or a function call.  (If the result
6     * comes back in a register other than w0, you can override "result".)
7     *
8     * If "chkzero" is set to 1, we perform a divide-by-zero check on
9     * vCC (w1).  Useful for integer division and modulus.
10     *
11     * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
12     *      rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
13     *      shl-int/lit8, shr-int/lit8, ushr-int/lit8
14     */
15    /* binop/lit8 vAA, vBB, #+CC */
16    FETCH_S w3, 1                       // w3<- ssssCCBB (sign-extended for CC
17    lsr     w9, wINST, #8               // w9<- AA
18    and     w2, w3, #255                // w2<- BB
19    GET_VREG w0, w2                     // w0<- vBB
20    asr    w1, w3, #8                   // w1<- ssssssCC (sign extended)
21    .if $chkzero
22    cbz     w1, common_errDivideByZero
23    .endif
24    FETCH_ADVANCE_INST 2                // advance rPC, load rINST
25    $preinstr                           // optional op; may set condition codes
26    $instr                              // $result<- op, w0-w3 changed
27    GET_INST_OPCODE ip                  // extract opcode from rINST
28    SET_VREG $result, w9                // vAA<- $result
29    GOTO_OPCODE ip                      // jump to next instruction
30    /* 10-12 instructions */
31