1 /******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20
21 /*****************************************************************************/
22 /* Includes */
23 /*****************************************************************************/
24
25 /* System include files */
26 #include "stdio.h"
27
28 /* User include files */
29 #include "irc_datatypes.h"
30 #include "irc_common.h"
31 #include "irc_cntrl_param.h"
32 #include "irc_mem_req_and_acq.h"
33 #include "irc_rd_model.h"
34 #include "irc_est_sad.h"
35 #include "irc_fixed_point_error_bits.h"
36 #include "irc_vbr_storage_vbv.h"
37 #include "irc_picture_type.h"
38 #include "irc_bit_allocation.h"
39 #include "irc_mb_model_based.h"
40 #include "irc_cbr_buffer_control.h"
41 #include "irc_vbr_str_prms.h"
42 #include "irc_rate_control_api.h"
43 #include "irc_rate_control_api_structs.h"
44 #include "irc_trace_support.h"
45
46
47 #define MIN(a,b) (((a) < (b)) ? (a) : (b))
48 #define MAX(a,b) (((a) > (b)) ? (a) : (b))
49
50 #define DEV_Q 4 /*Q format(Shift) for Deviation range factor */
51 #define HI_DEV_FCTR 22 /* 1.4*16 */
52 #define LO_DEV_FCTR 12 /* 0.75*16 */
53 #define GET_HI_DEV_QP(Qprev) (( ((WORD32) Qprev)*HI_DEV_FCTR + (1<<(DEV_Q-1)))>>DEV_Q)
54 #define GET_LO_DEV_QP(Qprev) (( ((WORD32) Qprev)*LO_DEV_FCTR + (1<<(DEV_Q-1)))>>DEV_Q)
55 #define CLIP_QP(Qc, hi_d, lo_d) (((Qc) < (lo_d))?((lo_d)):(((Qc) > (hi_d))?(hi_d):(Qc)))
56
57 /*****************************************************************************/
58 /* Restricts the quantization parameter variation within delta */
59 /*****************************************************************************/
60 /* static WORD32 restrict_swing(WORD32 cur_qp, WORD32 prev_qp, WORD32 delta_qp)
61 {
62 if((cur_qp) - (prev_qp) > (delta_qp)) (cur_qp) = (prev_qp) + (delta_qp) ;
63 if((prev_qp) - (cur_qp) > (delta_qp)) (cur_qp) = (prev_qp) - (delta_qp) ;
64 return cur_qp;
65 }*/
66
67 /*****************************************************************************
68 Function Name : rate_control_get_init_free_memtab
69 Description : Takes or gives memtab
70 Inputs : pps_rate_control_api - pointer to RC api pointer
71 ps_memtab - Memtab pointer
72 i4_use_base - Set during init, else 0
73 i4_fill_base - Set during free, else 0
74 *****************************************************************************/
irc_rate_control_num_fill_use_free_memtab(rate_control_handle * pps_rate_control_api,itt_memtab_t * ps_memtab,ITT_FUNC_TYPE_E e_func_type)75 WORD32 irc_rate_control_num_fill_use_free_memtab(rate_control_handle *pps_rate_control_api,
76 itt_memtab_t *ps_memtab,
77 ITT_FUNC_TYPE_E e_func_type)
78 {
79 WORD32 i4_mem_tab_idx = 0, i;
80 rate_control_api_t s_temp_rc_api;
81
82 /*
83 * Hack for al alloc, during which we dont have any state memory.
84 * Dereferencing can cause issues
85 */
86 if(e_func_type == GET_NUM_MEMTAB || e_func_type == FILL_MEMTAB)
87 (*pps_rate_control_api) = &s_temp_rc_api;
88
89 /*for src rate control state structure*/
90 if(e_func_type != GET_NUM_MEMTAB)
91 {
92 fill_memtab(&ps_memtab[i4_mem_tab_idx], sizeof(rate_control_api_t),
93 ALIGN_128_BYTE, PERSISTENT, DDR);
94 use_or_fill_base(&ps_memtab[0], (void**)pps_rate_control_api,
95 e_func_type);
96 }
97 i4_mem_tab_idx++;
98
99 /* Get the memory requirement of lower modules */
100 i4_mem_tab_idx += irc_ba_num_fill_use_free_memtab(
101 &pps_rate_control_api[0]->ps_bit_allocation,
102 &ps_memtab[i4_mem_tab_idx], e_func_type);
103
104 i4_mem_tab_idx += irc_cbr_buffer_num_fill_use_free_memtab(
105 &pps_rate_control_api[0]->ps_cbr_buffer,
106 &ps_memtab[i4_mem_tab_idx], e_func_type);
107
108 i4_mem_tab_idx += irc_est_sad_num_fill_use_free_memtab(
109 &pps_rate_control_api[0]->ps_est_sad,
110 &ps_memtab[i4_mem_tab_idx], e_func_type);
111
112 i4_mem_tab_idx += irc_mbrc_num_fill_use_free_memtab(
113 &pps_rate_control_api[0]->ps_mb_rate_control,
114 &ps_memtab[i4_mem_tab_idx], e_func_type);
115
116 i4_mem_tab_idx += irc_vbr_vbv_num_fill_use_free_memtab(
117 &pps_rate_control_api[0]->ps_vbr_storage_vbv,
118 &ps_memtab[i4_mem_tab_idx], e_func_type);
119
120 for(i = 0; i < MAX_PIC_TYPE; i++)
121 {
122 i4_mem_tab_idx += irc_rd_model_num_fill_use_free_memtab(
123 &pps_rate_control_api[0]->aps_rd_model[i],
124 &ps_memtab[i4_mem_tab_idx], e_func_type);
125 }
126 i4_mem_tab_idx += irc_pic_handling_num_fill_use_free_memtab(
127 &pps_rate_control_api[0]->ps_pic_handling,
128 &ps_memtab[i4_mem_tab_idx], e_func_type);
129
130 return (i4_mem_tab_idx);
131 }
132
133 /*****************************************************************************
134 Function Name : irc_initialise_rate_control
135 Description : Initialise the rate control structure
136 Inputs : ps_rate_control_api - api struct
137 e_rate_control_type - VBR, CBR (NLDRC/LDRC), VBR_STREAMING
138 u1_is_mb_level_rc_on - enabling mb level RC
139 u4_avg_bit_rate - bit rate to achieved across the entire
140 file size
141 u4_peak_bit_rate - max possible drain rate
142 u4_frame_rate - number of frames in 1000 seconds
143 u4_intra_frame_interval - num frames between two I frames
144 *au1_init_qp - init_qp for I,P,B
145 *****************************************************************************/
irc_initialise_rate_control(rate_control_api_t * ps_rate_control_api,rc_type_e e_rate_control_type,UWORD8 u1_is_mb_level_rc_on,UWORD32 u4_avg_bit_rate,UWORD32 * pu4_peak_bit_rate,UWORD32 u4_min_bit_rate,UWORD32 u4_frame_rate,UWORD32 u4_max_delay,UWORD32 u4_intra_frame_interval,WORD32 i4_inter_frm_int,UWORD8 * pu1_init_qp,UWORD32 u4_max_vbv_buff_size,WORD32 i4_max_inter_frm_int,WORD32 i4_is_gop_closed,UWORD8 * pu1_min_max_qp,WORD32 i4_use_est_intra_sad,UWORD32 u4_src_ticks,UWORD32 u4_tgt_ticks)146 void irc_initialise_rate_control(rate_control_api_t *ps_rate_control_api,
147 rc_type_e e_rate_control_type,
148 UWORD8 u1_is_mb_level_rc_on,
149 UWORD32 u4_avg_bit_rate,
150 UWORD32 *pu4_peak_bit_rate,
151 UWORD32 u4_min_bit_rate,
152 UWORD32 u4_frame_rate,
153 UWORD32 u4_max_delay,
154 UWORD32 u4_intra_frame_interval,
155 WORD32 i4_inter_frm_int,
156 UWORD8 *pu1_init_qp,
157 UWORD32 u4_max_vbv_buff_size,
158 WORD32 i4_max_inter_frm_int,
159 WORD32 i4_is_gop_closed,
160 UWORD8 *pu1_min_max_qp,
161 WORD32 i4_use_est_intra_sad,
162 UWORD32 u4_src_ticks,
163 UWORD32 u4_tgt_ticks)
164 {
165 WORD32 i;
166 UWORD32 u4_frms_in_delay_prd = (u4_frame_rate * u4_max_delay) / 1000000;
167 ps_rate_control_api->e_rc_type = e_rate_control_type;
168 ps_rate_control_api->u1_is_mb_level_rc_on = u1_is_mb_level_rc_on;
169
170 trace_printf((const WORD8*)"RC type = %d\n", e_rate_control_type);
171
172 /* Set the avg_bitrate_changed flag for each pic_type to 0 */
173 for(i = 0; i < MAX_PIC_TYPE; i++)
174 {
175 ps_rate_control_api->au1_avg_bitrate_changed[i] = 0;
176 }
177
178 /* Initialize the pic_handling module */
179 irc_init_pic_handling(ps_rate_control_api->ps_pic_handling,
180 (WORD32)u4_intra_frame_interval,
181 i4_inter_frm_int, i4_max_inter_frm_int,
182 i4_is_gop_closed);
183
184 /*** Initialize the rate control modules ***/
185 if(ps_rate_control_api->e_rc_type != CONST_QP)
186 {
187 UWORD32 au4_num_pics_in_delay_prd[MAX_PIC_TYPE];
188
189 /* Initialize the model parameter structures */
190 for(i = 0; i < MAX_PIC_TYPE; i++)
191 {
192 irc_init_frm_rc_rd_model(ps_rate_control_api->aps_rd_model[i],
193 MAX_FRAMES_MODELLED);
194 }
195
196 /* Initialize the buffer mechanism */
197 if((ps_rate_control_api->e_rc_type == VBR_STORAGE)
198 || (ps_rate_control_api->e_rc_type
199 == VBR_STORAGE_DVD_COMP))
200 {
201 /* Assuming both the peak bit rates are same for a VBR_STORAGE and
202 VBR_STORAGE_DVD_COMP */
203 if(pu4_peak_bit_rate[0] != pu4_peak_bit_rate[1])
204 {
205 trace_printf((const WORD8*)"For VBR_STORAGE and VBR_STORAGE_DVD_COMP the peak bit rates should be same\n");
206 }
207 irc_init_vbr_vbv(ps_rate_control_api->ps_vbr_storage_vbv,
208 (WORD32)pu4_peak_bit_rate[0],
209 (WORD32)u4_frame_rate,
210 (WORD32)u4_max_vbv_buff_size);
211 }
212 else if(ps_rate_control_api->e_rc_type == CBR_NLDRC)
213 {
214 UWORD32 u4_avg_bit_rate_copy[MAX_NUM_DRAIN_RATES];
215 for(i = 0; i < MAX_NUM_DRAIN_RATES; i++)
216 {
217 u4_avg_bit_rate_copy[i] = u4_avg_bit_rate;
218 }
219 /* In case of CBR the num pics in delay is ignored */
220 for(i = 0; i < MAX_PIC_TYPE; i++)
221 au4_num_pics_in_delay_prd[i] = 0;
222
223 irc_init_cbr_buffer(ps_rate_control_api->ps_cbr_buffer,
224 u4_max_delay, u4_frame_rate,
225 (WORD32 *)u4_avg_bit_rate_copy,
226 au4_num_pics_in_delay_prd,
227 u4_max_vbv_buff_size);
228 }
229 else if(ps_rate_control_api->e_rc_type == VBR_STREAMING)
230 {
231 irc_init_vbv_str_prms(&ps_rate_control_api->s_vbr_str_prms,
232 u4_intra_frame_interval, u4_src_ticks,
233 u4_tgt_ticks, u4_frms_in_delay_prd);
234
235 /* Get the number of pics of each type in delay period */
236 irc_get_vsp_num_pics_in_dly_prd(
237 &ps_rate_control_api->s_vbr_str_prms,
238 au4_num_pics_in_delay_prd);
239
240 irc_init_cbr_buffer(ps_rate_control_api->ps_cbr_buffer,
241 u4_max_delay, u4_frame_rate,
242 (WORD32 *)pu4_peak_bit_rate,
243 au4_num_pics_in_delay_prd,
244 u4_max_vbv_buff_size);
245 }
246
247 /* Initialize the SAD estimation module */
248 irc_init_est_sad(ps_rate_control_api->ps_est_sad, i4_use_est_intra_sad);
249
250 /* Initialize the bit allocation module according to VBR or CBR */
251 if((ps_rate_control_api->e_rc_type == VBR_STORAGE)
252 || (ps_rate_control_api->e_rc_type == VBR_STREAMING)
253 || (ps_rate_control_api->e_rc_type
254 == VBR_STORAGE_DVD_COMP))
255 {
256 irc_ba_init_bit_allocation(ps_rate_control_api->ps_bit_allocation,
257 ps_rate_control_api->ps_pic_handling,
258 VBR_BIT_ALLOC_PERIOD, u4_avg_bit_rate,
259 u4_frame_rate,
260 (WORD32 *)pu4_peak_bit_rate,
261 u4_min_bit_rate);
262 }
263 else if(ps_rate_control_api->e_rc_type == CBR_NLDRC)
264 {
265 irc_ba_init_bit_allocation(ps_rate_control_api->ps_bit_allocation,
266 ps_rate_control_api->ps_pic_handling,
267 CBR_BIT_ALLOC_PERIOD, u4_avg_bit_rate,
268 u4_frame_rate,
269 (WORD32 *)pu4_peak_bit_rate,
270 u4_min_bit_rate);
271 }
272
273 /*
274 * u1_scd_detected will be initialized to 1 when a Scene change is
275 * detected
276 */
277 ps_rate_control_api->u1_scd_detected = 0;
278 }
279
280 /* Initialize the init_qp */
281 for(i = 0; i < MAX_PIC_TYPE; i++)
282 {
283 ps_rate_control_api->au1_init_qp[i] = pu1_init_qp[i];
284 ps_rate_control_api->au1_prev_frm_qp[i] = pu1_init_qp[i];
285 ps_rate_control_api->au1_min_max_qp[(i << 1)] =
286 pu1_min_max_qp[(i << 1)];
287 ps_rate_control_api->au1_min_max_qp[(i << 1) + 1] = pu1_min_max_qp[(i
288 << 1) + 1];
289 }
290
291 /* Initialize the is_first_frm_encoded */
292 for(i = 0; i < MAX_PIC_TYPE; i++)
293 {
294 ps_rate_control_api->au1_is_first_frm_coded[i] = 0;
295 }
296 ps_rate_control_api->u1_is_first_frm = 1;
297
298 /*
299 * Control flag for delayed impact after a change in peak bitrate has been
300 * made
301 */
302 ps_rate_control_api->u4_frms_in_delay_prd_for_peak_bit_rate_change = 0;
303 for(i = 0; i < MAX_NUM_DRAIN_RATES; i++)
304 {
305 ps_rate_control_api->au4_new_peak_bit_rate[i] = pu4_peak_bit_rate[i];
306 }
307
308 /* Initialize the mb level rate control module */
309 irc_init_mb_level_rc(ps_rate_control_api->ps_mb_rate_control);
310 ps_rate_control_api->i4_prev_frm_est_bits = u4_avg_bit_rate * 1000
311 / u4_frame_rate;
312
313 ps_rate_control_api->prev_ref_pic_type = I_PIC;
314 }
315
316 /******************************************************************************
317 *Description : calls irc_add_pic_to_stack
318 ******************************************************************************/
irc_add_picture_to_stack(rate_control_api_t * rate_control_api,WORD32 i4_enc_pic_id)319 void irc_add_picture_to_stack(rate_control_api_t *rate_control_api,
320 WORD32 i4_enc_pic_id)
321 {
322 /* Call the routine to add the pic to stack in encode order */
323 irc_add_pic_to_stack(rate_control_api->ps_pic_handling, i4_enc_pic_id);
324 }
325
irc_add_picture_to_stack_re_enc(rate_control_api_t * rate_control_api,WORD32 i4_enc_pic_id,picture_type_e e_pic_type)326 void irc_add_picture_to_stack_re_enc(rate_control_api_t *rate_control_api,
327 WORD32 i4_enc_pic_id,
328 picture_type_e e_pic_type)
329 {
330 /*
331 * In case of a re-encoder, the pics will come in the encode order itself.
332 * So, there is no need to buffer the pics up
333 */
334 irc_add_pic_to_stack_re_enc(rate_control_api->ps_pic_handling,
335 i4_enc_pic_id, e_pic_type);
336 }
337
338 /*******************************************************************************
339 Description : Decides the picture type based on the state
340 ******************************************************************************/
irc_get_picture_details(rate_control_handle rate_control_api,WORD32 * pi4_pic_id,WORD32 * pi4_pic_disp_order_no,picture_type_e * pe_pic_type)341 void irc_get_picture_details(rate_control_handle rate_control_api,
342 WORD32 *pi4_pic_id,
343 WORD32 *pi4_pic_disp_order_no,
344 picture_type_e *pe_pic_type)
345 {
346 /* Call to get the pic_details */
347 irc_get_pic_from_stack(rate_control_api->ps_pic_handling, pi4_pic_id,
348 pi4_pic_disp_order_no, pe_pic_type);
349 }
350
351 /*******************************************************************************
352 * Description : Gets the frame level qp for the given picture type
353 ******************************************************************************/
irc_get_frame_level_qp(rate_control_api_t * ps_rate_control_api,picture_type_e e_pic_type,WORD32 i4_ud_max_bits)354 UWORD8 irc_get_frame_level_qp(rate_control_api_t *ps_rate_control_api,
355 picture_type_e e_pic_type,
356 WORD32 i4_ud_max_bits)
357 {
358 UWORD8 u1_frame_qp, i;
359
360 if((ps_rate_control_api->e_rc_type != VBR_STORAGE)
361 && (ps_rate_control_api->e_rc_type != VBR_STORAGE_DVD_COMP)
362 && (ps_rate_control_api->e_rc_type != CBR_NLDRC)
363 && (ps_rate_control_api->e_rc_type != CONST_QP)
364 && (ps_rate_control_api->e_rc_type != VBR_STREAMING))
365 {
366 trace_printf((const WORD8*)(const WORD8*)" Only VBR,NLDRC and CONST QP supported for now \n");
367 return (0);
368 }
369
370 if(ps_rate_control_api->e_rc_type != CONST_QP)
371 {
372 UWORD8 u1_is_first_frm_coded = 1;
373
374 /* Check whether at least one frame of a each picture type gets encoded*/
375 /* Check whether it is an IPP or IPB kind of encoding */
376 if((ps_rate_control_api->au1_is_first_frm_coded[I_PIC]
377 && ps_rate_control_api->au1_is_first_frm_coded[P_PIC])
378 || ((irc_pic_type_get_intra_frame_interval(
379 ps_rate_control_api->ps_pic_handling)
380 == 1)
381 && (ps_rate_control_api->au1_is_first_frm_coded[I_PIC])))
382 {
383 if(e_pic_type != B_PIC)
384 u1_is_first_frm_coded = 1;
385 else
386 {
387 for(i = 0; i < MAX_PIC_TYPE; i++)
388 {
389 u1_is_first_frm_coded &=
390 ps_rate_control_api->au1_is_first_frm_coded[i];
391 }
392 }
393 }
394 else
395 {
396 u1_is_first_frm_coded = 0;
397 }
398
399 if(u1_is_first_frm_coded)
400 {
401 WORD32 i4_cur_est_texture_bits, i4_cur_est_header_bits;
402 WORD32 i4_cur_est_bits;
403 UWORD32 u4_estimated_sad;
404
405 /* Force I frame updation of rem_bits_in_frame*/
406 if(irc_get_forced_I_frame_cur_frm_flag(
407 ps_rate_control_api->ps_pic_handling) == 1)
408 {
409 irc_ba_change_rem_bits_in_prd_at_force_I_frame(
410 ps_rate_control_api->ps_bit_allocation,
411 ps_rate_control_api->ps_pic_handling);
412 irc_reset_forced_I_frame_cur_frm_flag(
413 ps_rate_control_api->ps_pic_handling);
414 }
415
416 /* Get the estimated texture bits allocated for the current frame*/
417 i4_cur_est_texture_bits = irc_ba_get_cur_frm_est_texture_bits(
418 ps_rate_control_api->ps_bit_allocation,
419 ps_rate_control_api->aps_rd_model,
420 ps_rate_control_api->ps_est_sad,
421 ps_rate_control_api->ps_pic_handling, e_pic_type);
422
423 /* Get the estimated header bits*/
424 i4_cur_est_header_bits = irc_ba_get_cur_frm_est_header_bits(
425 ps_rate_control_api->ps_bit_allocation, e_pic_type);
426
427 /* Total estimated bits */
428 i4_cur_est_bits = i4_cur_est_header_bits + i4_cur_est_texture_bits;
429
430 trace_printf((const WORD8*)"ft %d, etb = %d, eb %d, ", e_pic_type,
431 i4_cur_est_texture_bits, i4_cur_est_bits);
432
433 /* Threshold the estimated bits based on the buffer fullness*/
434 if(ps_rate_control_api->e_rc_type == VBR_STORAGE)
435 {
436 WORD32 i4_cur_frm_max_bit_possible;
437 i4_cur_frm_max_bit_possible = irc_get_max_target_bits(
438 ps_rate_control_api->ps_vbr_storage_vbv);
439
440 if(i4_cur_est_bits > i4_cur_frm_max_bit_possible)
441 {
442 /* Assuming header would consume the same amount of bits */
443 i4_cur_est_texture_bits = i4_cur_frm_max_bit_possible
444 - i4_cur_est_header_bits;
445 }
446 }
447 else if(ps_rate_control_api->e_rc_type == VBR_STORAGE_DVD_COMP)
448 {
449 WORD32 i4_rem_bits_in_gop, i4_rem_frms_in_gop, i;
450 WORD32 i4_cur_frm_max_bit_possible,
451 ai4_rem_frms_in_gop[MAX_PIC_TYPE];
452 irc_pic_type_get_rem_frms_in_gop(
453 ps_rate_control_api->ps_pic_handling,
454 ai4_rem_frms_in_gop);
455 i4_rem_bits_in_gop = irc_get_rem_bits_in_period(
456 ps_rate_control_api);
457 i4_rem_frms_in_gop = 0;
458 for(i = 0; i < MAX_PIC_TYPE; i++)
459 i4_rem_frms_in_gop += ai4_rem_frms_in_gop[i];
460
461 /* Threshold the bits based on estimated buffer fullness */
462 i4_cur_frm_max_bit_possible = irc_get_max_tgt_bits_dvd_comp(
463 ps_rate_control_api->ps_vbr_storage_vbv,
464 i4_rem_bits_in_gop, i4_rem_frms_in_gop,
465 e_pic_type);
466
467 if(i4_cur_est_bits > i4_cur_frm_max_bit_possible)
468 {
469 /* Assuming header would consume the same amount of bits */
470 i4_cur_est_texture_bits = i4_cur_frm_max_bit_possible
471 - i4_cur_est_header_bits;
472
473 }
474 }
475 else if(ps_rate_control_api->e_rc_type == CBR_NLDRC)
476 {
477 WORD32 i4_cur_frm_bits_acc_buffer =
478 irc_cbr_buffer_constraint_check(
479 ps_rate_control_api->ps_cbr_buffer,
480 i4_cur_est_bits, e_pic_type);
481
482 /* Assuming the header would consume the same amount of bits */
483 i4_cur_est_texture_bits = i4_cur_frm_bits_acc_buffer
484 - i4_cur_est_header_bits;
485
486 }
487 else if(ps_rate_control_api->e_rc_type == VBR_STREAMING)
488 {
489 WORD32 i4_cur_frm_bits_acc_buffer =
490 irc_vbr_stream_buffer_constraint_check(
491 ps_rate_control_api->ps_cbr_buffer,
492 i4_cur_est_bits, e_pic_type);
493
494 /* Assuming the header would consume the same amount of bits */
495 i4_cur_est_texture_bits = i4_cur_frm_bits_acc_buffer
496 - i4_cur_est_header_bits;
497 }
498
499 trace_printf((const WORD8*)"emtb = %d, ", i4_cur_est_texture_bits);
500
501 /*
502 * If the estimated texture bits go to values less than zero
503 * due to buffer underflow, make the estimated target bits to go
504 * to zero
505 */
506 if(i4_cur_est_texture_bits < 0)
507 i4_cur_est_texture_bits = 0;
508
509 ps_rate_control_api->i4_prev_frm_est_bits = (i4_cur_est_texture_bits
510 + i4_cur_est_header_bits);
511
512 /* Clip est_texture_bits according to the user-defined max value */
513 if((i4_cur_est_texture_bits
514 > (i4_ud_max_bits - i4_cur_est_header_bits))
515 && (e_pic_type != I_PIC))
516 {
517 i4_cur_est_texture_bits = (i4_ud_max_bits
518 - i4_cur_est_header_bits);
519 trace_printf((const WORD8*)"udcb = %d, ",
520 i4_ud_max_bits - i4_cur_est_header_bits);
521 }
522
523 /* Calculate the estimated SAD for corresponding frame*/
524 u4_estimated_sad = irc_get_est_sad(ps_rate_control_api->ps_est_sad,
525 e_pic_type);
526
527 /* Query the model for the Qp for the corresponding frame*/
528
529 /*
530 * The check is because the model gives a negative QP when the
531 * i4_cur_est_texture_bits is less than or equal to 0
532 * [This is a bug in the model]. As a temporary fix, the frame QP
533 * is being set to the max QP allowed
534 */
535 if(i4_cur_est_texture_bits > 0)
536 {
537 u1_frame_qp = irc_find_qp_for_target_bits(
538 ps_rate_control_api->aps_rd_model[e_pic_type],
539 i4_cur_est_texture_bits,
540 u4_estimated_sad,
541 ps_rate_control_api->au1_min_max_qp[(e_pic_type
542 << 1)],
543 ps_rate_control_api->au1_min_max_qp[(e_pic_type
544 << 1) + 1]);
545 }
546 else
547 {
548 u1_frame_qp = ps_rate_control_api->au1_min_max_qp[(e_pic_type
549 << 1) + 1];
550 }
551
552 trace_printf((const WORD8*)"ehb %d, etb %d, fqp %d, es %d, eb %d, ",
553 i4_cur_est_header_bits, i4_cur_est_texture_bits,
554 u1_frame_qp, u4_estimated_sad, i4_cur_est_bits);
555
556 /* Restricting the QP swing if the average bit rate has changed */
557 if(ps_rate_control_api->au1_avg_bitrate_changed[e_pic_type] == 0)
558 {
559 WORD32 prev_qp;
560 WORD32 hi_dev_qp, lo_dev_qp;
561 /* Restricting the qp swing */
562 prev_qp = ps_rate_control_api->au1_prev_frm_qp[ps_rate_control_api->prev_ref_pic_type];
563
564 if(ps_rate_control_api->prev_ref_pic_type != e_pic_type)
565 {
566 if(e_pic_type == I_PIC)
567 {
568 /*
569 * Constrain I-frame QP to be within specified limit of
570 * prev_ref_qp/Kp
571 */
572 prev_qp = (P_TO_I_RATIO * prev_qp + (1 << (K_Q - 1)))
573 >> (K_Q);
574 }
575 else if(e_pic_type == P_PIC)
576 {
577 /*
578 * Constrain P-frame QP to be within specified limit of
579 * Kp*prev_ref_qp
580 */
581 prev_qp = (I_TO_P_RATIO * prev_qp + (1 << (K_Q - 1)))
582 >> (K_Q);
583 }
584 else if(ps_rate_control_api->prev_ref_pic_type == P_PIC)
585 {
586 /* current frame is B-pic */
587 /* Constrain B-frame QP to be within specified limit of
588 * prev_ref_qp/Kb
589 */
590 prev_qp = (P_TO_B_RATIO * prev_qp + (1 << (K_Q - 1)))
591 >> (K_Q);
592 }
593 else /* if(ps_rate_control_api->prev_ref_pic_type == I_PIC*/
594 {
595 /* current frame is B-pic */
596 /*
597 * Constrain B-frame QP to be within specified limit of
598 * prev_ref_qp/Kb
599 */
600 prev_qp = (P_TO_B_RATIO * I_TO_P_RATIO * prev_qp
601 + (1 << (K_Q + K_Q - 1)))
602 >> (K_Q + K_Q);
603 }
604 }
605
606 /*
607 * Due to the inexact nature of translation tables, QP may
608 * get locked at some values. This is because of the inexactness of
609 * the tables causing a change of +-1 in back and forth translations.
610 * In that case, if we restrict the QP swing to +-1, we will get
611 * the lock up condition. Hence we make it such that we will have
612 * a swing of atleast +- 2 from prev_qp
613 */
614
615 lo_dev_qp = GET_LO_DEV_QP(prev_qp);
616 lo_dev_qp = MIN(lo_dev_qp, prev_qp - 2);
617 lo_dev_qp = MAX(lo_dev_qp, ps_rate_control_api->au1_min_max_qp[(e_pic_type << 1)]);
618
619 hi_dev_qp = GET_HI_DEV_QP(prev_qp);
620 hi_dev_qp = MAX(hi_dev_qp, prev_qp + 2);
621 hi_dev_qp = MIN(hi_dev_qp, ps_rate_control_api->au1_min_max_qp[(e_pic_type << 1) + 1]);
622
623 u1_frame_qp = (UWORD8)CLIP_QP((WORD32)u1_frame_qp, hi_dev_qp , lo_dev_qp);
624
625 }
626 else
627 {
628 ps_rate_control_api->au1_avg_bitrate_changed[e_pic_type] = 0;
629 }
630 }
631 else
632 {
633 /*
634 * The u1_is_first_frm_coded gets reset
635 * a) at start of sequence
636 * b) whenever there is a scene change.
637 * In both cases since we do not have any estimate about the
638 * current frame, we just send in the previous frame qp value.IN
639 * Scene change case the previous QP is incremented by 4 , This is
640 * done because the Scene changed VOP will have over consumed and
641 * chances of future frames skipping is very high. For the init
642 * case, the previous frame QP is initialized with the init qp
643 */
644 if((ps_rate_control_api->u1_scd_detected)
645 && (ps_rate_control_api->e_rc_type != CONST_QP))
646 {
647 /*
648 * If scene change is detected, I frame Qp would have been
649 * updated
650 */
651 /* Use a QP calculated in the prev update fxn */
652 u1_frame_qp = ps_rate_control_api->u1_frm_qp_after_scd;
653 }
654 else
655 {
656 u1_frame_qp = ps_rate_control_api->au1_prev_frm_qp[e_pic_type];
657 }
658 }
659 }
660 else
661 {
662 u1_frame_qp = ps_rate_control_api->au1_init_qp[e_pic_type];
663 }
664
665 trace_printf((const WORD8*)"fqp %d\n", u1_frame_qp);
666
667 return (u1_frame_qp);
668 }
669
670 /*******************************************************************************
671 *Function Name : irc_get_buffer_status
672 *Description : Gets the state of VBV buffer
673 *Outputs : 0 = normal, 1 = underflow, 2= overflow
674 *Returns : vbv_buf_status_e
675 ******************************************************************************/
irc_get_buffer_status(rate_control_api_t * ps_rate_control_api,WORD32 i4_total_frame_bits,picture_type_e e_pic_type,WORD32 * pi4_num_bits_to_prevent_vbv_underflow)676 vbv_buf_status_e irc_get_buffer_status(rate_control_api_t *ps_rate_control_api,
677 WORD32 i4_total_frame_bits,
678 picture_type_e e_pic_type,
679 WORD32 *pi4_num_bits_to_prevent_vbv_underflow)
680 {
681 vbv_buf_status_e e_buf_status = VBV_NORMAL;
682
683 /* Get the buffer status for the current total consumed bits and error bits*/
684 if(ps_rate_control_api->e_rc_type == VBR_STORAGE_DVD_COMP)
685 {
686 e_buf_status = irc_get_vbv_buffer_status(
687 ps_rate_control_api->ps_vbr_storage_vbv,
688 i4_total_frame_bits,
689 pi4_num_bits_to_prevent_vbv_underflow);
690
691 trace_printf((const WORD8*)"e_buf_status = %d\n", e_buf_status);
692 }
693 else if(ps_rate_control_api->e_rc_type == VBR_STORAGE)
694 {
695 /* For VBR case since there is not underflow returning the max value */
696 pi4_num_bits_to_prevent_vbv_underflow[0] = irc_get_max_vbv_buf_size(
697 ps_rate_control_api->ps_vbr_storage_vbv);
698 e_buf_status = VBV_NORMAL;
699 }
700 else if(ps_rate_control_api->e_rc_type == CBR_NLDRC)
701 {
702 e_buf_status = irc_get_cbr_buffer_status(
703 ps_rate_control_api->ps_cbr_buffer, i4_total_frame_bits,
704 pi4_num_bits_to_prevent_vbv_underflow, e_pic_type);
705
706 }
707 else if(ps_rate_control_api->e_rc_type == VBR_STREAMING)
708 {
709 /* For VBR_streaming, error bits are computed according to peak bitrate*/
710 e_buf_status = irc_get_cbr_buffer_status(
711 ps_rate_control_api->ps_cbr_buffer, i4_total_frame_bits,
712 pi4_num_bits_to_prevent_vbv_underflow, e_pic_type);
713 }
714 return e_buf_status;
715 }
716
717 /*******************************************************************************
718 Function Name : irc_update_pic_handling_state
719 Description : If the forward path and the backward path of rate control
720 ******************************************************************************/
irc_update_pic_handling_state(rate_control_api_t * ps_rate_control_api,picture_type_e e_pic_type)721 void irc_update_pic_handling_state(rate_control_api_t *ps_rate_control_api,
722 picture_type_e e_pic_type)
723 {
724 irc_update_pic_handling(ps_rate_control_api->ps_pic_handling, e_pic_type);
725 }
726
727 /******************************************************************************
728 Function Name : irc_update_frame_level_info
729 Description : Updates the frame level information into the rate control
730 structure
731 ******************************************************************************/
irc_update_frame_level_info(rate_control_api_t * ps_rate_control_api,picture_type_e e_pic_type,WORD32 * pi4_mb_type_sad,WORD32 i4_total_frame_bits,WORD32 i4_model_updation_hdr_bits,WORD32 * pi4_mb_type_tex_bits,WORD32 * pi4_tot_mb_type_qp,WORD32 * pi4_tot_mb_in_type,WORD32 i4_avg_activity,UWORD8 u1_is_scd,WORD32 i4_is_it_a_skip,WORD32 i4_intra_frm_cost,WORD32 i4_is_pic_handling_done)732 void irc_update_frame_level_info(rate_control_api_t *ps_rate_control_api,
733 picture_type_e e_pic_type,
734 WORD32 *pi4_mb_type_sad,
735 WORD32 i4_total_frame_bits,
736 WORD32 i4_model_updation_hdr_bits,
737 WORD32 *pi4_mb_type_tex_bits,
738 WORD32 *pi4_tot_mb_type_qp,
739 WORD32 *pi4_tot_mb_in_type,
740 WORD32 i4_avg_activity,
741 UWORD8 u1_is_scd,
742 WORD32 i4_is_it_a_skip,
743 WORD32 i4_intra_frm_cost,
744 WORD32 i4_is_pic_handling_done)
745 {
746 UWORD8 u1_num_skips = 0;
747 WORD32 i;
748 UWORD32 u4_frame_sad = 0;
749 WORD32 i4_tot_texture_bits = 0;
750 WORD32 i4_tot_mbs = 0;
751 WORD32 i4_avg_qp = 0;
752
753 /* SCD not supported in case of IPB encoder */
754 if(u1_is_scd && (irc_pic_type_get_inter_frame_interval(
755 ps_rate_control_api->ps_pic_handling) > 1))
756 {
757 u1_is_scd = 0;
758 }
759 trace_printf((const WORD8*)"i4_total_frame_bits %d\n", i4_total_frame_bits);
760
761 if(!i4_is_it_a_skip && !i4_is_pic_handling_done)
762 {
763 /* Update the pic_handling struct */
764 irc_update_pic_handling(ps_rate_control_api->ps_pic_handling,
765 e_pic_type);
766 }
767
768 if(ps_rate_control_api->e_rc_type != CONST_QP)
769 {
770 if(!i4_is_it_a_skip)
771 {
772 WORD32 i4_new_period_flag;
773 /******************************************************************
774 Calculate the total values from the individual values
775 ******************************************************************/
776 for(i = 0; i < MAX_MB_TYPE; i++)
777 u4_frame_sad += pi4_mb_type_sad[i];
778 for(i = 0; i < MAX_MB_TYPE; i++)
779 i4_tot_texture_bits += pi4_mb_type_tex_bits[i];
780 for(i = 0; i < MAX_MB_TYPE; i++)
781 i4_avg_qp += pi4_tot_mb_type_qp[i];
782 for(i = 0; i < MAX_MB_TYPE; i++)
783 i4_tot_mbs += pi4_tot_mb_in_type[i];
784 i4_avg_qp /= i4_tot_mbs; /* Calculate the average QP */
785
786 if(ps_rate_control_api->u1_is_mb_level_rc_on)
787 {
788 /*
789 * The model needs to take into consideration the average
790 * activity of the entire frame while estimating the QP. Thus
791 * the frame sad values are scaled by the average activity
792 * before updating it into the model.
793 */
794 if(!i4_avg_activity)
795 i4_avg_activity = 1;
796 i4_intra_frm_cost *= i4_avg_activity;
797 u4_frame_sad *= i4_avg_activity;
798 }
799
800 /******************************************************************
801 Update the bit allocation module
802 NOTE: For bit allocation module, the pic_type should not be
803 modified to that of 'I', in case of a SCD.
804 ******************************************************************/
805 i4_new_period_flag = irc_is_last_frame_in_gop(
806 ps_rate_control_api->ps_pic_handling);
807 irc_ba_update_cur_frm_consumed_bits(
808 ps_rate_control_api->ps_bit_allocation,
809 ps_rate_control_api->ps_pic_handling,
810 i4_total_frame_bits, i4_model_updation_hdr_bits,
811 e_pic_type, u1_is_scd, i4_new_period_flag);
812
813 if(1 == i4_new_period_flag
814 && ((ps_rate_control_api->e_rc_type == VBR_STORAGE)
815 || (ps_rate_control_api->e_rc_type
816 == VBR_STORAGE_DVD_COMP)))
817 {
818 irc_ba_check_and_update_bit_allocation(
819 ps_rate_control_api->ps_bit_allocation,
820 ps_rate_control_api->ps_pic_handling,
821 irc_get_cur_vbv_buf_size(
822 ps_rate_control_api->ps_vbr_storage_vbv),
823 irc_get_max_vbv_buf_size(
824 ps_rate_control_api->ps_vbr_storage_vbv),
825 irc_get_max_bits_per_tgt_frm(
826 ps_rate_control_api->ps_vbr_storage_vbv),
827 i4_total_frame_bits);
828 }
829 }
830
831 /**********************************************************************
832 Update the buffer status
833 *********************************************************************/
834 /*
835 * This update is done after overflow and underflow handling to
836 * account for the actual bits dumped
837 */
838 if((ps_rate_control_api->e_rc_type == VBR_STORAGE)
839 || (ps_rate_control_api->e_rc_type
840 == VBR_STORAGE_DVD_COMP))
841 {
842 irc_update_vbr_vbv(ps_rate_control_api->ps_vbr_storage_vbv,
843 i4_total_frame_bits);
844 }
845 else if(ps_rate_control_api->e_rc_type == CBR_NLDRC)
846 {
847 irc_update_cbr_buffer(ps_rate_control_api->ps_cbr_buffer,
848 i4_total_frame_bits, e_pic_type);
849 }
850 else if(ps_rate_control_api->e_rc_type == VBR_STREAMING)
851 {
852 UWORD32 au4_num_pics_in_delay_prd[MAX_PIC_TYPE];
853
854 irc_get_vsp_num_pics_in_dly_prd(
855 &ps_rate_control_api->s_vbr_str_prms,
856 au4_num_pics_in_delay_prd);
857
858 irc_update_cbr_buffer(ps_rate_control_api->ps_cbr_buffer,
859 i4_total_frame_bits, e_pic_type);
860
861 irc_update_vbr_str_prms(&ps_rate_control_api->s_vbr_str_prms,
862 e_pic_type);
863
864 irc_change_cbr_vbv_num_pics_in_delay_period(
865 ps_rate_control_api->ps_cbr_buffer,
866 au4_num_pics_in_delay_prd);
867
868 /*
869 * If the change_in_peak_bitrate flag is set, after the delay period
870 * update the peak_bitrate and the buffer parameters
871 */
872 if(!ps_rate_control_api->u4_frms_in_delay_prd_for_peak_bit_rate_change)
873 {
874 irc_ba_change_ba_peak_bit_rate(
875 ps_rate_control_api->ps_bit_allocation,
876 (WORD32 *)&ps_rate_control_api->au4_new_peak_bit_rate[0]);
877 irc_change_cbr_vbv_bit_rate(
878 ps_rate_control_api->ps_cbr_buffer,
879 (WORD32 *)&ps_rate_control_api->au4_new_peak_bit_rate[0]);
880 }
881 if(ps_rate_control_api->u4_frms_in_delay_prd_for_peak_bit_rate_change)
882 ps_rate_control_api->u4_frms_in_delay_prd_for_peak_bit_rate_change--;
883 }
884
885 if(!i4_is_it_a_skip)
886 {
887 /*******************************************************************
888 Handle the SCENE CHANGE DETECTED
889 1) Make the picture type as I, so that updation happens as if it is
890 an I frame
891 2) Reset model, SAD and flag to restart the estimation process
892 ******************************************************************/
893 if(u1_is_scd)
894 {
895 WORD32 i4_frm_qp_after_scd;
896 UWORD32 u4_prev_I_frm_sad;
897
898 e_pic_type = I_PIC;
899
900 /* Scale scd qp based on SCD Frm sad and previous I Frm sad */
901 /* frm_qp_after_scd = (avg_qp * cur_frm_sad)/prev_I_frm_sad */
902
903 /*
904 * QP for the next frame should take care of
905 * 1) due to scene change, the current picture has consumed more
906 * bits
907 * 2) relative complexity of the previous scene and the current
908 * scene
909 */
910
911 /* Get the intra SAD for the previous scene */
912 u4_prev_I_frm_sad = irc_get_est_sad(
913 ps_rate_control_api->ps_est_sad, I_PIC);
914
915 /*
916 * Scale the QP based on the SAD ratio of the current pic and
917 * previous scene intra SAD
918 */
919 X_PROD_Y_DIV_Z(i4_avg_qp, u4_frame_sad, u4_prev_I_frm_sad,
920 i4_frm_qp_after_scd);
921
922 /* Limit the next frame qp by 50% across both the sides */
923 if(i4_frm_qp_after_scd > ((i4_avg_qp * 3) >> 1))
924 {
925 i4_frm_qp_after_scd = (i4_avg_qp * 3) >> 1;
926 }
927 else if(i4_frm_qp_after_scd < (i4_avg_qp >> 1))
928 {
929 i4_frm_qp_after_scd = (i4_avg_qp >> 1);
930 }
931
932 /*
933 * Ensure that the next frame QP is within the min_max limit of
934 * QP allowed
935 */
936 if(i4_frm_qp_after_scd
937 > ps_rate_control_api->au1_min_max_qp[(e_pic_type
938 << 1) + 1])
939 {
940 i4_frm_qp_after_scd =
941 ps_rate_control_api->au1_min_max_qp[(e_pic_type
942 << 1) + 1];
943 }
944 else if(i4_frm_qp_after_scd
945 < ps_rate_control_api->au1_min_max_qp[(e_pic_type
946 << 1)])
947 {
948 i4_frm_qp_after_scd =
949 ps_rate_control_api->au1_min_max_qp[(e_pic_type
950 << 1)];
951 }
952
953 /* Update the state var */
954 ps_rate_control_api->u1_frm_qp_after_scd =
955 (UWORD8)i4_frm_qp_after_scd;
956
957 /* re-set model */
958 for(i = 0; i < MAX_PIC_TYPE; i++)
959 {
960 irc_reset_frm_rc_rd_model(
961 ps_rate_control_api->aps_rd_model[i]);
962 }
963
964 /* Reset the SAD estimation module */
965 irc_reset_est_sad(ps_rate_control_api->ps_est_sad);
966
967 /* Reset flag */
968 for(i = 0; i < MAX_PIC_TYPE; i++)
969 {
970 ps_rate_control_api->au1_is_first_frm_coded[i] = 0;
971 }
972
973 /* Reset the MB Rate control */
974 irc_init_mb_level_rc(ps_rate_control_api->ps_mb_rate_control);
975
976 /*Set u1_scd_detected flag*/
977 ps_rate_control_api->u1_scd_detected = 1;
978
979 /*
980 * Adjust the average QP for the frame based on bits
981 * consumption
982 */
983 /*
984 * Initialize the QP for each picture type according to the
985 * average QP of the SCD pic
986 */
987 ps_rate_control_api->au1_prev_frm_qp[I_PIC] = (UWORD8)i4_avg_qp;
988
989 trace_printf((const WORD8*)"SCD DETECTED\n");
990 }
991 else
992 {
993 ps_rate_control_api->u1_scd_detected = 0;
994 /**************************************************************
995 Update the Qp used by the current frame
996 **************************************************************/
997 ps_rate_control_api->au1_prev_frm_qp[e_pic_type] =
998 (UWORD8)i4_avg_qp;
999 }
1000
1001 /********************************************************************
1002 Update the model of the correponding picture type
1003 NOTE: For SCD, we force the frame type from 'P' to that of a 'I'
1004 ******************************************************************/
1005 /*
1006 * For very simple sequences no bits are consumed by texture. These
1007 * frames do not add any information to the model and so not added
1008 */
1009 if(i4_tot_texture_bits && u4_frame_sad)
1010 {
1011 irc_add_frame_to_rd_model(
1012 ps_rate_control_api->aps_rd_model[e_pic_type],
1013 i4_tot_texture_bits, (UWORD8)i4_avg_qp,
1014 u4_frame_sad, u1_num_skips);
1015
1016 /*
1017 * At least one proper frame in added into the model. Until that
1018 * keep using the initial QP
1019 */
1020 ps_rate_control_api->au1_is_first_frm_coded[e_pic_type] = 1;
1021 }
1022
1023 if(i4_avg_activity)
1024 {
1025 /* Update the mb_level model */
1026 irc_mb_update_frame_level(
1027 ps_rate_control_api->ps_mb_rate_control,
1028 i4_avg_activity);
1029 }
1030
1031 /******************************************************************
1032 Update the sad estimation module
1033 NOTE: For SCD, we force the frame type from 'P' to that of a 'I'
1034 ******************************************************************/
1035 if(u4_frame_sad)
1036 {
1037 irc_update_actual_sad(ps_rate_control_api->ps_est_sad,
1038 u4_frame_sad, e_pic_type);
1039
1040 irc_update_actual_sad_for_intra(ps_rate_control_api->ps_est_sad,
1041 i4_intra_frm_cost);
1042 }
1043
1044 /*
1045 * Update the variable which denotes that a frame has been
1046 * encountered
1047 */
1048 ps_rate_control_api->u1_is_first_frm = 0;
1049
1050 }
1051 }
1052
1053 /* Store the prev encoded picture type for restricting Qp swing */
1054 if((e_pic_type == I_PIC) || (e_pic_type == P_PIC))
1055 {
1056 ps_rate_control_api->prev_ref_pic_type = e_pic_type;
1057 }
1058
1059 trace_printf((const WORD8*)"ft %d,hb %d,tb %d,qp %d,fs %d\n", e_pic_type,
1060 i4_model_updation_hdr_bits, i4_tot_texture_bits, i4_avg_qp,
1061 u4_frame_sad);
1062
1063 return;
1064 }
1065
1066 /*******************************************************************************
1067 MB Level API functions
1068 ******************************************************************************/
1069
1070 /******************************************************************************
1071 Function Name : irc_init_mb_rc_frame_level
1072 Description : Initialise the frame level details required for a mb level
1073 ******************************************************************************/
1074
irc_init_mb_rc_frame_level(rate_control_api_t * ps_rate_control_api,UWORD8 u1_frame_qp)1075 void irc_init_mb_rc_frame_level(rate_control_api_t *ps_rate_control_api,
1076 UWORD8 u1_frame_qp)
1077 {
1078 irc_mb_init_frame_level(ps_rate_control_api->ps_mb_rate_control,
1079 u1_frame_qp);
1080 }
1081
1082 /******************************************************************************
1083 Function Name : irc_get_mb_level_qp
1084 Description : Get the mb level qp
1085 *****************************************************************************/
irc_get_mb_level_qp(rate_control_api_t * ps_rate_control_api,WORD32 i4_cur_mb_activity,WORD32 * pi4_mb_qp,picture_type_e e_pic_type)1086 void irc_get_mb_level_qp(rate_control_api_t *ps_rate_control_api,
1087 WORD32 i4_cur_mb_activity,
1088 WORD32 *pi4_mb_qp,
1089 picture_type_e e_pic_type)
1090 {
1091 if(ps_rate_control_api->u1_is_mb_level_rc_on)
1092 {
1093 irc_get_mb_qp(ps_rate_control_api->ps_mb_rate_control,
1094 i4_cur_mb_activity, pi4_mb_qp);
1095
1096 /* Truncating the QP to the Max and Min Qp values possible */
1097 if(pi4_mb_qp[1] < ps_rate_control_api->au1_min_max_qp[e_pic_type << 1])
1098 {
1099 pi4_mb_qp[1] = ps_rate_control_api->au1_min_max_qp[e_pic_type << 1];
1100 }
1101 if(pi4_mb_qp[1]
1102 > ps_rate_control_api->au1_min_max_qp[(e_pic_type << 1)
1103 + 1])
1104 {
1105 pi4_mb_qp[1] = ps_rate_control_api->au1_min_max_qp[(e_pic_type << 1)
1106 + 1];
1107 }
1108 }
1109 else
1110 {
1111 WORD32 i4_qp;
1112 i4_qp = irc_get_frm_level_qp(ps_rate_control_api->ps_mb_rate_control);
1113 /* Both the qp are used for */
1114 pi4_mb_qp[0] = i4_qp; /* Used as feedback for the rate control */
1115 pi4_mb_qp[1] = i4_qp; /* Used for quantising the MB*/
1116 }
1117 }
1118
1119 /****************************************************************************
1120 Function Name : irc_get_bits_to_stuff
1121 Description : Gets the bits to stuff to prevent Underflow of Encoder Buffer
1122 *****************************************************************************/
irc_get_bits_to_stuff(rate_control_api_t * ps_rate_control_api,WORD32 i4_tot_consumed_bits,picture_type_e e_pic_type)1123 WORD32 irc_get_bits_to_stuff(rate_control_api_t *ps_rate_control_api,
1124 WORD32 i4_tot_consumed_bits,
1125 picture_type_e e_pic_type)
1126 {
1127 WORD32 i4_bits_to_stuff;
1128 /* Get the CBR bits to stuff*/
1129 i4_bits_to_stuff = irc_get_cbr_bits_to_stuff(
1130 ps_rate_control_api->ps_cbr_buffer, i4_tot_consumed_bits,
1131 e_pic_type);
1132 return i4_bits_to_stuff;
1133 }
1134
1135 /****************************************************************************
1136 Function Name : irc_get_prev_frm_est_bits
1137 Description : Returns previous frame estimated bits
1138 *****************************************************************************/
irc_get_prev_frm_est_bits(rate_control_api_t * ps_rate_control_api)1139 WORD32 irc_get_prev_frm_est_bits(rate_control_api_t *ps_rate_control_api)
1140 {
1141 return (ps_rate_control_api->i4_prev_frm_est_bits);
1142 }
1143
1144 /******************************************************************************
1145 Control Level API functions
1146 Logic: The control call sets the state structure of the rate control api
1147 accordingly such that the next process call would implement the same.
1148 ******************************************************************************/
1149
irc_change_inter_frm_int_call(rate_control_api_t * ps_rate_control_api,WORD32 i4_inter_frm_int)1150 void irc_change_inter_frm_int_call(rate_control_api_t *ps_rate_control_api,
1151 WORD32 i4_inter_frm_int)
1152 {
1153 irc_pic_handling_register_new_inter_frm_interval(
1154 ps_rate_control_api->ps_pic_handling, i4_inter_frm_int);
1155 }
1156
irc_change_intra_frm_int_call(rate_control_api_t * ps_rate_control_api,WORD32 i4_intra_frm_int)1157 void irc_change_intra_frm_int_call(rate_control_api_t *ps_rate_control_api,
1158 WORD32 i4_intra_frm_int)
1159 {
1160 irc_pic_handling_register_new_int_frm_interval(
1161 ps_rate_control_api->ps_pic_handling, i4_intra_frm_int);
1162
1163 if(ps_rate_control_api->e_rc_type == VBR_STREAMING)
1164 {
1165 irc_change_vsp_ifi(&ps_rate_control_api->s_vbr_str_prms,
1166 i4_intra_frm_int);
1167 }
1168 }
1169
1170 /****************************************************************************
1171 Function Name : irc_change_avg_bit_rate
1172 Description : Whenever the average bit rate changes, the excess bits is
1173 between the changed bit rate and the old one is re-distributed
1174 in the bit allocation module
1175 *****************************************************************************/
irc_change_avg_bit_rate(rate_control_api_t * ps_rate_control_api,UWORD32 u4_average_bit_rate)1176 void irc_change_avg_bit_rate(rate_control_api_t *ps_rate_control_api,
1177 UWORD32 u4_average_bit_rate)
1178 {
1179 int i;
1180 if(ps_rate_control_api->e_rc_type != CONST_QP)
1181 {
1182 /*
1183 * Bit Allocation Module: distribute the excess/deficit bits between the
1184 * old and the new frame rate to all the remaining frames
1185 */
1186 irc_ba_change_remaining_bits_in_period(
1187 ps_rate_control_api->ps_bit_allocation,
1188 ps_rate_control_api->ps_pic_handling,
1189 u4_average_bit_rate,
1190 irc_ba_get_frame_rate(
1191 ps_rate_control_api->ps_bit_allocation),
1192 (WORD32 *)(ps_rate_control_api->au4_new_peak_bit_rate));
1193 }
1194 if(ps_rate_control_api->e_rc_type == CBR_NLDRC)
1195 {
1196 UWORD32 u4_average_bit_rate_copy[MAX_NUM_DRAIN_RATES];
1197 for(i = 0; i < MAX_NUM_DRAIN_RATES; i++)
1198 {
1199 u4_average_bit_rate_copy[i] = u4_average_bit_rate;
1200 }
1201 irc_change_cbr_vbv_bit_rate(ps_rate_control_api->ps_cbr_buffer,
1202 (WORD32 *)(u4_average_bit_rate_copy));
1203 }
1204
1205 /*
1206 * This is done only for average bitrate changing somewhere after the model
1207 * stabilizes.Here it is assumed that user will not do this call after
1208 * first few frames. If we dont have this check, what would happen is since
1209 * the model has not stabilized, also bitrate has changed before the first
1210 * frame, we dont restrict the qp. Qp can go to very bad values after init
1211 * qp since if swing is disabled.
1212 * This check will become buggy if change bitrate is called say somewhere
1213 * after first two frames.Bottom line - RC init is done during create and
1214 * this call is done just before first process.And we want to differentiate
1215 * between this call done before first process and the call which is done
1216 * during run time
1217 */
1218 if(ps_rate_control_api->u1_is_first_frm == 0)
1219 {
1220 for(i = 0; i < MAX_PIC_TYPE; i++)
1221 {
1222 ps_rate_control_api->au1_avg_bitrate_changed[i] = 1;
1223 }
1224 }
1225 }
1226
1227 /****************************************************************************
1228 Function Name : irc_change_frame_rate
1229 Description : Does the necessary changes whenever there is a change in
1230 frame rate
1231 *****************************************************************************/
irc_change_frame_rate(rate_control_api_t * ps_rate_control_api,UWORD32 u4_frame_rate,UWORD32 u4_src_ticks,UWORD32 u4_tgt_ticks)1232 void irc_change_frame_rate(rate_control_api_t *ps_rate_control_api,
1233 UWORD32 u4_frame_rate,
1234 UWORD32 u4_src_ticks,
1235 UWORD32 u4_tgt_ticks)
1236 {
1237
1238 if(ps_rate_control_api->e_rc_type != CONST_QP)
1239 {
1240 UWORD32 u4_frms_in_delay_prd = ((u4_frame_rate
1241 * irc_get_cbr_buffer_delay(
1242 ps_rate_control_api->ps_cbr_buffer))
1243 / 1000000);
1244 if((ps_rate_control_api->e_rc_type == VBR_STORAGE)
1245 || (ps_rate_control_api->e_rc_type
1246 == VBR_STORAGE_DVD_COMP))
1247 {
1248 irc_change_vbr_vbv_frame_rate(
1249 ps_rate_control_api->ps_vbr_storage_vbv,
1250 u4_frame_rate);
1251 }
1252 else if(ps_rate_control_api->e_rc_type == CBR_NLDRC)
1253 {
1254 irc_change_cbr_vbv_tgt_frame_rate(
1255 ps_rate_control_api->ps_cbr_buffer, u4_frame_rate);
1256 }
1257 else if(ps_rate_control_api->e_rc_type == VBR_STREAMING)
1258 {
1259 UWORD32 au4_num_pics_in_delay_prd[MAX_PIC_TYPE];
1260 irc_change_vsp_tgt_ticks(&ps_rate_control_api->s_vbr_str_prms,
1261 u4_tgt_ticks);
1262 irc_change_vsp_src_ticks(&ps_rate_control_api->s_vbr_str_prms,
1263 u4_src_ticks);
1264 irc_change_vsp_fidp(&ps_rate_control_api->s_vbr_str_prms,
1265 u4_frms_in_delay_prd);
1266
1267 irc_get_vsp_num_pics_in_dly_prd(
1268 &ps_rate_control_api->s_vbr_str_prms,
1269 au4_num_pics_in_delay_prd);
1270 irc_change_cbr_vbv_tgt_frame_rate(
1271 ps_rate_control_api->ps_cbr_buffer, u4_frame_rate);
1272 irc_change_cbr_vbv_num_pics_in_delay_period(
1273 ps_rate_control_api->ps_cbr_buffer,
1274 au4_num_pics_in_delay_prd);
1275 }
1276
1277 /*
1278 * Bit Allocation Module: distribute the excess/deficit bits between the
1279 * old and the new frame rate to all the remaining frames
1280 */
1281 irc_ba_change_remaining_bits_in_period(
1282 ps_rate_control_api->ps_bit_allocation,
1283 ps_rate_control_api->ps_pic_handling,
1284 irc_ba_get_bit_rate(
1285 ps_rate_control_api->ps_bit_allocation),
1286 u4_frame_rate,
1287 (WORD32 *)(ps_rate_control_api->au4_new_peak_bit_rate));
1288 }
1289 }
1290
1291 /****************************************************************************
1292 Function Name : irc_change_frm_rate_for_bit_alloc
1293 Description : Does the necessary changes only in the bit_allocation module
1294 there is a change in frame rate
1295 *****************************************************************************/
irc_change_frm_rate_for_bit_alloc(rate_control_api_t * ps_rate_control_api,UWORD32 u4_frame_rate)1296 void irc_change_frm_rate_for_bit_alloc(rate_control_api_t *ps_rate_control_api,
1297 UWORD32 u4_frame_rate)
1298 {
1299
1300 if(ps_rate_control_api->e_rc_type != CONST_QP)
1301 {
1302 /*
1303 * Bit Allocation Module: distribute the excess/deficit bits between the
1304 * old and the new frame rate to all the remaining frames
1305 */
1306 irc_ba_change_remaining_bits_in_period(
1307 ps_rate_control_api->ps_bit_allocation,
1308 ps_rate_control_api->ps_pic_handling,
1309 irc_ba_get_bit_rate(
1310 ps_rate_control_api->ps_bit_allocation),
1311 u4_frame_rate,
1312 (WORD32 *)(ps_rate_control_api->au4_new_peak_bit_rate));
1313
1314 if(ps_rate_control_api->e_rc_type == VBR_STORAGE
1315 || ps_rate_control_api->e_rc_type
1316 == VBR_STORAGE_DVD_COMP)
1317 {
1318 irc_change_vbr_max_bits_per_tgt_frm(
1319 ps_rate_control_api->ps_vbr_storage_vbv,
1320 u4_frame_rate);
1321 }
1322 }
1323 }
1324
irc_change_init_qp(rate_control_api_t * ps_rate_control_api,UWORD8 * pu1_init_qp)1325 void irc_change_init_qp(rate_control_api_t *ps_rate_control_api,
1326 UWORD8 *pu1_init_qp)
1327 {
1328 WORD32 i;
1329 /* Initialize the init_qp */
1330 for(i = 0; i < MAX_PIC_TYPE; i++)
1331 {
1332 ps_rate_control_api->au1_init_qp[i] = pu1_init_qp[i];
1333 ps_rate_control_api->au1_prev_frm_qp[i] = pu1_init_qp[i];
1334 }
1335 }
1336
irc_change_min_max_qp(rate_control_api_t * ps_rate_control_api,UWORD8 * pu1_min_max_qp)1337 void irc_change_min_max_qp(rate_control_api_t *ps_rate_control_api,
1338 UWORD8 *pu1_min_max_qp)
1339 {
1340 WORD32 i;
1341 for(i = 0; i < MAX_PIC_TYPE; i++)
1342 {
1343 ps_rate_control_api->au1_min_max_qp[(i << 1)] =
1344 pu1_min_max_qp[(i << 1)];
1345 ps_rate_control_api->au1_min_max_qp[(i << 1) + 1] = pu1_min_max_qp[(i
1346 << 1) + 1];
1347 }
1348 }
1349
1350 /****************************************************************************
1351 Function Name : irc_change_peak_bit_rate
1352 Description : Does the necessary changes whenever there is a change in
1353 peak bit rate
1354 *****************************************************************************/
irc_change_peak_bit_rate(rate_control_api_t * ps_rate_control_api,UWORD32 * pu4_peak_bit_rate)1355 WORD32 irc_change_peak_bit_rate(rate_control_api_t *ps_rate_control_api,
1356 UWORD32 *pu4_peak_bit_rate)
1357 {
1358 WORD32 i4_ret_val = RC_OK;
1359 int i;
1360
1361 /*
1362 * Buffer Mechanism Module: Re-initialize the number of bits consumed per
1363 * frame
1364 */
1365 if(ps_rate_control_api->e_rc_type == VBR_STORAGE
1366 || ps_rate_control_api->e_rc_type == VBR_STORAGE_DVD_COMP)
1367 {
1368 /* Send the new peak bit rate and the old frame rate */
1369 irc_change_vbr_vbv_bit_rate(ps_rate_control_api->ps_vbr_storage_vbv,
1370 pu4_peak_bit_rate[0]);
1371 irc_ba_change_ba_peak_bit_rate(ps_rate_control_api->ps_bit_allocation,
1372 (WORD32 *)pu4_peak_bit_rate);
1373
1374 for(i = 0; i < MAX_NUM_DRAIN_RATES; i++)
1375 {
1376 ps_rate_control_api->au4_new_peak_bit_rate[i] =
1377 pu4_peak_bit_rate[i];
1378 }
1379 }
1380 else if(ps_rate_control_api->e_rc_type == VBR_STREAMING)
1381 {
1382 if(ps_rate_control_api->u4_frms_in_delay_prd_for_peak_bit_rate_change)
1383 {
1384 /*
1385 * Means that change in peak bit rate has been made twice before the
1386 * previous change could take effect
1387 */
1388 i4_ret_val = RC_BENIGN_ERR;
1389 }
1390 /*
1391 * If the change happens before encoding the first frame make the
1392 * effect immediately else delay the effect
1393 */
1394 if(ps_rate_control_api->u1_is_first_frm)
1395 {
1396 for(i = 0; i < MAX_NUM_DRAIN_RATES; i++)
1397 {
1398 ps_rate_control_api->au4_new_peak_bit_rate[i] =
1399 pu4_peak_bit_rate[i];
1400 }
1401 irc_ba_change_ba_peak_bit_rate(
1402 ps_rate_control_api->ps_bit_allocation,
1403 (WORD32 *)pu4_peak_bit_rate);
1404 irc_change_cbr_vbv_bit_rate(ps_rate_control_api->ps_cbr_buffer,
1405 (WORD32 *)pu4_peak_bit_rate);
1406 }
1407 else
1408 {
1409 UWORD32 au4_num_pics_in_delay_prd[MAX_NUM_DRAIN_RATES];
1410 /*
1411 * Else store the number of frames after which the effect should
1412 * happen and then update the peak bitrate
1413 */
1414 ps_rate_control_api->u4_frms_in_delay_prd_for_peak_bit_rate_change =
1415 irc_get_vsp_num_pics_in_dly_prd(
1416 &ps_rate_control_api->s_vbr_str_prms,
1417 au4_num_pics_in_delay_prd);
1418 for(i = 0; i < MAX_NUM_DRAIN_RATES; i++)
1419 {
1420 ps_rate_control_api->au4_new_peak_bit_rate[i] =
1421 pu4_peak_bit_rate[i];
1422 }
1423 }
1424 }
1425
1426 return (i4_ret_val);
1427 }
1428
irc_change_buffer_delay(rate_control_api_t * ps_rate_control_api,UWORD32 u4_buffer_delay)1429 void irc_change_buffer_delay(rate_control_api_t *ps_rate_control_api,
1430 UWORD32 u4_buffer_delay)
1431 {
1432 UWORD32 u4_frms_in_delay_prd = ((irc_ba_get_frame_rate(
1433 ps_rate_control_api->ps_bit_allocation) * u4_buffer_delay)
1434 / 1000000);
1435
1436 /* Initialize the rate control modules */
1437 if(ps_rate_control_api->e_rc_type == CBR_NLDRC)
1438 {
1439 irc_change_cbr_buffer_delay(ps_rate_control_api->ps_cbr_buffer,
1440 u4_buffer_delay);
1441 }
1442 else if(ps_rate_control_api->e_rc_type == VBR_STORAGE
1443 || ps_rate_control_api->e_rc_type == VBR_STORAGE_DVD_COMP)
1444 {
1445 UWORD32 au4_num_pics_in_delay_prd[MAX_PIC_TYPE];
1446
1447 irc_change_vsp_fidp(&ps_rate_control_api->s_vbr_str_prms,
1448 u4_frms_in_delay_prd);
1449
1450 /* Get the number of pics of each type in delay period */
1451 irc_get_vsp_num_pics_in_dly_prd(&ps_rate_control_api->s_vbr_str_prms,
1452 au4_num_pics_in_delay_prd);
1453
1454 irc_change_cbr_vbv_num_pics_in_delay_period(
1455 ps_rate_control_api->ps_cbr_buffer,
1456 au4_num_pics_in_delay_prd);
1457 }
1458 }
1459
1460 /* Getter functions to get the current rate control parameters */
irc_get_frame_rate(rate_control_api_t * ps_rate_control_api)1461 UWORD32 irc_get_frame_rate(rate_control_api_t *ps_rate_control_api)
1462 {
1463 return (irc_ba_get_frame_rate(ps_rate_control_api->ps_bit_allocation));
1464 }
1465
irc_get_bit_rate(rate_control_api_t * ps_rate_control_api)1466 UWORD32 irc_get_bit_rate(rate_control_api_t *ps_rate_control_api)
1467 {
1468 return (irc_ba_get_bit_rate(ps_rate_control_api->ps_bit_allocation));
1469 }
1470
irc_get_peak_bit_rate(rate_control_api_t * ps_rate_control_api,WORD32 i4_index)1471 UWORD32 irc_get_peak_bit_rate(rate_control_api_t *ps_rate_control_api,
1472 WORD32 i4_index)
1473 {
1474 return (ps_rate_control_api->au4_new_peak_bit_rate[i4_index]);
1475 }
1476
irc_get_intra_frame_interval(rate_control_api_t * ps_rate_control_api)1477 UWORD32 irc_get_intra_frame_interval(rate_control_api_t *ps_rate_control_api)
1478 {
1479 return (irc_pic_type_get_intra_frame_interval(
1480 ps_rate_control_api->ps_pic_handling));
1481 }
1482
irc_get_inter_frame_interval(rate_control_api_t * ps_rate_control_api)1483 UWORD32 irc_get_inter_frame_interval(rate_control_api_t *ps_rate_control_api)
1484 {
1485 return (irc_pic_type_get_inter_frame_interval(
1486 ps_rate_control_api->ps_pic_handling));
1487 }
1488
irc_get_rc_type(rate_control_api_t * ps_rate_control_api)1489 rc_type_e irc_get_rc_type(rate_control_api_t *ps_rate_control_api)
1490 {
1491 return (ps_rate_control_api->e_rc_type);
1492 }
1493
irc_get_bits_per_frame(rate_control_api_t * ps_rate_control_api)1494 WORD32 irc_get_bits_per_frame(rate_control_api_t *ps_rate_control_api)
1495 {
1496 WORD32 i4_bits_per_frm;
1497
1498 X_PROD_Y_DIV_Z(irc_ba_get_bit_rate(ps_rate_control_api->ps_bit_allocation),
1499 (UWORD32)1000,
1500 irc_ba_get_frame_rate(ps_rate_control_api->ps_bit_allocation),
1501 i4_bits_per_frm);
1502
1503 return (i4_bits_per_frm);
1504 }
1505
irc_get_max_delay(rate_control_api_t * ps_rate_control_api)1506 UWORD32 irc_get_max_delay(rate_control_api_t *ps_rate_control_api)
1507 {
1508 return (irc_get_cbr_buffer_delay(ps_rate_control_api->ps_cbr_buffer));
1509 }
1510
irc_get_seq_no(rate_control_api_t * ps_rate_control_api)1511 UWORD32 irc_get_seq_no(rate_control_api_t *ps_rate_control_api)
1512 {
1513 return (irc_pic_type_get_disp_order_no(ps_rate_control_api->ps_pic_handling));
1514 }
1515
irc_get_rem_frames_in_gop(rate_control_api_t * ps_rate_control_api)1516 UWORD32 irc_get_rem_frames_in_gop(rate_control_api_t *ps_rate_control_api)
1517 {
1518 WORD32 ai4_rem_frms_in_period[MAX_PIC_TYPE];
1519 WORD32 j;
1520 UWORD32 u4_rem_frms_in_period = 0;
1521
1522 /* Get the rem_frms_in_gop & the frms_in_gop from the pic_type state struct */
1523 irc_pic_type_get_rem_frms_in_gop(ps_rate_control_api->ps_pic_handling,
1524 ai4_rem_frms_in_period);
1525
1526 /* Depending on the number of gops in a period, find the num_frms_in_prd */
1527 for(j = 0; j < MAX_PIC_TYPE; j++)
1528 {
1529 u4_rem_frms_in_period += ai4_rem_frms_in_period[j];
1530 }
1531
1532 return (u4_rem_frms_in_period);
1533 }
1534
1535 /****************************************************************************
1536 Function Name : irc_flush_buf_frames
1537 Description : API call to flush the buffered up frames
1538 *****************************************************************************/
irc_flush_buf_frames(rate_control_api_t * ps_rate_control_api)1539 void irc_flush_buf_frames(rate_control_api_t *ps_rate_control_api)
1540 {
1541 irc_flush_frame_from_pic_stack(ps_rate_control_api->ps_pic_handling);
1542 }
1543
1544 /****************************************************************************
1545 Function Name : irc_flush_buf_frames
1546 Description : API call to flush the buffered up frames
1547 *****************************************************************************/
1548
irc_post_encode_frame_skip(rate_control_api_t * ps_rate_control_api,picture_type_e e_pic_type)1549 void irc_post_encode_frame_skip(rate_control_api_t *ps_rate_control_api,
1550 picture_type_e e_pic_type)
1551 {
1552 irc_skip_encoded_frame(ps_rate_control_api->ps_pic_handling, e_pic_type);
1553 }
1554
1555 /****************************************************************************
1556 Function Name : irc_force_I_frame
1557 Description : API call to force an I frame
1558 *****************************************************************************/
irc_force_I_frame(rate_control_api_t * ps_rate_control_api)1559 void irc_force_I_frame(rate_control_api_t *ps_rate_control_api)
1560 {
1561 irc_set_force_I_frame_flag(ps_rate_control_api->ps_pic_handling);
1562 }
1563
1564 /****************************************************************************
1565 * Function Name : rc_get_rem_bits_in_gop
1566 * Description : API call to get remaining bits in GOP
1567 * *****************************************************************************/
irc_get_rem_bits_in_period(rate_control_api_t * ps_rate_control_api)1568 WORD32 irc_get_rem_bits_in_period(rate_control_api_t *ps_rate_control_api)
1569 {
1570 return (irc_ba_get_rem_bits_in_period(
1571 ps_rate_control_api->ps_bit_allocation,
1572 ps_rate_control_api->ps_pic_handling));
1573 }
1574
1575 /****************************************************************************
1576 * Function Name : irc_get_vbv_buf_fullness
1577 * Description : API call to get VBV buffer fullness
1578 ******************************************************************************/
irc_get_vbv_buf_fullness(rate_control_api_t * ps_rate_control_api)1579 WORD32 irc_get_vbv_buf_fullness(rate_control_api_t *ps_rate_control_api)
1580 {
1581 return (irc_get_cur_vbv_buf_size(ps_rate_control_api->ps_vbr_storage_vbv));
1582 }
1583
irc_get_vbv_buf_size(rate_control_api_t * ps_rate_control_api)1584 WORD32 irc_get_vbv_buf_size(rate_control_api_t *ps_rate_control_api)
1585 {
1586 if(ps_rate_control_api->e_rc_type == CBR_NLDRC
1587 || ps_rate_control_api->e_rc_type == VBR_STREAMING)
1588 {
1589 return (irc_get_cbr_buffer_size(ps_rate_control_api->ps_cbr_buffer));
1590 }
1591 else
1592 {
1593 return (irc_get_max_vbv_buf_size(
1594 ps_rate_control_api->ps_vbr_storage_vbv));
1595 }
1596 }
1597
irc_get_vbv_fulness_with_cur_bits(rate_control_api_t * ps_rate_control_api,UWORD32 u4_bits)1598 WORD32 irc_get_vbv_fulness_with_cur_bits(rate_control_api_t *ps_rate_control_api,
1599 UWORD32 u4_bits)
1600 {
1601 return (irc_vbv_get_vbv_buf_fullness(
1602 ps_rate_control_api->ps_vbr_storage_vbv, u4_bits));
1603 }
1604
irc_set_avg_mb_act(rate_control_api_t * ps_rate_control_api,WORD32 i4_avg_activity)1605 void irc_set_avg_mb_act(rate_control_api_t *ps_rate_control_api,
1606 WORD32 i4_avg_activity)
1607 {
1608 irc_mb_update_frame_level(ps_rate_control_api->ps_mb_rate_control,
1609 i4_avg_activity);
1610 return;
1611 }
1612