1 //===-- LiveIntervalUnion.cpp - Live interval union data structure --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // LiveIntervalUnion represents a coalesced set of live intervals. This may be
11 // used during coalescing to represent a congruence class, or during register
12 // allocation to model liveness of a physical register.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "llvm/CodeGen/LiveIntervalUnion.h"
17 #include "llvm/ADT/SparseBitVector.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/raw_ostream.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include <algorithm>
22 
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "regalloc"
26 
27 
28 // Merge a LiveInterval's segments. Guarantee no overlaps.
unify(LiveInterval & VirtReg,const LiveRange & Range)29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) {
30   if (Range.empty())
31     return;
32   ++Tag;
33 
34   // Insert each of the virtual register's live segments into the map.
35   LiveRange::const_iterator RegPos = Range.begin();
36   LiveRange::const_iterator RegEnd = Range.end();
37   SegmentIter SegPos = Segments.find(RegPos->start);
38 
39   while (SegPos.valid()) {
40     SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
41     if (++RegPos == RegEnd)
42       return;
43     SegPos.advanceTo(RegPos->start);
44   }
45 
46   // We have reached the end of Segments, so it is no longer necessary to search
47   // for the insertion position.
48   // It is faster to insert the end first.
49   --RegEnd;
50   SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
51   for (; RegPos != RegEnd; ++RegPos, ++SegPos)
52     SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
53 }
54 
55 // Remove a live virtual register's segments from this union.
extract(LiveInterval & VirtReg,const LiveRange & Range)56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) {
57   if (Range.empty())
58     return;
59   ++Tag;
60 
61   // Remove each of the virtual register's live segments from the map.
62   LiveRange::const_iterator RegPos = Range.begin();
63   LiveRange::const_iterator RegEnd = Range.end();
64   SegmentIter SegPos = Segments.find(RegPos->start);
65 
66   for (;;) {
67     assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval");
68     SegPos.erase();
69     if (!SegPos.valid())
70       return;
71 
72     // Skip all segments that may have been coalesced.
73     RegPos = Range.advanceTo(RegPos, SegPos.start());
74     if (RegPos == RegEnd)
75       return;
76 
77     SegPos.advanceTo(RegPos->start);
78   }
79 }
80 
81 void
print(raw_ostream & OS,const TargetRegisterInfo * TRI) const82 LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
83   if (empty()) {
84     OS << " empty\n";
85     return;
86   }
87   for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
88     OS << " [" << SI.start() << ' ' << SI.stop() << "):"
89        << PrintReg(SI.value()->reg, TRI);
90   }
91   OS << '\n';
92 }
93 
94 #ifndef NDEBUG
95 // Verify the live intervals in this union and add them to the visited set.
verify(LiveVirtRegBitSet & VisitedVRegs)96 void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) {
97   for (SegmentIter SI = Segments.begin(); SI.valid(); ++SI)
98     VisitedVRegs.set(SI.value()->reg);
99 }
100 #endif //!NDEBUG
101 
102 // Scan the vector of interfering virtual registers in this union. Assume it's
103 // quite small.
isSeenInterference(LiveInterval * VirtReg) const104 bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const {
105   SmallVectorImpl<LiveInterval*>::const_iterator I =
106     std::find(InterferingVRegs.begin(), InterferingVRegs.end(), VirtReg);
107   return I != InterferingVRegs.end();
108 }
109 
110 // Collect virtual registers in this union that interfere with this
111 // query's live virtual register.
112 //
113 // The query state is one of:
114 //
115 // 1. CheckedFirstInterference == false: Iterators are uninitialized.
116 // 2. SeenAllInterferences == true: InterferingVRegs complete, iterators unused.
117 // 3. Iterators left at the last seen intersection.
118 //
119 unsigned LiveIntervalUnion::Query::
collectInterferingVRegs(unsigned MaxInterferingRegs)120 collectInterferingVRegs(unsigned MaxInterferingRegs) {
121   // Fast path return if we already have the desired information.
122   if (SeenAllInterferences || InterferingVRegs.size() >= MaxInterferingRegs)
123     return InterferingVRegs.size();
124 
125   // Set up iterators on the first call.
126   if (!CheckedFirstInterference) {
127     CheckedFirstInterference = true;
128 
129     // Quickly skip interference check for empty sets.
130     if (VirtReg->empty() || LiveUnion->empty()) {
131       SeenAllInterferences = true;
132       return 0;
133     }
134 
135     // In most cases, the union will start before VirtReg.
136     VirtRegI = VirtReg->begin();
137     LiveUnionI.setMap(LiveUnion->getMap());
138     LiveUnionI.find(VirtRegI->start);
139   }
140 
141   LiveInterval::iterator VirtRegEnd = VirtReg->end();
142   LiveInterval *RecentReg = nullptr;
143   while (LiveUnionI.valid()) {
144     assert(VirtRegI != VirtRegEnd && "Reached end of VirtReg");
145 
146     // Check for overlapping interference.
147     while (VirtRegI->start < LiveUnionI.stop() &&
148            VirtRegI->end > LiveUnionI.start()) {
149       // This is an overlap, record the interfering register.
150       LiveInterval *VReg = LiveUnionI.value();
151       if (VReg != RecentReg && !isSeenInterference(VReg)) {
152         RecentReg = VReg;
153         InterferingVRegs.push_back(VReg);
154         if (InterferingVRegs.size() >= MaxInterferingRegs)
155           return InterferingVRegs.size();
156       }
157       // This LiveUnion segment is no longer interesting.
158       if (!(++LiveUnionI).valid()) {
159         SeenAllInterferences = true;
160         return InterferingVRegs.size();
161       }
162     }
163 
164     // The iterators are now not overlapping, LiveUnionI has been advanced
165     // beyond VirtRegI.
166     assert(VirtRegI->end <= LiveUnionI.start() && "Expected non-overlap");
167 
168     // Advance the iterator that ends first.
169     VirtRegI = VirtReg->advanceTo(VirtRegI, LiveUnionI.start());
170     if (VirtRegI == VirtRegEnd)
171       break;
172 
173     // Detect overlap, handle above.
174     if (VirtRegI->start < LiveUnionI.stop())
175       continue;
176 
177     // Still not overlapping. Catch up LiveUnionI.
178     LiveUnionI.advanceTo(VirtRegI->start);
179   }
180   SeenAllInterferences = true;
181   return InterferingVRegs.size();
182 }
183 
init(LiveIntervalUnion::Allocator & Alloc,unsigned NSize)184 void LiveIntervalUnion::Array::init(LiveIntervalUnion::Allocator &Alloc,
185                                     unsigned NSize) {
186   // Reuse existing allocation.
187   if (NSize == Size)
188     return;
189   clear();
190   Size = NSize;
191   LIUs = static_cast<LiveIntervalUnion*>(
192     malloc(sizeof(LiveIntervalUnion)*NSize));
193   for (unsigned i = 0; i != Size; ++i)
194     new(LIUs + i) LiveIntervalUnion(Alloc);
195 }
196 
clear()197 void LiveIntervalUnion::Array::clear() {
198   if (!LIUs)
199     return;
200   for (unsigned i = 0; i != Size; ++i)
201     LIUs[i].~LiveIntervalUnion();
202   free(LIUs);
203   Size =  0;
204   LIUs = nullptr;
205 }
206