1//===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Thumb specific DAG Nodes. 16// 17 18def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall, 19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 20 SDNPVariadic]>; 21 22def imm_sr_XFORM: SDNodeXForm<imm, [{ 23 unsigned Imm = N->getZExtValue(); 24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), SDLoc(N), MVT::i32); 25}]>; 26def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; } 27def imm_sr : Operand<i32>, PatLeaf<(imm), [{ 28 uint64_t Imm = N->getZExtValue(); 29 return Imm > 0 && Imm <= 32; 30}], imm_sr_XFORM> { 31 let PrintMethod = "printThumbSRImm"; 32 let ParserMatchClass = ThumbSRImmAsmOperand; 33} 34 35def imm_comp_XFORM : SDNodeXForm<imm, [{ 36 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N), 37 MVT::i32); 38}]>; 39 40def imm0_7_neg : PatLeaf<(i32 imm), [{ 41 return (uint32_t)-N->getZExtValue() < 8; 42}], imm_neg_XFORM>; 43 44def imm0_255_comp : PatLeaf<(i32 imm), [{ 45 return ~((uint32_t)N->getZExtValue()) < 256; 46}]>; 47 48def imm8_255 : ImmLeaf<i32, [{ 49 return Imm >= 8 && Imm < 256; 50}]>; 51def imm8_255_neg : PatLeaf<(i32 imm), [{ 52 unsigned Val = -N->getZExtValue(); 53 return Val >= 8 && Val < 256; 54}], imm_neg_XFORM>; 55 56// Break imm's up into two pieces: an immediate + a left shift. This uses 57// thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt 58// to get the val/shift pieces. 59def thumb_immshifted : PatLeaf<(imm), [{ 60 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue()); 61}]>; 62 63def thumb_immshifted_val : SDNodeXForm<imm, [{ 64 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); 65 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32); 66}]>; 67 68def thumb_immshifted_shamt : SDNodeXForm<imm, [{ 69 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); 70 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32); 71}]>; 72 73// Scaled 4 immediate. 74def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; } 75def t_imm0_1020s4 : Operand<i32> { 76 let PrintMethod = "printThumbS4ImmOperand"; 77 let ParserMatchClass = t_imm0_1020s4_asmoperand; 78 let OperandType = "OPERAND_IMMEDIATE"; 79} 80 81def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; } 82def t_imm0_508s4 : Operand<i32> { 83 let PrintMethod = "printThumbS4ImmOperand"; 84 let ParserMatchClass = t_imm0_508s4_asmoperand; 85 let OperandType = "OPERAND_IMMEDIATE"; 86} 87// Alias use only, so no printer is necessary. 88def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; } 89def t_imm0_508s4_neg : Operand<i32> { 90 let ParserMatchClass = t_imm0_508s4_neg_asmoperand; 91 let OperandType = "OPERAND_IMMEDIATE"; 92} 93 94// Define Thumb specific addressing modes. 95 96// unsigned 8-bit, 2-scaled memory offset 97class OperandUnsignedOffset_b8s2 : AsmOperandClass { 98 let Name = "UnsignedOffset_b8s2"; 99 let PredicateMethod = "isUnsignedOffset<8, 2>"; 100} 101 102def UnsignedOffset_b8s2 : OperandUnsignedOffset_b8s2; 103 104// thumb style PC relative operand. signed, 8 bits magnitude, 105// two bits shift. can be represented as either [pc, #imm], #imm, 106// or relocatable expression... 107def ThumbMemPC : AsmOperandClass { 108 let Name = "ThumbMemPC"; 109} 110 111let OperandType = "OPERAND_PCREL" in { 112def t_brtarget : Operand<OtherVT> { 113 let EncoderMethod = "getThumbBRTargetOpValue"; 114 let DecoderMethod = "DecodeThumbBROperand"; 115} 116 117// ADR instruction labels. 118def t_adrlabel : Operand<i32> { 119 let EncoderMethod = "getThumbAdrLabelOpValue"; 120 let PrintMethod = "printAdrLabelOperand<2>"; 121 let ParserMatchClass = UnsignedOffset_b8s2; 122} 123 124def t_bcctarget : Operand<i32> { 125 let EncoderMethod = "getThumbBCCTargetOpValue"; 126 let DecoderMethod = "DecodeThumbBCCTargetOperand"; 127} 128 129def t_cbtarget : Operand<i32> { 130 let EncoderMethod = "getThumbCBTargetOpValue"; 131 let DecoderMethod = "DecodeThumbCmpBROperand"; 132} 133 134def t_bltarget : Operand<i32> { 135 let EncoderMethod = "getThumbBLTargetOpValue"; 136 let DecoderMethod = "DecodeThumbBLTargetOperand"; 137} 138 139def t_blxtarget : Operand<i32> { 140 let EncoderMethod = "getThumbBLXTargetOpValue"; 141 let DecoderMethod = "DecodeThumbBLXOffset"; 142} 143 144// t_addrmode_pc := <label> => pc + imm8 * 4 145// 146def t_addrmode_pc : MemOperand { 147 let EncoderMethod = "getAddrModePCOpValue"; 148 let DecoderMethod = "DecodeThumbAddrModePC"; 149 let PrintMethod = "printThumbLdrLabelOperand"; 150 let ParserMatchClass = ThumbMemPC; 151} 152} 153 154// t_addrmode_rr := reg + reg 155// 156def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; } 157def t_addrmode_rr : MemOperand, 158 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> { 159 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 160 let PrintMethod = "printThumbAddrModeRROperand"; 161 let DecoderMethod = "DecodeThumbAddrModeRR"; 162 let ParserMatchClass = t_addrmode_rr_asm_operand; 163 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 164} 165 166// t_addrmode_rrs := reg + reg 167// 168// We use separate scaled versions because the Select* functions need 169// to explicitly check for a matching constant and return false here so that 170// the reg+imm forms will match instead. This is a horrible way to do that, 171// as it forces tight coupling between the methods, but it's how selectiondag 172// currently works. 173def t_addrmode_rrs1 : MemOperand, 174 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> { 175 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 176 let PrintMethod = "printThumbAddrModeRROperand"; 177 let DecoderMethod = "DecodeThumbAddrModeRR"; 178 let ParserMatchClass = t_addrmode_rr_asm_operand; 179 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 180} 181def t_addrmode_rrs2 : MemOperand, 182 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> { 183 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 184 let DecoderMethod = "DecodeThumbAddrModeRR"; 185 let PrintMethod = "printThumbAddrModeRROperand"; 186 let ParserMatchClass = t_addrmode_rr_asm_operand; 187 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 188} 189def t_addrmode_rrs4 : MemOperand, 190 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> { 191 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 192 let DecoderMethod = "DecodeThumbAddrModeRR"; 193 let PrintMethod = "printThumbAddrModeRROperand"; 194 let ParserMatchClass = t_addrmode_rr_asm_operand; 195 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 196} 197 198// t_addrmode_is4 := reg + imm5 * 4 199// 200def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; } 201def t_addrmode_is4 : MemOperand, 202 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> { 203 let EncoderMethod = "getAddrModeISOpValue"; 204 let DecoderMethod = "DecodeThumbAddrModeIS"; 205 let PrintMethod = "printThumbAddrModeImm5S4Operand"; 206 let ParserMatchClass = t_addrmode_is4_asm_operand; 207 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 208} 209 210// t_addrmode_is2 := reg + imm5 * 2 211// 212def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; } 213def t_addrmode_is2 : MemOperand, 214 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> { 215 let EncoderMethod = "getAddrModeISOpValue"; 216 let DecoderMethod = "DecodeThumbAddrModeIS"; 217 let PrintMethod = "printThumbAddrModeImm5S2Operand"; 218 let ParserMatchClass = t_addrmode_is2_asm_operand; 219 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 220} 221 222// t_addrmode_is1 := reg + imm5 223// 224def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; } 225def t_addrmode_is1 : MemOperand, 226 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> { 227 let EncoderMethod = "getAddrModeISOpValue"; 228 let DecoderMethod = "DecodeThumbAddrModeIS"; 229 let PrintMethod = "printThumbAddrModeImm5S1Operand"; 230 let ParserMatchClass = t_addrmode_is1_asm_operand; 231 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 232} 233 234// t_addrmode_sp := sp + imm8 * 4 235// 236// FIXME: This really shouldn't have an explicit SP operand at all. It should 237// be implicit, just like in the instruction encoding itself. 238def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; } 239def t_addrmode_sp : MemOperand, 240 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { 241 let EncoderMethod = "getAddrModeThumbSPOpValue"; 242 let DecoderMethod = "DecodeThumbAddrModeSP"; 243 let PrintMethod = "printThumbAddrModeSPOperand"; 244 let ParserMatchClass = t_addrmode_sp_asm_operand; 245 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 246} 247 248//===----------------------------------------------------------------------===// 249// Miscellaneous Instructions. 250// 251 252// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 253// from removing one half of the matched pairs. That breaks PEI, which assumes 254// these will always be in pairs, and asserts if it finds otherwise. Better way? 255let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 256def tADJCALLSTACKUP : 257 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, 258 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, 259 Requires<[IsThumb, IsThumb1Only]>; 260 261def tADJCALLSTACKDOWN : 262 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, 263 [(ARMcallseq_start imm:$amt)]>, 264 Requires<[IsThumb, IsThumb1Only]>; 265} 266 267class T1SystemEncoding<bits<8> opc> 268 : T1Encoding<0b101111> { 269 let Inst{9-8} = 0b11; 270 let Inst{7-0} = opc; 271} 272 273def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm", 274 [(int_arm_hint imm0_15:$imm)]>, 275 T1SystemEncoding<0x00>, 276 Requires<[IsThumb, HasV6M]> { 277 bits<4> imm; 278 let Inst{7-4} = imm; 279} 280 281class tHintAlias<string Asm, dag Result> : tInstAlias<Asm, Result> { 282 let Predicates = [IsThumb, HasV6M]; 283} 284 285def : tHintAlias<"nop$p", (tHINT 0, pred:$p)>; // A8.6.110 286def : tHintAlias<"yield$p", (tHINT 1, pred:$p)>; // A8.6.410 287def : tHintAlias<"wfe$p", (tHINT 2, pred:$p)>; // A8.6.408 288def : tHintAlias<"wfi$p", (tHINT 3, pred:$p)>; // A8.6.409 289def : tHintAlias<"sev$p", (tHINT 4, pred:$p)>; // A8.6.157 290def : tInstAlias<"sevl$p", (tHINT 5, pred:$p)> { 291 let Predicates = [IsThumb2, HasV8]; 292} 293 294// The imm operand $val can be used by a debugger to store more information 295// about the breakpoint. 296def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val", 297 []>, 298 T1Encoding<0b101111> { 299 let Inst{9-8} = 0b10; 300 // A8.6.22 301 bits<8> val; 302 let Inst{7-0} = val; 303} 304// default immediate for breakpoint mnemonic 305def : InstAlias<"bkpt", (tBKPT 0)>, Requires<[IsThumb]>; 306 307def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val", 308 []>, T1Encoding<0b101110>, Requires<[IsThumb, HasV8]> { 309 let Inst{9-6} = 0b1010; 310 bits<6> val; 311 let Inst{5-0} = val; 312} 313 314def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end", 315 []>, T1Encoding<0b101101>, Requires<[IsNotMClass]>, Deprecated<HasV8Ops> { 316 bits<1> end; 317 // A8.6.156 318 let Inst{9-5} = 0b10010; 319 let Inst{4} = 1; 320 let Inst{3} = end; 321 let Inst{2-0} = 0b000; 322} 323 324// Change Processor State is a system instruction -- for disassembly only. 325def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags), 326 NoItinerary, "cps$imod $iflags", []>, 327 T1Misc<0b0110011> { 328 // A8.6.38 & B6.1.1 329 bit imod; 330 bits<3> iflags; 331 332 let Inst{4} = imod; 333 let Inst{3} = 0; 334 let Inst{2-0} = iflags; 335 let DecoderMethod = "DecodeThumbCPS"; 336} 337 338// For both thumb1 and thumb2. 339let isNotDuplicable = 1, isCodeGenOnly = 1 in 340def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "", 341 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>, 342 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 343 // A8.6.6 344 bits<3> dst; 345 let Inst{6-3} = 0b1111; // Rm = pc 346 let Inst{2-0} = dst; 347} 348 349// ADD <Rd>, sp, #<imm8> 350// FIXME: This should not be marked as having side effects, and it should be 351// rematerializable. Clearing the side effect bit causes miscompilations, 352// probably because the instruction can be moved around. 353def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm), 354 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>, 355 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> { 356 // A6.2 & A8.6.8 357 bits<3> dst; 358 bits<8> imm; 359 let Inst{10-8} = dst; 360 let Inst{7-0} = imm; 361 let DecoderMethod = "DecodeThumbAddSpecialReg"; 362} 363 364// Thumb1 frame lowering is rather fragile, we hope to be able to use 365// tADDrSPi, but we may need to insert a sequence that clobbers CPSR. 366def tADDframe : PseudoInst<(outs tGPR:$dst), (ins i32imm:$base, i32imm:$offset), 367 NoItinerary, []>, 368 Requires<[IsThumb, IsThumb1Only]> { 369 let Defs = [CPSR]; 370} 371 372// ADD sp, sp, #<imm7> 373def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 374 IIC_iALUi, "add", "\t$Rdn, $imm", []>, 375 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> { 376 // A6.2.5 & A8.6.8 377 bits<7> imm; 378 let Inst{6-0} = imm; 379 let DecoderMethod = "DecodeThumbAddSPImm"; 380} 381 382// SUB sp, sp, #<imm7> 383// FIXME: The encoding and the ASM string don't match up. 384def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 385 IIC_iALUi, "sub", "\t$Rdn, $imm", []>, 386 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> { 387 // A6.2.5 & A8.6.214 388 bits<7> imm; 389 let Inst{6-0} = imm; 390 let DecoderMethod = "DecodeThumbAddSPImm"; 391} 392 393def : tInstAlias<"add${p} sp, $imm", 394 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 395def : tInstAlias<"add${p} sp, sp, $imm", 396 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 397 398// Can optionally specify SP as a three operand instruction. 399def : tInstAlias<"add${p} sp, sp, $imm", 400 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>; 401def : tInstAlias<"sub${p} sp, sp, $imm", 402 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>; 403 404// ADD <Rm>, sp 405def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr, 406 "add", "\t$Rdn, $sp, $Rn", []>, 407 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 408 // A8.6.9 Encoding T1 409 bits<4> Rdn; 410 let Inst{7} = Rdn{3}; 411 let Inst{6-3} = 0b1101; 412 let Inst{2-0} = Rdn{2-0}; 413 let DecoderMethod = "DecodeThumbAddSPReg"; 414} 415 416// ADD sp, <Rm> 417def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr, 418 "add", "\t$Rdn, $Rm", []>, 419 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 420 // A8.6.9 Encoding T2 421 bits<4> Rm; 422 let Inst{7} = 1; 423 let Inst{6-3} = Rm; 424 let Inst{2-0} = 0b101; 425 let DecoderMethod = "DecodeThumbAddSPReg"; 426} 427 428//===----------------------------------------------------------------------===// 429// Control Flow Instructions. 430// 431 432// Indirect branches 433let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 434 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>, 435 T1Special<{1,1,0,?}>, Sched<[WriteBr]> { 436 // A6.2.3 & A8.6.25 437 bits<4> Rm; 438 let Inst{6-3} = Rm; 439 let Inst{2-0} = 0b000; 440 let Unpredictable{2-0} = 0b111; 441 } 442} 443 444let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 445 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br, 446 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>; 447 448 // Alternative return instruction used by vararg functions. 449 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p), 450 2, IIC_Br, [], 451 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>; 452} 453 454// All calls clobber the non-callee saved registers. SP is marked as a use to 455// prevent stack-pointer assignments that appear immediately before calls from 456// potentially appearing dead. 457let isCall = 1, 458 Defs = [LR], Uses = [SP] in { 459 // Also used for Thumb2 460 def tBL : TIx2<0b11110, 0b11, 1, 461 (outs), (ins pred:$p, t_bltarget:$func), IIC_Br, 462 "bl${p}\t$func", 463 [(ARMtcall tglobaladdr:$func)]>, 464 Requires<[IsThumb]>, Sched<[WriteBrL]> { 465 bits<24> func; 466 let Inst{26} = func{23}; 467 let Inst{25-16} = func{20-11}; 468 let Inst{13} = func{22}; 469 let Inst{11} = func{21}; 470 let Inst{10-0} = func{10-0}; 471 } 472 473 // ARMv5T and above, also used for Thumb2 474 def tBLXi : TIx2<0b11110, 0b11, 0, 475 (outs), (ins pred:$p, t_blxtarget:$func), IIC_Br, 476 "blx${p}\t$func", 477 [(ARMcall tglobaladdr:$func)]>, 478 Requires<[IsThumb, HasV5T, IsNotMClass]>, Sched<[WriteBrL]> { 479 bits<24> func; 480 let Inst{26} = func{23}; 481 let Inst{25-16} = func{20-11}; 482 let Inst{13} = func{22}; 483 let Inst{11} = func{21}; 484 let Inst{10-1} = func{10-1}; 485 let Inst{0} = 0; // func{0} is assumed zero 486 } 487 488 // Also used for Thumb2 489 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br, 490 "blx${p}\t$func", 491 [(ARMtcall GPR:$func)]>, 492 Requires<[IsThumb, HasV5T]>, 493 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24; 494 bits<4> func; 495 let Inst{6-3} = func; 496 let Inst{2-0} = 0b000; 497 } 498 499 // ARMv4T 500 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func), 501 4, IIC_Br, 502 [(ARMcall_nolink tGPR:$func)]>, 503 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>; 504} 505 506let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 507 let isPredicable = 1 in 508 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br, 509 "b", "\t$target", [(br bb:$target)]>, 510 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> { 511 bits<11> target; 512 let Inst{10-0} = target; 513 let AsmMatchConverter = "cvtThumbBranches"; 514 } 515 516 // Far jump 517 // Just a pseudo for a tBL instruction. Needed to let regalloc know about 518 // the clobber of LR. 519 let Defs = [LR] in 520 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p), 521 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>, 522 Sched<[WriteBrTbl]>; 523 524 def tBR_JTr : tPseudoInst<(outs), 525 (ins tGPR:$target, i32imm:$jt), 526 0, IIC_Br, 527 [(ARMbrjt tGPR:$target, tjumptable:$jt)]>, 528 Sched<[WriteBrTbl]> { 529 let Size = 2; 530 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 531 } 532} 533 534// FIXME: should be able to write a pattern for ARMBrcond, but can't use 535// a two-value operand where a dag node expects two operands. :( 536let isBranch = 1, isTerminator = 1 in 537 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br, 538 "b${p}\t$target", 539 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, 540 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> { 541 bits<4> p; 542 bits<8> target; 543 let Inst{11-8} = p; 544 let Inst{7-0} = target; 545 let AsmMatchConverter = "cvtThumbBranches"; 546} 547 548 549// Tail calls 550let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 551 // IOS versions. 552 let Uses = [SP] in { 553 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst), 554 4, IIC_Br, [], 555 (tBX GPR:$dst, (ops 14, zero_reg))>, 556 Requires<[IsThumb]>, Sched<[WriteBr]>; 557 } 558 // tTAILJMPd: MachO version uses a Thumb2 branch (no Thumb1 tail calls 559 // on MachO), so it's in ARMInstrThumb2.td. 560 // Non-MachO version: 561 let Uses = [SP] in { 562 def tTAILJMPdND : tPseudoExpand<(outs), 563 (ins t_brtarget:$dst, pred:$p), 564 4, IIC_Br, [], 565 (tB t_brtarget:$dst, pred:$p)>, 566 Requires<[IsThumb, IsNotMachO]>, Sched<[WriteBr]>; 567 } 568} 569 570 571// A8.6.218 Supervisor Call (Software Interrupt) 572// A8.6.16 B: Encoding T1 573// If Inst{11-8} == 0b1111 then SEE SVC 574let isCall = 1, Uses = [SP] in 575def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br, 576 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> { 577 bits<8> imm; 578 let Inst{15-12} = 0b1101; 579 let Inst{11-8} = 0b1111; 580 let Inst{7-0} = imm; 581} 582 583// The assembler uses 0xDEFE for a trap instruction. 584let isBarrier = 1, isTerminator = 1 in 585def tTRAP : TI<(outs), (ins), IIC_Br, 586 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> { 587 let Inst = 0xdefe; 588} 589 590//===----------------------------------------------------------------------===// 591// Load Store Instructions. 592// 593 594// PC-relative loads need to be matched first as constant pool accesses need to 595// always be PC-relative. We do this using AddedComplexity, as the pattern is 596// simpler than the patterns of the other load instructions. 597let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 10 in 598def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 599 "ldr", "\t$Rt, $addr", 600 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>, 601 T1Encoding<{0,1,0,0,1,?}> { 602 // A6.2 & A8.6.59 603 bits<3> Rt; 604 bits<8> addr; 605 let Inst{10-8} = Rt; 606 let Inst{7-0} = addr; 607} 608 609// SP-relative loads should be matched before standard immediate-offset loads as 610// it means we avoid having to move SP to another register. 611let canFoldAsLoad = 1 in 612def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i, 613 "ldr", "\t$Rt, $addr", 614 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>, 615 T1LdStSP<{1,?,?}> { 616 bits<3> Rt; 617 bits<8> addr; 618 let Inst{10-8} = Rt; 619 let Inst{7-0} = addr; 620} 621 622// Loads: reg/reg and reg/imm5 623let canFoldAsLoad = 1, isReMaterializable = 1 in 624multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 625 Operand AddrMode_r, Operand AddrMode_i, 626 AddrMode am, InstrItinClass itin_r, 627 InstrItinClass itin_i, string asm, 628 PatFrag opnode> { 629 // Immediate-offset loads should be matched before register-offset loads as 630 // when the offset is a constant it's simpler to first check if it fits in the 631 // immediate offset field then fall back to register-offset if it doesn't. 632 def i : // reg/imm5 633 T1pILdStEncodeImm<imm_opc, 1 /* Load */, 634 (outs tGPR:$Rt), (ins AddrMode_i:$addr), 635 am, itin_i, asm, "\t$Rt, $addr", 636 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>; 637 // Register-offset loads are matched last. 638 def r : // reg/reg 639 T1pILdStEncode<reg_opc, 640 (outs tGPR:$Rt), (ins AddrMode_r:$addr), 641 am, itin_r, asm, "\t$Rt, $addr", 642 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>; 643} 644// Stores: reg/reg and reg/imm5 645multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 646 Operand AddrMode_r, Operand AddrMode_i, 647 AddrMode am, InstrItinClass itin_r, 648 InstrItinClass itin_i, string asm, 649 PatFrag opnode> { 650 def i : // reg/imm5 651 T1pILdStEncodeImm<imm_opc, 0 /* Store */, 652 (outs), (ins tGPR:$Rt, AddrMode_i:$addr), 653 am, itin_i, asm, "\t$Rt, $addr", 654 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>; 655 def r : // reg/reg 656 T1pILdStEncode<reg_opc, 657 (outs), (ins tGPR:$Rt, AddrMode_r:$addr), 658 am, itin_r, asm, "\t$Rt, $addr", 659 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>; 660} 661 662// A8.6.57 & A8.6.60 663defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rr, 664 t_addrmode_is4, AddrModeT1_4, 665 IIC_iLoad_r, IIC_iLoad_i, "ldr", 666 UnOpFrag<(load node:$Src)>>; 667 668// A8.6.64 & A8.6.61 669defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rr, 670 t_addrmode_is1, AddrModeT1_1, 671 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb", 672 UnOpFrag<(zextloadi8 node:$Src)>>; 673 674// A8.6.76 & A8.6.73 675defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rr, 676 t_addrmode_is2, AddrModeT1_2, 677 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh", 678 UnOpFrag<(zextloadi16 node:$Src)>>; 679 680let AddedComplexity = 10 in 681def tLDRSB : // A8.6.80 682 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 683 AddrModeT1_1, IIC_iLoad_bh_r, 684 "ldrsb", "\t$Rt, $addr", 685 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>; 686 687let AddedComplexity = 10 in 688def tLDRSH : // A8.6.84 689 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 690 AddrModeT1_2, IIC_iLoad_bh_r, 691 "ldrsh", "\t$Rt, $addr", 692 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>; 693 694 695def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i, 696 "str", "\t$Rt, $addr", 697 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>, 698 T1LdStSP<{0,?,?}> { 699 bits<3> Rt; 700 bits<8> addr; 701 let Inst{10-8} = Rt; 702 let Inst{7-0} = addr; 703} 704 705// A8.6.194 & A8.6.192 706defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rr, 707 t_addrmode_is4, AddrModeT1_4, 708 IIC_iStore_r, IIC_iStore_i, "str", 709 BinOpFrag<(store node:$LHS, node:$RHS)>>; 710 711// A8.6.197 & A8.6.195 712defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rr, 713 t_addrmode_is1, AddrModeT1_1, 714 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb", 715 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 716 717// A8.6.207 & A8.6.205 718defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rr, 719 t_addrmode_is2, AddrModeT1_2, 720 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh", 721 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 722 723 724//===----------------------------------------------------------------------===// 725// Load / store multiple Instructions. 726// 727 728// These require base address to be written back or one of the loaded regs. 729let hasSideEffects = 0 in { 730 731let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 732def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 733 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> { 734 bits<3> Rn; 735 bits<8> regs; 736 let Inst{10-8} = Rn; 737 let Inst{7-0} = regs; 738} 739 740// Writeback version is just a pseudo, as there's no encoding difference. 741// Writeback happens iff the base register is not in the destination register 742// list. 743let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 744def tLDMIA_UPD : 745 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, 746 "$Rn = $wb", IIC_iLoad_mu>, 747 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> { 748 let Size = 2; 749 let OutOperandList = (outs GPR:$wb); 750 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops); 751 let Pattern = []; 752 let isCodeGenOnly = 1; 753 let isPseudo = 1; 754 list<Predicate> Predicates = [IsThumb]; 755} 756 757// There is no non-writeback version of STM for Thumb. 758let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 759def tSTMIA_UPD : Thumb1I<(outs GPR:$wb), 760 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 761 AddrModeNone, 2, IIC_iStore_mu, 762 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>, 763 T1Encoding<{1,1,0,0,0,?}> { 764 bits<3> Rn; 765 bits<8> regs; 766 let Inst{10-8} = Rn; 767 let Inst{7-0} = regs; 768} 769 770} // hasSideEffects 771 772def : InstAlias<"ldm${p} $Rn!, $regs", 773 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>, 774 Requires<[IsThumb, IsThumb1Only]>; 775 776let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in 777def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 778 IIC_iPop, 779 "pop${p}\t$regs", []>, 780 T1Misc<{1,1,0,?,?,?,?}> { 781 bits<16> regs; 782 let Inst{8} = regs{15}; 783 let Inst{7-0} = regs{7-0}; 784} 785 786let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in 787def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 788 IIC_iStore_m, 789 "push${p}\t$regs", []>, 790 T1Misc<{0,1,0,?,?,?,?}> { 791 bits<16> regs; 792 let Inst{8} = regs{14}; 793 let Inst{7-0} = regs{7-0}; 794} 795 796//===----------------------------------------------------------------------===// 797// Arithmetic Instructions. 798// 799 800// Helper classes for encoding T1pI patterns: 801class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 802 string opc, string asm, list<dag> pattern> 803 : T1pI<oops, iops, itin, opc, asm, pattern>, 804 T1DataProcessing<opA> { 805 bits<3> Rm; 806 bits<3> Rn; 807 let Inst{5-3} = Rm; 808 let Inst{2-0} = Rn; 809} 810class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin, 811 string opc, string asm, list<dag> pattern> 812 : T1pI<oops, iops, itin, opc, asm, pattern>, 813 T1Misc<opA> { 814 bits<3> Rm; 815 bits<3> Rd; 816 let Inst{5-3} = Rm; 817 let Inst{2-0} = Rd; 818} 819 820// Helper classes for encoding T1sI patterns: 821class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 822 string opc, string asm, list<dag> pattern> 823 : T1sI<oops, iops, itin, opc, asm, pattern>, 824 T1DataProcessing<opA> { 825 bits<3> Rd; 826 bits<3> Rn; 827 let Inst{5-3} = Rn; 828 let Inst{2-0} = Rd; 829} 830class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 831 string opc, string asm, list<dag> pattern> 832 : T1sI<oops, iops, itin, opc, asm, pattern>, 833 T1General<opA> { 834 bits<3> Rm; 835 bits<3> Rn; 836 bits<3> Rd; 837 let Inst{8-6} = Rm; 838 let Inst{5-3} = Rn; 839 let Inst{2-0} = Rd; 840} 841class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 842 string opc, string asm, list<dag> pattern> 843 : T1sI<oops, iops, itin, opc, asm, pattern>, 844 T1General<opA> { 845 bits<3> Rd; 846 bits<3> Rm; 847 let Inst{5-3} = Rm; 848 let Inst{2-0} = Rd; 849} 850 851// Helper classes for encoding T1sIt patterns: 852class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 853 string opc, string asm, list<dag> pattern> 854 : T1sIt<oops, iops, itin, opc, asm, pattern>, 855 T1DataProcessing<opA> { 856 bits<3> Rdn; 857 bits<3> Rm; 858 let Inst{5-3} = Rm; 859 let Inst{2-0} = Rdn; 860} 861class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 862 string opc, string asm, list<dag> pattern> 863 : T1sIt<oops, iops, itin, opc, asm, pattern>, 864 T1General<opA> { 865 bits<3> Rdn; 866 bits<8> imm8; 867 let Inst{10-8} = Rdn; 868 let Inst{7-0} = imm8; 869} 870 871// Add with carry register 872let isCommutable = 1, Uses = [CPSR] in 873def tADC : // A8.6.2 874 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr, 875 "adc", "\t$Rdn, $Rm", 876 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 877 878// Add immediate 879def tADDi3 : // A8.6.4 T1 880 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 881 IIC_iALUi, 882 "add", "\t$Rd, $Rm, $imm3", 883 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>, 884 Sched<[WriteALU]> { 885 bits<3> imm3; 886 let Inst{8-6} = imm3; 887} 888 889def tADDi8 : // A8.6.4 T2 890 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), 891 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 892 "add", "\t$Rdn, $imm8", 893 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>, 894 Sched<[WriteALU]>; 895 896// Add register 897let isCommutable = 1 in 898def tADDrr : // A8.6.6 T1 899 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 900 IIC_iALUr, 901 "add", "\t$Rd, $Rn, $Rm", 902 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 903 904let hasSideEffects = 0 in 905def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr, 906 "add", "\t$Rdn, $Rm", []>, 907 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 908 // A8.6.6 T2 909 bits<4> Rdn; 910 bits<4> Rm; 911 let Inst{7} = Rdn{3}; 912 let Inst{6-3} = Rm; 913 let Inst{2-0} = Rdn{2-0}; 914} 915 916// AND register 917let isCommutable = 1 in 918def tAND : // A8.6.12 919 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 920 IIC_iBITr, 921 "and", "\t$Rdn, $Rm", 922 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 923 924// ASR immediate 925def tASRri : // A8.6.14 926 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 927 IIC_iMOVsi, 928 "asr", "\t$Rd, $Rm, $imm5", 929 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>, 930 Sched<[WriteALU]> { 931 bits<5> imm5; 932 let Inst{10-6} = imm5; 933} 934 935// ASR register 936def tASRrr : // A8.6.15 937 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 938 IIC_iMOVsr, 939 "asr", "\t$Rdn, $Rm", 940 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 941 942// BIC register 943def tBIC : // A8.6.20 944 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 945 IIC_iBITr, 946 "bic", "\t$Rdn, $Rm", 947 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>, 948 Sched<[WriteALU]>; 949 950// CMN register 951let isCompare = 1, Defs = [CPSR] in { 952//FIXME: Disable CMN, as CCodes are backwards from compare expectations 953// Compare-to-zero still works out, just not the relationals 954//def tCMN : // A8.6.33 955// T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs), 956// IIC_iCMPr, 957// "cmn", "\t$lhs, $rhs", 958// [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>; 959 960def tCMNz : // A8.6.33 961 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm), 962 IIC_iCMPr, 963 "cmn", "\t$Rn, $Rm", 964 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>; 965 966} // isCompare = 1, Defs = [CPSR] 967 968// CMP immediate 969let isCompare = 1, Defs = [CPSR] in { 970def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi, 971 "cmp", "\t$Rn, $imm8", 972 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>, 973 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> { 974 // A8.6.35 975 bits<3> Rn; 976 bits<8> imm8; 977 let Inst{10-8} = Rn; 978 let Inst{7-0} = imm8; 979} 980 981// CMP register 982def tCMPr : // A8.6.36 T1 983 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm), 984 IIC_iCMPr, 985 "cmp", "\t$Rn, $Rm", 986 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>; 987 988def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr, 989 "cmp", "\t$Rn, $Rm", []>, 990 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> { 991 // A8.6.36 T2 992 bits<4> Rm; 993 bits<4> Rn; 994 let Inst{7} = Rn{3}; 995 let Inst{6-3} = Rm; 996 let Inst{2-0} = Rn{2-0}; 997} 998} // isCompare = 1, Defs = [CPSR] 999 1000 1001// XOR register 1002let isCommutable = 1 in 1003def tEOR : // A8.6.45 1004 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1005 IIC_iBITr, 1006 "eor", "\t$Rdn, $Rm", 1007 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1008 1009// LSL immediate 1010def tLSLri : // A8.6.88 1011 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5), 1012 IIC_iMOVsi, 1013 "lsl", "\t$Rd, $Rm, $imm5", 1014 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>, 1015 Sched<[WriteALU]> { 1016 bits<5> imm5; 1017 let Inst{10-6} = imm5; 1018} 1019 1020// LSL register 1021def tLSLrr : // A8.6.89 1022 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1023 IIC_iMOVsr, 1024 "lsl", "\t$Rdn, $Rm", 1025 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1026 1027// LSR immediate 1028def tLSRri : // A8.6.90 1029 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 1030 IIC_iMOVsi, 1031 "lsr", "\t$Rd, $Rm, $imm5", 1032 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>, 1033 Sched<[WriteALU]> { 1034 bits<5> imm5; 1035 let Inst{10-6} = imm5; 1036} 1037 1038// LSR register 1039def tLSRrr : // A8.6.91 1040 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1041 IIC_iMOVsr, 1042 "lsr", "\t$Rdn, $Rm", 1043 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1044 1045// Move register 1046let isMoveImm = 1 in 1047def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi, 1048 "mov", "\t$Rd, $imm8", 1049 [(set tGPR:$Rd, imm0_255:$imm8)]>, 1050 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> { 1051 // A8.6.96 1052 bits<3> Rd; 1053 bits<8> imm8; 1054 let Inst{10-8} = Rd; 1055 let Inst{7-0} = imm8; 1056} 1057// Because we have an explicit tMOVSr below, we need an alias to handle 1058// the immediate "movs" form here. Blech. 1059def : tInstAlias <"movs $Rdn, $imm", 1060 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>; 1061 1062// A7-73: MOV(2) - mov setting flag. 1063 1064let hasSideEffects = 0 in { 1065def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone, 1066 2, IIC_iMOVr, 1067 "mov", "\t$Rd, $Rm", "", []>, 1068 T1Special<{1,0,?,?}>, Sched<[WriteALU]> { 1069 // A8.6.97 1070 bits<4> Rd; 1071 bits<4> Rm; 1072 let Inst{7} = Rd{3}; 1073 let Inst{6-3} = Rm; 1074 let Inst{2-0} = Rd{2-0}; 1075} 1076let Defs = [CPSR] in 1077def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr, 1078 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> { 1079 // A8.6.97 1080 bits<3> Rd; 1081 bits<3> Rm; 1082 let Inst{15-6} = 0b0000000000; 1083 let Inst{5-3} = Rm; 1084 let Inst{2-0} = Rd; 1085} 1086} // hasSideEffects 1087 1088// Multiply register 1089let isCommutable = 1 in 1090def tMUL : // A8.6.105 T1 1091 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2, 1092 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd", 1093 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>, 1094 T1DataProcessing<0b1101> { 1095 bits<3> Rd; 1096 bits<3> Rn; 1097 let Inst{5-3} = Rn; 1098 let Inst{2-0} = Rd; 1099 let AsmMatchConverter = "cvtThumbMultiply"; 1100} 1101 1102def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn, 1103 pred:$p)>; 1104 1105// Move inverse register 1106def tMVN : // A8.6.107 1107 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr, 1108 "mvn", "\t$Rd, $Rn", 1109 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>; 1110 1111// Bitwise or register 1112let isCommutable = 1 in 1113def tORR : // A8.6.114 1114 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1115 IIC_iBITr, 1116 "orr", "\t$Rdn, $Rm", 1117 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1118 1119// Swaps 1120def tREV : // A8.6.134 1121 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1122 IIC_iUNAr, 1123 "rev", "\t$Rd, $Rm", 1124 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>, 1125 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1126 1127def tREV16 : // A8.6.135 1128 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1129 IIC_iUNAr, 1130 "rev16", "\t$Rd, $Rm", 1131 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>, 1132 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1133 1134def tREVSH : // A8.6.136 1135 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1136 IIC_iUNAr, 1137 "revsh", "\t$Rd, $Rm", 1138 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>, 1139 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1140 1141// Rotate right register 1142def tROR : // A8.6.139 1143 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1144 IIC_iMOVsr, 1145 "ror", "\t$Rdn, $Rm", 1146 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>, 1147 Sched<[WriteALU]>; 1148 1149// Negate register 1150def tRSB : // A8.6.141 1151 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn), 1152 IIC_iALUi, 1153 "rsb", "\t$Rd, $Rn, #0", 1154 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>; 1155 1156// Subtract with carry register 1157let Uses = [CPSR] in 1158def tSBC : // A8.6.151 1159 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1160 IIC_iALUr, 1161 "sbc", "\t$Rdn, $Rm", 1162 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>, 1163 Sched<[WriteALU]>; 1164 1165// Subtract immediate 1166def tSUBi3 : // A8.6.210 T1 1167 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 1168 IIC_iALUi, 1169 "sub", "\t$Rd, $Rm, $imm3", 1170 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>, 1171 Sched<[WriteALU]> { 1172 bits<3> imm3; 1173 let Inst{8-6} = imm3; 1174} 1175 1176def tSUBi8 : // A8.6.210 T2 1177 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), 1178 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 1179 "sub", "\t$Rdn, $imm8", 1180 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>, 1181 Sched<[WriteALU]>; 1182 1183// Subtract register 1184def tSUBrr : // A8.6.212 1185 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 1186 IIC_iALUr, 1187 "sub", "\t$Rd, $Rn, $Rm", 1188 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>, 1189 Sched<[WriteALU]>; 1190 1191// Sign-extend byte 1192def tSXTB : // A8.6.222 1193 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1194 IIC_iUNAr, 1195 "sxtb", "\t$Rd, $Rm", 1196 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>, 1197 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1198 Sched<[WriteALU]>; 1199 1200// Sign-extend short 1201def tSXTH : // A8.6.224 1202 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1203 IIC_iUNAr, 1204 "sxth", "\t$Rd, $Rm", 1205 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>, 1206 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1207 Sched<[WriteALU]>; 1208 1209// Test 1210let isCompare = 1, isCommutable = 1, Defs = [CPSR] in 1211def tTST : // A8.6.230 1212 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr, 1213 "tst", "\t$Rn, $Rm", 1214 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>, 1215 Sched<[WriteALU]>; 1216 1217// A8.8.247 UDF - Undefined (Encoding T1) 1218def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8", 1219 [(int_arm_undefined imm0_255:$imm8)]>, Encoding16 { 1220 bits<8> imm8; 1221 let Inst{15-12} = 0b1101; 1222 let Inst{11-8} = 0b1110; 1223 let Inst{7-0} = imm8; 1224} 1225 1226// Zero-extend byte 1227def tUXTB : // A8.6.262 1228 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1229 IIC_iUNAr, 1230 "uxtb", "\t$Rd, $Rm", 1231 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>, 1232 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1233 Sched<[WriteALU]>; 1234 1235// Zero-extend short 1236def tUXTH : // A8.6.264 1237 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1238 IIC_iUNAr, 1239 "uxth", "\t$Rd, $Rm", 1240 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>, 1241 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1242 1243// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation. 1244// Expanded after instruction selection into a branch sequence. 1245let usesCustomInserter = 1 in // Expanded after instruction selection. 1246 def tMOVCCr_pseudo : 1247 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, cmovpred:$p), 1248 NoItinerary, 1249 [(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, cmovpred:$p))]>; 1250 1251// tLEApcrel - Load a pc-relative address into a register without offending the 1252// assembler. 1253 1254def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p), 1255 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>, 1256 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> { 1257 bits<3> Rd; 1258 bits<8> addr; 1259 let Inst{10-8} = Rd; 1260 let Inst{7-0} = addr; 1261 let DecoderMethod = "DecodeThumbAddSpecialReg"; 1262} 1263 1264let hasSideEffects = 0, isReMaterializable = 1 in 1265def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), 1266 2, IIC_iALUi, []>, Sched<[WriteALU]>; 1267 1268let hasSideEffects = 1 in 1269def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd), 1270 (ins i32imm:$label, pred:$p), 1271 2, IIC_iALUi, []>, Sched<[WriteALU]>; 1272 1273//===----------------------------------------------------------------------===// 1274// TLS Instructions 1275// 1276 1277// __aeabi_read_tp preserves the registers r1-r3. 1278// This is a pseudo inst so that we can get the encoding right, 1279// complete with fixup for the aeabi_read_tp function. 1280let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in 1281def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br, 1282 [(set R0, ARMthread_pointer)]>, 1283 Sched<[WriteBr]>; 1284 1285//===----------------------------------------------------------------------===// 1286// SJLJ Exception handling intrinsics 1287// 1288 1289// eh_sjlj_setjmp() is an instruction sequence to store the return address and 1290// save #0 in R0 for the non-longjmp case. Since by its nature we may be coming 1291// from some other function to get here, and we're using the stack frame for the 1292// containing function to save/restore registers, we can't keep anything live in 1293// regs across the eh_sjlj_setjmp(), else it will almost certainly have been 1294// tromped upon when we get here from a longjmp(). We force everything out of 1295// registers except for our own input by listing the relevant registers in 1296// Defs. By doing so, we also cause the prologue/epilogue code to actively 1297// preserve all of the callee-saved resgisters, which is exactly what we want. 1298// $val is a scratch register for our use. 1299let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ], 1300 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 1301 usesCustomInserter = 1 in 1302def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val), 1303 AddrModeNone, 0, NoItinerary, "","", 1304 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>; 1305 1306// FIXME: Non-IOS version(s) 1307let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, 1308 Defs = [ R7, LR, SP ] in 1309def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), 1310 AddrModeNone, 0, IndexModeNone, 1311 Pseudo, NoItinerary, "", "", 1312 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 1313 Requires<[IsThumb]>; 1314 1315//===----------------------------------------------------------------------===// 1316// Non-Instruction Patterns 1317// 1318 1319// Comparisons 1320def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8), 1321 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>; 1322def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm), 1323 (tCMPr tGPR:$Rn, tGPR:$Rm)>; 1324 1325// Add with carry 1326def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs), 1327 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>; 1328def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs), 1329 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>; 1330def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs), 1331 (tADDrr tGPR:$lhs, tGPR:$rhs)>; 1332 1333// Subtract with carry 1334def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs), 1335 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>; 1336def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs), 1337 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>; 1338def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs), 1339 (tSUBrr tGPR:$lhs, tGPR:$rhs)>; 1340 1341// Bswap 16 with load/store 1342def : T1Pat<(srl (bswap (extloadi16 t_addrmode_is2:$addr)), (i32 16)), 1343 (tREV16 (tLDRHi t_addrmode_is2:$addr))>; 1344def : T1Pat<(srl (bswap (extloadi16 t_addrmode_rr:$addr)), (i32 16)), 1345 (tREV16 (tLDRHr t_addrmode_rr:$addr))>; 1346def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)), 1347 t_addrmode_is2:$addr), 1348 (tSTRHi(tREV16 tGPR:$Rn), t_addrmode_is2:$addr)>; 1349def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)), 1350 t_addrmode_rr:$addr), 1351 (tSTRHr (tREV16 tGPR:$Rn), t_addrmode_rr:$addr)>; 1352 1353// ConstantPool 1354def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; 1355 1356// GlobalAddress 1357def tLDRLIT_ga_pcrel : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr), 1358 IIC_iLoadiALU, 1359 [(set tGPR:$dst, 1360 (ARMWrapperPIC tglobaladdr:$addr))]>, 1361 Requires<[IsThumb, DontUseMovt]>; 1362 1363def tLDRLIT_ga_abs : PseudoInst<(outs tGPR:$dst), (ins i32imm:$src), 1364 IIC_iLoad_i, 1365 [(set tGPR:$dst, 1366 (ARMWrapper tglobaladdr:$src))]>, 1367 Requires<[IsThumb, DontUseMovt]>; 1368 1369 1370// JumpTable 1371def : T1Pat<(ARMWrapperJT tjumptable:$dst), 1372 (tLEApcrelJT tjumptable:$dst)>; 1373 1374// Direct calls 1375def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>, 1376 Requires<[IsThumb]>; 1377 1378def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>, 1379 Requires<[IsThumb, HasV5T, IsNotMClass]>; 1380 1381// Indirect calls to ARM routines 1382def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>, 1383 Requires<[IsThumb, HasV5T]>; 1384 1385// zextload i1 -> zextload i8 1386def : T1Pat<(zextloadi1 t_addrmode_is1:$addr), 1387 (tLDRBi t_addrmode_is1:$addr)>; 1388def : T1Pat<(zextloadi1 t_addrmode_rr:$addr), 1389 (tLDRBr t_addrmode_rr:$addr)>; 1390 1391// extload from the stack -> word load from the stack, as it avoids having to 1392// materialize the base in a separate register. This only works when a word 1393// load puts the byte/halfword value in the same place in the register that the 1394// byte/halfword load would, i.e. when little-endian. 1395def : T1Pat<(extloadi1 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>, 1396 Requires<[IsThumb, IsThumb1Only, IsLE]>; 1397def : T1Pat<(extloadi8 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>, 1398 Requires<[IsThumb, IsThumb1Only, IsLE]>; 1399def : T1Pat<(extloadi16 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>, 1400 Requires<[IsThumb, IsThumb1Only, IsLE]>; 1401 1402// extload -> zextload 1403def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1404def : T1Pat<(extloadi1 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>; 1405def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1406def : T1Pat<(extloadi8 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>; 1407def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>; 1408def : T1Pat<(extloadi16 t_addrmode_rr:$addr), (tLDRHr t_addrmode_rr:$addr)>; 1409 1410// If it's impossible to use [r,r] address mode for sextload, select to 1411// ldr{b|h} + sxt{b|h} instead. 1412def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1413 (tSXTB (tLDRBi t_addrmode_is1:$addr))>, 1414 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1415def : T1Pat<(sextloadi8 t_addrmode_rr:$addr), 1416 (tSXTB (tLDRBr t_addrmode_rr:$addr))>, 1417 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1418def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1419 (tSXTH (tLDRHi t_addrmode_is2:$addr))>, 1420 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1421def : T1Pat<(sextloadi16 t_addrmode_rr:$addr), 1422 (tSXTH (tLDRHr t_addrmode_rr:$addr))>, 1423 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1424 1425def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1426 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>; 1427def : T1Pat<(sextloadi8 t_addrmode_rr:$addr), 1428 (tASRri (tLSLri (tLDRBr t_addrmode_rr:$addr), 24), 24)>; 1429def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1430 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>; 1431def : T1Pat<(sextloadi16 t_addrmode_rr:$addr), 1432 (tASRri (tLSLri (tLDRHr t_addrmode_rr:$addr), 16), 16)>; 1433 1434def : T1Pat<(atomic_load_8 t_addrmode_is1:$src), 1435 (tLDRBi t_addrmode_is1:$src)>; 1436def : T1Pat<(atomic_load_8 t_addrmode_rr:$src), 1437 (tLDRBr t_addrmode_rr:$src)>; 1438def : T1Pat<(atomic_load_16 t_addrmode_is2:$src), 1439 (tLDRHi t_addrmode_is2:$src)>; 1440def : T1Pat<(atomic_load_16 t_addrmode_rr:$src), 1441 (tLDRHr t_addrmode_rr:$src)>; 1442def : T1Pat<(atomic_load_32 t_addrmode_is4:$src), 1443 (tLDRi t_addrmode_is4:$src)>; 1444def : T1Pat<(atomic_load_32 t_addrmode_rr:$src), 1445 (tLDRr t_addrmode_rr:$src)>; 1446def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val), 1447 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>; 1448def : T1Pat<(atomic_store_8 t_addrmode_rr:$ptr, tGPR:$val), 1449 (tSTRBr tGPR:$val, t_addrmode_rr:$ptr)>; 1450def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val), 1451 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>; 1452def : T1Pat<(atomic_store_16 t_addrmode_rr:$ptr, tGPR:$val), 1453 (tSTRHr tGPR:$val, t_addrmode_rr:$ptr)>; 1454def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val), 1455 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>; 1456def : T1Pat<(atomic_store_32 t_addrmode_rr:$ptr, tGPR:$val), 1457 (tSTRr tGPR:$val, t_addrmode_rr:$ptr)>; 1458 1459// Large immediate handling. 1460 1461// Two piece imms. 1462def : T1Pat<(i32 thumb_immshifted:$src), 1463 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), 1464 (thumb_immshifted_shamt imm:$src))>; 1465 1466def : T1Pat<(i32 imm0_255_comp:$src), 1467 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; 1468 1469// Pseudo instruction that combines ldr from constpool and add pc. This should 1470// be expanded into two instructions late to allow if-conversion and 1471// scheduling. 1472let isReMaterializable = 1 in 1473def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 1474 NoItinerary, 1475 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 1476 imm:$cp))]>, 1477 Requires<[IsThumb, IsThumb1Only]>; 1478 1479// Pseudo-instruction for merged POP and return. 1480// FIXME: remove when we have a way to marking a MI with these properties. 1481let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 1482 hasExtraDefRegAllocReq = 1 in 1483def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops), 1484 2, IIC_iPop_Br, [], 1485 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>; 1486 1487// Indirect branch using "mov pc, $Rm" 1488let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1489 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p), 1490 2, IIC_Br, [(brind GPR:$Rm)], 1491 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>; 1492} 1493 1494 1495// In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00 1496// encoding is available on ARMv6K, but we don't differentiate that finely. 1497def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>; 1498 1499 1500// For round-trip assembly/disassembly, we have to handle a CPS instruction 1501// without any iflags. That's not, strictly speaking, valid syntax, but it's 1502// a useful extension and assembles to defined behaviour (the insn does 1503// nothing). 1504def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1505def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1506 1507// "neg" is and alias for "rsb rd, rn, #0" 1508def : tInstAlias<"neg${s}${p} $Rd, $Rm", 1509 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>; 1510 1511 1512// Implied destination operand forms for shifts. 1513def : tInstAlias<"lsl${s}${p} $Rdm, $imm", 1514 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>; 1515def : tInstAlias<"lsr${s}${p} $Rdm, $imm", 1516 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1517def : tInstAlias<"asr${s}${p} $Rdm, $imm", 1518 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1519