1let isCodeGenOnly = 1, Predicates = [InMicroMips] in {
2def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
3                ADDS_FM_MM<0, 0x30>;
4def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
5                ADDS_FM_MM<0, 0xf0>;
6def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
7                ADDS_FM_MM<0, 0xb0>;
8def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
9                ADDS_FM_MM<0, 0x70>;
10
11def FADD_MM  : MMRel, ADDS_FT<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>,
12               ADDS_FM_MM<1, 0x30>;
13def FDIV_MM  : MMRel, ADDS_FT<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>,
14               ADDS_FM_MM<1, 0xf0>;
15def FMUL_MM  : MMRel, ADDS_FT<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>,
16               ADDS_FM_MM<1, 0xb0>;
17def FSUB_MM  : MMRel, ADDS_FT<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>,
18               ADDS_FM_MM<1, 0x70>;
19
20def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM_MM<0x27>;
21def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>,
22              LW_FM_MM<0x26>;
23def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM_MM<0x2f>;
24def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>,
25              LW_FM_MM<0x2e>;
26def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>,
27               LWXC1_FM_MM<0x48>, INSN_MIPS4_32R2_NOT_32R6_64R6;
28def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>,
29               SWXC1_FM_MM<0x88>, INSN_MIPS4_32R2_NOT_32R6_64R6;
30def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>,
31               LWXC1_FM_MM<0x148>, INSN_MIPS5_32R2_NOT_32R6_64R6;
32def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>,
33               SWXC1_FM_MM<0x188>, INSN_MIPS5_32R2_NOT_32R6_64R6;
34
35def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>,
36                  CEQS_FM_MM<0>;
37def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>,
38                  CEQS_FM_MM<1>;
39
40def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>,
41              BC1F_FM_MM<0x1c>, ISA_MIPS1_NOT_32R6_64R6;
42def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>,
43              BC1F_FM_MM<0x1d>, ISA_MIPS1_NOT_32R6_64R6;
44def CVT_W_S_MM   : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
45                   ROUND_W_FM_MM<0, 0x24>;
46def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
47                   ROUND_W_FM_MM<0, 0xec>;
48
49def CEIL_W_MM  : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>,
50                 ROUND_W_FM_MM<1, 0x6c>;
51def CVT_W_MM   : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
52                 ROUND_W_FM_MM<1, 0x24>;
53def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>,
54                 ROUND_W_FM_MM<1, 0x2c>;
55def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, II_ROUND>,
56                 ROUND_W_FM_MM<1, 0xec>;
57def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>,
58                 ROUND_W_FM_MM<1, 0xac>;
59
60def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd, II_SQRT_D,
61                              fsqrt>, ROUND_W_FM_MM<1, 0x28>;
62
63def CVT_L_S_MM   : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
64                   ROUND_W_FM_MM<0, 0x4>, INSN_MIPS3_32R2;
65def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
66                   ROUND_W_FM_MM<1, 0x4>, INSN_MIPS3_32R2;
67
68def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
69                ABS_FM_MM<0, 0xd>;
70def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
71                ABS_FM_MM<0, 0x1>;
72def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
73                ABS_FM_MM<0, 0x2d>;
74def CVT_D_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
75                 ABS_FM_MM<0, 0x4d>;
76def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
77                   ABS_FM_MM<1, 0x4d>;
78def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
79                   ABS_FM_MM<0, 0x6d>;
80def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
81                 ABS_FM_MM<1, 0x6d>;
82
83def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, II_ABS, fabs>,
84              ABS_FM_MM<1, 0xd>;
85def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>,
86              ABS_FM_MM<1, 0x2d>;
87
88def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
89                  ABS_FM_MM<1, 0x1>, FGR_32;
90
91def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd,
92                                     II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>;
93def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd,
94                                     II_MOVN_S>, CMov_I_F_FM_MM<0x38, 0>;
95def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
96                                       II_MOVZ_D>, CMov_I_F_FM_MM<0x78, 1>;
97def MOVN_I_D32_MM : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
98                                       II_MOVN_D>, CMov_I_F_FM_MM<0x38, 1>;
99
100def MOVT_S_MM : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S,
101                                   MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 0>;
102def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S,
103                                   MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 0>;
104def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
105                                     MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>;
106def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
107                                     MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>;
108
109def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>,
110              MFC1_FM_MM<0x40>;
111def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>,
112              MFC1_FM_MM<0x60>;
113def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd,
114                             II_MFC1, bitconvert>, MFC1_FM_MM<0x80>;
115def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
116                             II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>;
117def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
118               MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32;
119def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
120               MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32;
121
122def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
123                MADDS_FM_MM<0x1>;
124def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
125                MADDS_FM_MM<0x21>;
126def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
127                 MADDS_FM_MM<0x2>;
128def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
129                 MADDS_FM_MM<0x22>;
130
131def MADD_D32_MM  : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
132                   MADDS_FM_MM<0x9>;
133def MSUB_D32_MM  : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
134                   MADDS_FM_MM<0x29>;
135def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
136                   MADDS_FM_MM<0xa>;
137def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
138                   MADDS_FM_MM<0x2a>;
139}
140
141let AdditionalPredicates = [InMicroMips] in {
142  def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd,
143    II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>;
144  def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd,
145    FGR32Opnd, II_TRUNC>, ROUND_W_FM_MM<0, 0xac>;
146  def CEIL_W_S_MM  : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
147    ROUND_W_FM_MM<0, 0x6c>;
148  def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S,
149    fsqrt>, ROUND_W_FM_MM<0, 0x28>;
150}
151