1 //===-- MipsSERegisterInfo.cpp - MIPS32/64 Register Information -== -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS32/64 implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "MipsSERegisterInfo.h"
16 #include "Mips.h"
17 #include "MipsAnalyzeImmediate.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSEInstrInfo.h"
20 #include "MipsSubtarget.h"
21 #include "MipsTargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/IR/Constants.h"
29 #include "llvm/IR/DebugInfo.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/Type.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
40
41 using namespace llvm;
42
43 #define DEBUG_TYPE "mips-reg-info"
44
MipsSERegisterInfo()45 MipsSERegisterInfo::MipsSERegisterInfo() : MipsRegisterInfo() {}
46
47 bool MipsSERegisterInfo::
requiresRegisterScavenging(const MachineFunction & MF) const48 requiresRegisterScavenging(const MachineFunction &MF) const {
49 return true;
50 }
51
52 bool MipsSERegisterInfo::
requiresFrameIndexScavenging(const MachineFunction & MF) const53 requiresFrameIndexScavenging(const MachineFunction &MF) const {
54 return true;
55 }
56
57 const TargetRegisterClass *
intRegClass(unsigned Size) const58 MipsSERegisterInfo::intRegClass(unsigned Size) const {
59 if (Size == 4)
60 return &Mips::GPR32RegClass;
61
62 assert(Size == 8);
63 return &Mips::GPR64RegClass;
64 }
65
66 /// Get the size of the offset supported by the given load/store.
67 /// The result includes the effects of any scale factors applied to the
68 /// instruction immediate.
getLoadStoreOffsetSizeInBits(const unsigned Opcode)69 static inline unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode) {
70 switch (Opcode) {
71 case Mips::LD_B:
72 case Mips::ST_B:
73 return 10;
74 case Mips::LD_H:
75 case Mips::ST_H:
76 return 10 + 1 /* scale factor */;
77 case Mips::LD_W:
78 case Mips::ST_W:
79 return 10 + 2 /* scale factor */;
80 case Mips::LD_D:
81 case Mips::ST_D:
82 return 10 + 3 /* scale factor */;
83 default:
84 return 16;
85 }
86 }
87
88 /// Get the scale factor applied to the immediate in the given load/store.
getLoadStoreOffsetAlign(const unsigned Opcode)89 static inline unsigned getLoadStoreOffsetAlign(const unsigned Opcode) {
90 switch (Opcode) {
91 case Mips::LD_H:
92 case Mips::ST_H:
93 return 2;
94 case Mips::LD_W:
95 case Mips::ST_W:
96 return 4;
97 case Mips::LD_D:
98 case Mips::ST_D:
99 return 8;
100 default:
101 return 1;
102 }
103 }
104
eliminateFI(MachineBasicBlock::iterator II,unsigned OpNo,int FrameIndex,uint64_t StackSize,int64_t SPOffset) const105 void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
106 unsigned OpNo, int FrameIndex,
107 uint64_t StackSize,
108 int64_t SPOffset) const {
109 MachineInstr &MI = *II;
110 MachineFunction &MF = *MI.getParent()->getParent();
111 MachineFrameInfo *MFI = MF.getFrameInfo();
112 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
113
114 MipsABIInfo ABI =
115 static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI();
116 const MipsRegisterInfo *RegInfo =
117 static_cast<const MipsRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
118
119 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
120 int MinCSFI = 0;
121 int MaxCSFI = -1;
122
123 if (CSI.size()) {
124 MinCSFI = CSI[0].getFrameIdx();
125 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
126 }
127
128 bool EhDataRegFI = MipsFI->isEhDataRegFI(FrameIndex);
129 bool IsISRRegFI = MipsFI->isISRRegFI(FrameIndex);
130 // The following stack frame objects are always referenced relative to $sp:
131 // 1. Outgoing arguments.
132 // 2. Pointer to dynamically allocated stack space.
133 // 3. Locations for callee-saved registers.
134 // 4. Locations for eh data registers.
135 // 5. Locations for ISR saved Coprocessor 0 registers 12 & 14.
136 // Everything else is referenced relative to whatever register
137 // getFrameRegister() returns.
138 unsigned FrameReg;
139
140 if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI ||
141 IsISRRegFI)
142 FrameReg = ABI.GetStackPtr();
143 else if (RegInfo->needsStackRealignment(MF)) {
144 if (MFI->hasVarSizedObjects() && !MFI->isFixedObjectIndex(FrameIndex))
145 FrameReg = ABI.GetBasePtr();
146 else if (MFI->isFixedObjectIndex(FrameIndex))
147 FrameReg = getFrameRegister(MF);
148 else
149 FrameReg = ABI.GetStackPtr();
150 } else
151 FrameReg = getFrameRegister(MF);
152
153 // Calculate final offset.
154 // - There is no need to change the offset if the frame object is one of the
155 // following: an outgoing argument, pointer to a dynamically allocated
156 // stack space or a $gp restore location,
157 // - If the frame object is any of the following, its offset must be adjusted
158 // by adding the size of the stack:
159 // incoming argument, callee-saved register location or local variable.
160 bool IsKill = false;
161 int64_t Offset;
162
163 Offset = SPOffset + (int64_t)StackSize;
164 Offset += MI.getOperand(OpNo + 1).getImm();
165
166 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
167
168 if (!MI.isDebugValue()) {
169 // Make sure Offset fits within the field available.
170 // For MSA instructions, this is a 10-bit signed immediate (scaled by
171 // element size), otherwise it is a 16-bit signed immediate.
172 unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits(MI.getOpcode());
173 unsigned OffsetAlign = getLoadStoreOffsetAlign(MI.getOpcode());
174
175 if (OffsetBitSize < 16 && isInt<16>(Offset) &&
176 (!isIntN(OffsetBitSize, Offset) ||
177 OffsetToAlignment(Offset, OffsetAlign) != 0)) {
178 // If we have an offset that needs to fit into a signed n-bit immediate
179 // (where n < 16) and doesn't, but does fit into 16-bits then use an ADDiu
180 MachineBasicBlock &MBB = *MI.getParent();
181 DebugLoc DL = II->getDebugLoc();
182 const TargetRegisterClass *PtrRC =
183 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
184 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
185 unsigned Reg = RegInfo.createVirtualRegister(PtrRC);
186 const MipsSEInstrInfo &TII =
187 *static_cast<const MipsSEInstrInfo *>(
188 MBB.getParent()->getSubtarget().getInstrInfo());
189 BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAddiuOp()), Reg)
190 .addReg(FrameReg)
191 .addImm(Offset);
192
193 FrameReg = Reg;
194 Offset = 0;
195 IsKill = true;
196 } else if (!isInt<16>(Offset)) {
197 // Otherwise split the offset into 16-bit pieces and add it in multiple
198 // instructions.
199 MachineBasicBlock &MBB = *MI.getParent();
200 DebugLoc DL = II->getDebugLoc();
201 unsigned NewImm = 0;
202 const MipsSEInstrInfo &TII =
203 *static_cast<const MipsSEInstrInfo *>(
204 MBB.getParent()->getSubtarget().getInstrInfo());
205 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL,
206 OffsetBitSize == 16 ? &NewImm : nullptr);
207 BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAdduOp()), Reg).addReg(FrameReg)
208 .addReg(Reg, RegState::Kill);
209
210 FrameReg = Reg;
211 Offset = SignExtend64<16>(NewImm);
212 IsKill = true;
213 }
214 }
215
216 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
217 MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
218 }
219