1 //===-- SparcRegisterInfo.cpp - SPARC Register Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the SPARC implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "SparcRegisterInfo.h"
15 #include "Sparc.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "SparcSubtarget.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/IR/Type.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27
28 using namespace llvm;
29
30 #define GET_REGINFO_TARGET_DESC
31 #include "SparcGenRegisterInfo.inc"
32
33 static cl::opt<bool>
34 ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
35 cl::desc("Reserve application registers (%g2-%g4)"));
36
SparcRegisterInfo()37 SparcRegisterInfo::SparcRegisterInfo() : SparcGenRegisterInfo(SP::O7) {}
38
39 const MCPhysReg*
getCalleeSavedRegs(const MachineFunction * MF) const40 SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
41 return CSR_SaveList;
42 }
43
44 const uint32_t *
getCallPreservedMask(const MachineFunction & MF,CallingConv::ID CC) const45 SparcRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
46 CallingConv::ID CC) const {
47 return CSR_RegMask;
48 }
49
50 const uint32_t*
getRTCallPreservedMask(CallingConv::ID CC) const51 SparcRegisterInfo::getRTCallPreservedMask(CallingConv::ID CC) const {
52 return RTCSR_RegMask;
53 }
54
getReservedRegs(const MachineFunction & MF) const55 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
56 BitVector Reserved(getNumRegs());
57 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
58 // FIXME: G1 reserved for now for large imm generation by frame code.
59 Reserved.set(SP::G1);
60
61 // G1-G4 can be used in applications.
62 if (ReserveAppRegisters) {
63 Reserved.set(SP::G2);
64 Reserved.set(SP::G3);
65 Reserved.set(SP::G4);
66 }
67 // G5 is not reserved in 64 bit mode.
68 if (!Subtarget.is64Bit())
69 Reserved.set(SP::G5);
70
71 Reserved.set(SP::O6);
72 Reserved.set(SP::I6);
73 Reserved.set(SP::I7);
74 Reserved.set(SP::G0);
75 Reserved.set(SP::G6);
76 Reserved.set(SP::G7);
77
78 // Also reserve the register pair aliases covering the above
79 // registers, with the same conditions.
80 Reserved.set(SP::G0_G1);
81 if (ReserveAppRegisters)
82 Reserved.set(SP::G2_G3);
83 if (ReserveAppRegisters || !Subtarget.is64Bit())
84 Reserved.set(SP::G4_G5);
85
86 Reserved.set(SP::O6_O7);
87 Reserved.set(SP::I6_I7);
88 Reserved.set(SP::G6_G7);
89
90 // Unaliased double registers are not available in non-V9 targets.
91 if (!Subtarget.isV9()) {
92 for (unsigned n = 0; n != 16; ++n) {
93 for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI)
94 Reserved.set(*AI);
95 }
96 }
97
98 return Reserved;
99 }
100
101 const TargetRegisterClass*
getPointerRegClass(const MachineFunction & MF,unsigned Kind) const102 SparcRegisterInfo::getPointerRegClass(const MachineFunction &MF,
103 unsigned Kind) const {
104 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
105 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
106 }
107
replaceFI(MachineFunction & MF,MachineBasicBlock::iterator II,MachineInstr & MI,DebugLoc dl,unsigned FIOperandNum,int Offset,unsigned FramePtr)108 static void replaceFI(MachineFunction &MF,
109 MachineBasicBlock::iterator II,
110 MachineInstr &MI,
111 DebugLoc dl,
112 unsigned FIOperandNum, int Offset,
113 unsigned FramePtr)
114 {
115 // Replace frame index with a frame pointer reference.
116 if (Offset >= -4096 && Offset <= 4095) {
117 // If the offset is small enough to fit in the immediate field, directly
118 // encode it.
119 MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
120 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
121 return;
122 }
123
124 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
125
126 // FIXME: it would be better to scavenge a register here instead of
127 // reserving G1 all of the time.
128 if (Offset >= 0) {
129 // Emit nonnegaive immediates with sethi + or.
130 // sethi %hi(Offset), %g1
131 // add %g1, %fp, %g1
132 // Insert G1+%lo(offset) into the user.
133 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
134 .addImm(HI22(Offset));
135
136
137 // Emit G1 = G1 + I6
138 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
139 .addReg(FramePtr);
140 // Insert: G1+%lo(offset) into the user.
141 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
142 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(LO10(Offset));
143 return;
144 }
145
146 // Emit Negative numbers with sethi + xor
147 // sethi %hix(Offset), %g1
148 // xor %g1, %lox(offset), %g1
149 // add %g1, %fp, %g1
150 // Insert: G1 + 0 into the user.
151 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
152 .addImm(HIX22(Offset));
153 BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1)
154 .addReg(SP::G1).addImm(LOX10(Offset));
155
156 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
157 .addReg(FramePtr);
158 // Insert: G1+%lo(offset) into the user.
159 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
160 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
161 }
162
163
164 void
eliminateFrameIndex(MachineBasicBlock::iterator II,int SPAdj,unsigned FIOperandNum,RegScavenger * RS) const165 SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
166 int SPAdj, unsigned FIOperandNum,
167 RegScavenger *RS) const {
168 assert(SPAdj == 0 && "Unexpected");
169
170 MachineInstr &MI = *II;
171 DebugLoc dl = MI.getDebugLoc();
172 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
173 MachineFunction &MF = *MI.getParent()->getParent();
174 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
175 const SparcFrameLowering *TFI = getFrameLowering(MF);
176
177 unsigned FrameReg;
178 int Offset;
179 Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg);
180
181 Offset += MI.getOperand(FIOperandNum + 1).getImm();
182
183 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) {
184 if (MI.getOpcode() == SP::STQFri) {
185 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
186 unsigned SrcReg = MI.getOperand(2).getReg();
187 unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
188 unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
189 MachineInstr *StMI =
190 BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
191 .addReg(FrameReg).addImm(0).addReg(SrcEvenReg);
192 replaceFI(MF, II, *StMI, dl, 0, Offset, FrameReg);
193 MI.setDesc(TII.get(SP::STDFri));
194 MI.getOperand(2).setReg(SrcOddReg);
195 Offset += 8;
196 } else if (MI.getOpcode() == SP::LDQFri) {
197 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
198 unsigned DestReg = MI.getOperand(0).getReg();
199 unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64);
200 unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64);
201 MachineInstr *StMI =
202 BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)
203 .addReg(FrameReg).addImm(0);
204 replaceFI(MF, II, *StMI, dl, 1, Offset, FrameReg);
205
206 MI.setDesc(TII.get(SP::LDDFri));
207 MI.getOperand(0).setReg(DestOddReg);
208 Offset += 8;
209 }
210 }
211
212 replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FrameReg);
213
214 }
215
getFrameRegister(const MachineFunction & MF) const216 unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
217 return SP::I6;
218 }
219
220 // Sparc has no architectural need for stack realignment support,
221 // except that LLVM unfortunately currently implements overaligned
222 // stack objects by depending upon stack realignment support.
223 // If that ever changes, this can probably be deleted.
canRealignStack(const MachineFunction & MF) const224 bool SparcRegisterInfo::canRealignStack(const MachineFunction &MF) const {
225 if (!TargetRegisterInfo::canRealignStack(MF))
226 return false;
227
228 // Sparc always has a fixed frame pointer register, so don't need to
229 // worry about needing to reserve it. [even if we don't have a frame
230 // pointer for our frame, it still cannot be used for other things,
231 // or register window traps will be SADNESS.]
232
233 // If there's a reserved call frame, we can use SP to access locals.
234 if (getFrameLowering(MF)->hasReservedCallFrame(MF))
235 return true;
236
237 // Otherwise, we'd need a base pointer, but those aren't implemented
238 // for SPARC at the moment.
239
240 return false;
241 }
242