1; RUN: llc -mtriple=armv7k-apple-watchos2.0 -mcpu=cortex-a7 < %s | FileCheck %s
2
3define arm_aapcs_vfpcc float @t1(float %a, float %b) {
4entry:
5; CHECK: t1
6; CHECK-NOT: vmov
7; CHECK: vadd.f32
8  %a.addr = alloca float, align 4
9  %b.addr = alloca float, align 4
10  store float %a, float* %a.addr, align 4
11  store float %b, float* %b.addr, align 4
12  %0 = load float, float* %a.addr, align 4
13  %1 = load float, float* %b.addr, align 4
14  %add = fadd float %0, %1
15  ret float %add
16}
17
18define arm_aapcs_vfpcc double @t2(double %a, double %b) {
19entry:
20; CHECK: t2
21; CHECK-NOT: vmov
22; CHECK: vadd.f64
23  %a.addr = alloca double, align 8
24  %b.addr = alloca double, align 8
25  store double %a, double* %a.addr, align 8
26  store double %b, double* %b.addr, align 8
27  %0 = load double, double* %a.addr, align 8
28  %1 = load double, double* %b.addr, align 8
29  %add = fadd double %0, %1
30  ret double %add
31}
32
33define arm_aapcs_vfpcc i64 @t3(double %ti) {
34entry:
35; CHECK-LABEL: t3:
36; CHECK-NOT: vmov
37; CHECK: bl ___fixunsdfdi
38  %conv = fptoui double %ti to i64
39  ret i64 %conv
40}
41
42define arm_aapcs_vfpcc i64 @t4(double %ti) {
43entry:
44; CHECK-LABEL: t4:
45; CHECK-NOT: vmov
46; CHECK: bl ___fixdfdi
47  %conv = fptosi double %ti to i64
48  ret i64 %conv
49}
50
51define arm_aapcs_vfpcc double @t5(i64 %ti) {
52entry:
53; CHECK-LABEL: t5:
54; CHECK: bl ___floatundidf
55; CHECK-NOT: vmov
56; CHECK: pop
57  %conv = uitofp i64 %ti to double
58  ret double %conv
59}
60
61define arm_aapcs_vfpcc double @t6(i64 %ti) {
62entry:
63; CHECK-LABEL: t6:
64; CHECK: bl ___floatdidf
65; CHECK-NOT: vmov
66; CHECK: pop
67  %conv = sitofp i64 %ti to double
68  ret double %conv
69}
70
71define arm_aapcs_vfpcc float @t7(i64 %ti) {
72entry:
73; CHECK-LABEL: t7:
74; CHECK: bl ___floatundisf
75; CHECK-NOT: vmov
76; CHECK: pop
77  %conv = uitofp i64 %ti to float
78  ret float %conv
79}
80
81define arm_aapcs_vfpcc float @t8(i64 %ti) {
82entry:
83; CHECK-LABEL: t8:
84; CHECK: bl ___floatdisf
85; CHECK-NOT: vmov
86; CHECK: pop
87  %conv = sitofp i64 %ti to float
88  ret float %conv
89}
90
91define arm_aapcs_vfpcc double @t9(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, float %a, float %b) {
92entry:
93; CHECK-LABEL: t9:
94; CHECK-NOT: vmov
95; CHECK: vldr
96  %add = fadd float %a, %b
97  %conv = fpext float %add to double
98  ret double %conv
99}
100
101define arm_aapcs_vfpcc double @t10(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %a, float %b, double %c) {
102entry:
103; CHECK-LABEL: t10:
104; CHECK-NOT: vmov
105; CHECK: vldr
106  %add = fadd double %a, %c
107  ret double %add
108}
109
110define arm_aapcs_vfpcc float @t11(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, float %a, double %b, float %c) {
111entry:
112; CHECK-LABEL: t11:
113; CHECK: vldr
114  %add = fadd float %a, %c
115  ret float %add
116}
117
118; rdar://16039676
119define arm_aapcs_vfpcc double @t12(double %a, double %b) {
120entry:
121; CHECK-LABEL: t12:
122; CHECK: vstr
123  %add = fadd double %a, %b
124  %sub = fsub double %a, %b
125  %call = tail call arm_aapcs_vfpcc double @x(double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double %add, float 0.000000e+00, double %sub)
126  ret double %call
127}
128
129define arm_aapcs_vfpcc double @t13(double %x) {
130entry:
131; CHECK-LABEL: t13:
132; CHECK-NOT: vmov
133; CHECK: bl ___sincos_stret
134  %call = tail call arm_aapcs_vfpcc double @cos(double %x)
135  %call1 = tail call arm_aapcs_vfpcc double @sin(double %x)
136  %mul = fmul double %call, %call1
137  ret double %mul
138}
139
140define arm_aapcs_vfpcc double @t14(double %x) {
141; CHECK-LABEL: t14:
142; CHECK-NOT: vmov
143; CHECK: b ___exp10
144  %__exp10 = tail call double @__exp10(double %x) #1
145  ret double %__exp10
146}
147
148declare arm_aapcs_vfpcc double @x(double, double, double, double, double, double, double, float, double)
149declare arm_aapcs_vfpcc double @cos(double) #0
150declare arm_aapcs_vfpcc double @sin(double) #0
151declare double @__exp10(double)
152
153attributes #0 = { readnone }
154attributes #1 = { readonly }
155