1# RUN: llc -march=amdgcn -mcpu=SI -start-after postrapseudos -stop-after postrapseudos -o /dev/null %s | FileCheck %s
2# This test verifies that the MIR parser can parse target index operands.
3
4--- |
5
6  %struct.foo = type { float, [5 x i32] }
7
8  @float_gv = internal unnamed_addr addrspace(2) constant [5 x float] [float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00], align 4
9
10  define void @float(float addrspace(1)* %out, i32 %index) #0 {
11  entry:
12    %0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index
13    %1 = load float, float addrspace(2)* %0
14    store float %1, float addrspace(1)* %out
15    ret void
16  }
17
18  define void @float2(float addrspace(1)* %out, i32 %index) #0 {
19  entry:
20    %0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index
21    %1 = load float, float addrspace(2)* %0
22    store float %1, float addrspace(1)* %out
23    ret void
24  }
25
26  declare { i1, i64 } @llvm.SI.if(i1)
27
28  declare { i1, i64 } @llvm.SI.else(i64)
29
30  declare i64 @llvm.SI.break(i64)
31
32  declare i64 @llvm.SI.if.break(i1, i64)
33
34  declare i64 @llvm.SI.else.break(i64, i64)
35
36  declare i1 @llvm.SI.loop(i64)
37
38  declare void @llvm.SI.end.cf(i64)
39
40  attributes #0 = { "target-cpu"="SI" }
41
42...
43---
44name:            float
45tracksSubRegLiveness: true
46liveins:
47  - { reg: '%sgpr0_sgpr1' }
48frameInfo:
49  maxAlignment:  8
50body: |
51  bb.0.entry:
52    liveins: %sgpr0_sgpr1
53
54    %sgpr2_sgpr3 = S_GETPC_B64
55  ; CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc
56    %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc
57    %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
58    %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
59    %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11
60    %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
61    %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
62    %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
63    %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
64    %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
65    %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
66    %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0
67    %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9
68    %sgpr7 = S_MOV_B32 61440
69    %sgpr6 = S_MOV_B32 -1
70    %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
71    BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec
72    S_ENDPGM
73...
74---
75name:            float2
76tracksSubRegLiveness: true
77liveins:
78  - { reg: '%sgpr0_sgpr1' }
79frameInfo:
80  maxAlignment:  8
81body: |
82  bb.0.entry:
83    liveins: %sgpr0_sgpr1
84
85    %sgpr2_sgpr3 = S_GETPC_B64
86  ; CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc
87    %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc
88    %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
89    %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
90    %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11
91    %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
92    %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
93    %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
94    %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
95    %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
96    %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
97    %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0
98    %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9
99    %sgpr7 = S_MOV_B32 61440
100    %sgpr6 = S_MOV_B32 -1
101    %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
102    BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec
103    S_ENDPGM
104...
105